Abstract: A semiconductor device, comprising a semiconductor nanowire having a first region with one of a PN junction and a PIN junction and a second region with a field effect transistor structure, a pair of electrodes connected to both ends of the semiconductor nanowire, and a gate electrode provided in at least a part of the second region via an insulating layer. The semiconductor nanowire has a P-type semiconductor portion and an N-type semiconductor portion, and one of the P-type semiconductor portion and the N-type semiconductor portion is a common structural element of both the first and second regions.

Abstract: A technique for making a bulk isolated PN diode. Specifically, a technique is provided for making a voltage clamp with a pair of bulk isolated PN diode. Another embodiment provides for a voltage clamp with a pair of bulk isolated PN diodes in parallel with a pair of MOSFET diode-connected transistors. In addition, a method for manufacturing the bulk isolated PN diodes is recited.

Abstract: A technique for making a bulk isolated PN diode. Specifically, a technique is provided for making a voltage clamp with a pair of bulk isolated PN diode. Another embodiment provides for a voltage clamp with a pair of bulk isolated PN diodes in parallel with a pair of MOSFET diode-connected transistors. In addition, a method for manufacturing the bulk isolated PN diodes is recited.

Abstract: The invention relates to a sensor, especially for the probe of a screen probe microscope, for examining probe surfaces (40) or areas adjacent to the sensor, comprising at least one field effect transistor (FET) made of at least one semiconductor material. The invention also relates to a Hall sensor made of at least one semiconductor material for detecting magnetic fields and whose lateral resolution capacity can be electrically adjusted, in addition to a semiconductor electrode (28) whose electrode surface can be electrically adjusted.

Abstract: A semiconductor junction device includes a substrate of low resistivity semiconductor material having a preselected polarity. A tapered recess extends into the substrate and tapers inward as it extends downward from an upper surface of the substrate. A semiconductor layer is disposed within the recess and extends above the upper surface of the substrate. The semiconductor layer has a polarity opposite from that of the substrate. A metal layer overlies the semiconductor layer.

Abstract: Leakage current generated in a PN junction diode is reduced, and charge-up current caused by plasma treatment in formation of wiring connected to the PN junction diode is controlled. An N+ region as a first conductive type impurity region provided in a Si substrate with an upper surface being exposed on one main surface of the Si substrate, a P+ polysilicon plug provided with a bottom being contacted with an upper surface of the N+ region, and wiring connected to a top of the P+ polysilicon plug are included.

Abstract: A semiconductor device has a well region having a first conductivity type and formed in an upper portion of a semiconductor substrate, a gate insulating film and a gate electrode formed successively on the well region of the semiconductor substrate, a threshold voltage control layer for controlling a threshold voltage formed in the portion of the well region which is located below the gate electrode and in which an impurity of the first conductivity type has a concentration peak at a position shallower than in the well region, an extension region having a second conductivity type and formed in the well region to be located between each of the respective portions of the well region which are located below the both end portions in the gate-length direction of the gate electrode and the threshold voltage control layer, and source and drain regions each having the second conductivity type and formed outside the extension layer in connected relation thereto.

Abstract: The invention relates to a semiconductor component having a semiconductor body (100) and at least one pn junction present in the semiconductor body (100) and an amorphous passivation layer (70) arranged at least in sections on a surface (101) of the semiconductor body (100), the following holding true for the minimum Ds,min of an interface state density Ds at the junction between the passivation layer (70) and the semiconductor body (100): D s , min ? N S , Bd E g where NS,Bd is the breakdown charge and Eg is the band gap of the semiconductor material used for the semiconductor body (100).

Abstract: The present invention provides a semiconductor device having an active region bent at right angles, wherein an interval between patterns for the active region and a gate is set larger than an arc radius of a curved portion (portion where a line is brought to arcuate form) formed inside the pattern for the bent active region. By defining and designing the pattern interval, the curved portion of the active region do not overlap the gate pattern, and the difference between a device characteristic and a designed value can be prevented from increasing.

Abstract: An improved superjunction semiconductor device includes a charged balanced pylon in a body region, where a top of the pylon is large to create slight charge imbalance. A MOSgated structure is formed over the top of the pylon and designed to conduct current through the pylon. By increasing a dimension of the top of the pylon, the resulting device is less susceptible to variations in manufacturing tolerances to obtain a good breakdown voltage and improved device ruggedness.

Abstract: Formed on an insulator (9) are an N? type semiconductor layer (10) having a partial isolator formed on its surface and a P? type semiconductor layer (20) having a partial isolator formed on its surface. Source/drain (11, 12) being P+ type semiconductor layers are provided on the semiconductor layer (10) to form a PMOS transistor (1). Source/drain (21, 22) being N+ type semiconductor layers are provided on the semiconductor layer (20) to form an NMOS transistor (2). A pn junction (J5) formed by the semiconductor layers (10, 20) is provided in a CMOS transistor (100) made up of the transistors (1, 2). The pn junction (J5) is positioned separately from the partial isolators (41, 42), where the crystal defect is thus very small. Therefore, the leakage current is very low at the pn junction (J5).

Abstract: A method of making dielectrically isolated solid state device comprising state device (including integrated circuits) comprises providing a silicon wafer having a PN junction or other electronic rectifying barrier contained therein and thermally growing or ion-implanting selected ions to an oxide or nitride isolating groove in-situ to isolate it into a plurality of physically integral pockets for use as electrically separately operable components. The groove has a symmetrical, centrally rounded bottom which is located within a few microns below the PN junction or rectifying barrier. Through the unique oxide/nitride forming conditions and through curvature, symmetry, and proximity effects, novel passivation and isolation results obtain.

Abstract: A PN junction diode has a substrate 1 of a first conductivity type, and first and second stripe diffusion regions 2, 3 which are the first conductivity type and second conductivity type, respectively. The stripe diffusion regions are alternately arranged at a regular interval in a surface layer of the semiconductor substrate. The diode further includes first and second stripe electrodes 7a, 7b connected to the first and second diffusion regions along the longitudinal sides thereof, respectively. The diode further includes a third electrode 7b? which covers through an insulation film 5, 5? the neighboring ends of the first and second diffusion regions and of which a potential is equalized to that of the second electrode 7b having a different conductivity type from the substrate.

Abstract: A convex polycrystalline silicon film is formed on a handle wafer. A semiconductor layer is formed on the polycrystalline silicon film. The semiconductor is thinner on its areas in which the convex polycrystalline silicon film is formed and is thicker on its areas in which the convex polycrystalline silicon film is not formed. An opening is formed in each of those areas of an insulating film which are located under respective thick-film semiconductor areas of the semiconductor layer. The polycrystalline silicon film is formed in the openings to connect electrically the thick-film semiconductor areas and the handle wafer together.

Abstract: A semiconductor structure is disclosed that enhances quality control inspection of device. The structure includes a substrate having at least one planar face, a first metal layer on the planar face, and covering some, but not all of the planar face in a first predetermined geometric pattern, and a second metal layer on the planar face, and covering some, but not all of the planar face in a second geometric pattern that is different from the first geometric pattern. A quality control method for manufacturing a semiconductor device is also disclosed. The method includes the steps of placing a first metal layer on a semiconductor face of a device in a first predetermined geometric pattern, placing a second metal layer on the same face of the device as the first layer and in a second predetermined geometric pattern that is different from the first geometric pattern, and then inspecting the device to identify the presence or absence of one or both of the patterns on the face.

Abstract: A compensation component, in which a lateral section and, at least at one end of the lateral section, a section that is inclined with respect to the surface of a drift path, includes n-conducting and p-conducting regions completely embedded in a semiconductor body without a trench. In such a case, the inclined section is formed by ion implantation through an implantation mask with an inclined edge.

Abstract: A cold electron emitter may include a heavily a p-doped semiconductor, and dielectric layer, and a metallic layer (p-D-M structure). A modification of this structure includes a heavily n+ doped region below the p region (n+-p-D-M structure). These structures make it possible to combine high current emission with stable (durable) operation. The high current density is possible since under certain voltage drop across the dielectric layer, effective negative electron affinity is realized for the quasi-equilibrium “cold” electrons accumulated in the depletion layer in the p-region next to the dielectric layer. These electrons are generated as a result of the avalanche in the p-D-M structure or injection processes in the n+-p-D-M structure. These emitters are stable since they make use of relatively low extracting field in the vacuum region and are not affected by contamination and absorption from accelerated ions. In addition, the structures may be fabricated with current state-of-the-art technology.

Abstract: A method for electrically determining in a semiconductor wafer the location of edges of a well that underlies an insulating layer that includes forming in the wafer before forming of the well and the insulating layer a plurality of conductive stripes will that pass under the future insulating layer and extend to varying distances under the insulating layer so as to include stripes that will penetrate an edge to be located so as to form a low resistance connection thereto and stripes that will fall short of an edge to be located. From the stripes of minimum penetration that make low resistance can be determined the location of the well edges.

Abstract: A semiconductor integrated circuit device with built-in spark killer diodes suitable for output transistor protection has a problem such that a leakage current to the substrate is great and a desirable forward current cannot be obtained. In a semiconductor integrated circuit device of the present invention, P+-type first and second diffusion regions 34 and 32 are formed on the surface of a second epitaxial layer 23 in a partly overlapping manner. And, by a connection to an anode electrode 39 at a part immediately over the P+-type second diffusion region 32, a parasitic resistance R1 is made greater than a parasitic resistance R2. Thus, an operation of a parasitic transistor TR2 that causes a leakage current to a substrate 21 is suppressed, whereby leakage current can be greatly reduced.

Abstract: Method of manufacturing an edge structure for a high voltage semiconductor device, including a first step of forming a first semiconductor layer of a first conductivity type, a second step of forming a first mask over the top surface of the first semiconductor layer, a third step of removing portions of the first mask in order to form at least one opening in it, a fourth step of introducing dopant of a second conductivity type in the first semiconductor layer through the at least one opening, a fifth step of completely removing the first mask and of forming a second semiconductor layer of the first conductivity type over the first semiconductor layer, a sixth step of diffusing the dopant implanted in the first semiconductor layer in order to form a doped region of the second conductivity type in the first and second semiconductor layers.

Abstract: The invention provides a semiconductor device having a pn diode that includes a p-type SiGe layer and a n-type Si layer junctioned to the p-type SiGe layer. A built-in potential of the pn diode can be reduced, and thus obtaining a diode characteristics with lower impedance compared to the conventional scheme. Further, by forming a bridge-rectifier circuit with the pn diode or the like, alternating-current voltages can efficiently be converted into direct-current voltages. Accordingly, the invention provides a semiconductor device and method of manufacturing the same that can flow a larger electrical current in the forward direction of a diode by improving the voltage-current characteristics of the diode.

Abstract: The invention relates to a thermoelectric element comprising at least one n-type layer (1) and at least one p-type layer (2) of one or more doped semiconductors, whereby the n-type layer(s) (2) are arranged to form at least one pn-type junction (3). At least one n-type layer (1) and at least one p-type (2) are contacted in an electrically selective manner, and a temperature gradient (T1, T2) is applied or tapped parallel (x-direction) to the boundary layer (3) between at the least one n-type layer (1) and p-type layer (2). At least one pn-type junction is formed essentially along the entire, preferably longest, extension of the n-type layer(s) (1) and the p-type layer(s) (2) and, thus, essentially along the entire boundary layer (3) thereof.

Abstract: A two-terminal power diode has improved reverse bias breakdown voltage and on resistance includes a semiconductor body having two opposing surfaces and a superjunction structure therebetween, the superjunction structure including a plurality of alternating P and N doped regions aligned generally perpendicular to the two surfaces. The P and N doped regions can be parallel stripes or a mesh with each region being surrounded by doped material of opposite conductivity type. A diode junction associated with one surface can be an anode region with a gate controlled channel region connecting the anode region to the superjunction structure. Alternatively, the diode junction can comprise a metal forming a Schottky junction with the one surface. The superjunction structure is within the cathode and spaced from the anode. The spacing can be varied during device fabrication.

Abstract: A semiconductor system (200), particularly a diode, having a p-n junction is proposed, that is formed as a chip having an edge area, which includes a first layer (2) of a first conductivity type and a second layer (1, 3) of a second conductivity type; the second layer (1, 3) including at least two sublayers (1, 3); both sublayers (1, 3) forming a p-n junction with the first layer (2); the p-n junction of the first layer (2) with the first sublayer (3) being provided exclusively in the interior of the chip, and the p-n junction between the first layer (2) and the second sublayer (1) being provided in the edge area of the chip; for each cross-section of the chip area parallel to the chip plane, the first sublayer (3) corresponding only to a part of such a cross-section.

Abstract: The lateral pnp transistor encompasses a p-type semiconductor substrate, an n-type first buried region disposed on the semiconductor substrate, an n-type uniform base region disposed on the first buried region, an n-type first plug region disposed in the uniform base region, a p-type first emitter region and a first collector region disposed in and at the top surface of the uniform base region, a graded base region disposed in the uniform base region and a first base contact region disposed in the first plug region. The graded base region encloses the bottom and the side of the first main electrode region. The doping profile in the graded base region intervening between the first emitter region and the first collector region is such that the impurity concentration is gradually decreases towards the second main electrode region from the first main electrode region.

Abstract: Formed on an insulator (9) are an N− type semiconductor layer (10) having a partial isolator formed on its surface and a P− type semiconductor layer (20) having a partial isolator formed on its surface. Source/drain (11, 12) being P+ type semiconductor layers are provided on the semiconductor layer (10) to form a PMOS transistor (1). Source/drain (21, 22) being N+ type semiconductor layers are provided on the semiconductor layer (20) to form an NMOS transistor (2). A pn junction (J5) formed by the semiconductor layers (10, 20) is provided in a CMOS transistor (100) made up of the transistors (1, 2). The pn junction (J5) is positioned separately from the partial isolators (41, 42), where the crystal defect is thus very small. Therefore, the leakage current is very low at the pn junction (J5).

Abstract: A method for electrically determining in a semiconductor wafer the location of edges of a well that underlies an insulating layer that includes forming in the wafer before forming of the well and the insulating layer a plurality of conductive stripes will that pass under the future insulating layer and extend to varying distances under the insulating layer so as to include stripes that will penetrate an edge to be located so as to form a low resistance connection thereto and stripes that will fall short of an edge to be located. From the stripes of minimum penetration that make low resistance can be determined the location of the well edges.

Abstract: A low resistance gate stack for an integrated circuit transistor is provided including a metal layer having a first width and a metal nitride over surfaces of the metal layer being less than about 20 Å. The gate stack further includes a doped polysilicon layer underlying the metal layer, the doped polysilicon layer having a second width. In the illustrated embodiment, the metal layer comprises tungsten. In an atmosphere including an oxidant during a source/drain reoxidation process, the gate stack includes at least one surface simultaneously exposed to the oxidant and a passivating species which is adsorbed on the surface of the metal layer. The passivating species inhibits diffusion of the oxidant into the gate stack.

Abstract: A bi-directional transient voltage suppression device is provided. The device comprises: (a) a lower semiconductor layer of p-type conductivity; (b) an upper semiconductor layer of p-type conductivity; (c) a middle semiconductor layer of n-type conductivity adjacent to and disposed between the lower and upper layers such that lower and upper p-n junctions are formed; (d) a mesa trench extending through the upper layer, through the middle layer and through at least a portion of the lower layer, such that the mesa trench defines an active area for the device; and (e) an oxide layer covering at least portions of the walls of the mesa trench that correspond to the upper and lower junctions, such that the distance between the upper and lower junctions is increased at the walls. The integral of the net middle layer doping concentration of this device, when taken over the distance between the junctions, is such that breakdown, when it occurs, is punch through breakdown, rather than avalanche breakdown.

Abstract: In the semiconductor integrated circuit device, a first P+ type buried layer formed as an anode region and an N+ type diffused region formed in a cathode region are spaced from each other in the direction of the depth. This makes it possible to provide a semiconductor integrated circuit device in which a large depletion layer forming region can be provided in an N type region at a PN junction formed by first and second epitaxial layers and when a reverse bias voltage is applied to a diode element and in which a withstand voltage can be maintained by a depletion layer thus formed to prevent breakdown of elements in the device attributable to a breakdown current.

Abstract: A semiconductor device includes a diffusion area formed in a semiconductor layer of a first conductive type. The diffusion area comprises first and second impurity diffusion areas of the first and second conductive types, respectively. The diffusion area has a first and second areas which are defined by an impurity concentration of the first and second impurity diffusion areas. A junction between the first and second area is formed in a portion in which the first and second impurity diffusion areas overlap each other. A period of the impurity concentration, in a planar direction of the semiconductor layer, of the first or second area is smaller than the maximum width, in the planar direction of the semiconductor layer, of the first and second impurity diffusion areas constituting the first or second area.

Abstract: An electronic driver circuitry for an RF switch diode used in Acoustic Ink Jet Printing (AIP) systems is disclosed The electronic driver circuitry consists of a PMOS transistor and a poly resistor used to control the on/off states of the RF switch diode wherein the drive current for the RF switch diode is the same as the current in the PMOS transistor. To compensate for undesirable variations in the RF switch diode, the driver circuitry is designed such that the current in the PMOS transistor is adjusted in an opposite direction to cancel the unwanted variations.

Abstract: An electronic driver circuitry for an RF switch diode D1 used in Acoustic Ink Jet Printing (AIP) systems that compensates and cancels out undesired variations and non-idealities is disclosed. The electronic driver circuitry consists of a second RF switch diode D2 used as a compensation diode that is placed in close physical proximity to the RF switch diode D1 used for RF switching. To compensate for undesirable variations in the RF switch diode D1, the driver circuitry is designed such that the current in the RF switch diode D2 is adjusted in an opposite direction to cancel the unwanted variations of the RF switch diode D1.

Abstract: Semiconductor diodes are diode connected vertical cylindrical field effect devices having one diode terminal as the common connection between a gate and a source/drain of the vertical cylindrical field effect devices. Methods of forming the diode connected vertical cylindrical field effect devices are disclosed.

Abstract: Disclosed is an organic thin film device in which as a junction interface shape between an organic thin film and an adjacent layer, a sectional contour shape of a device interface having a Hausdorff dimension, as one fractal dimension, falling within the range 1.5≦D≦2.0 is formed by defining the Hausdorff dimension and its scale length.

Abstract: A semiconductor device such as an IGBT, for realizing measurement precision for forward voltage effect characteristics using a relatively small current. It includes a second conductivity type of first anode region formed to partially constitute the upper surface of a first conductivity type of semiconductor substrate and having an anode electrode formed on its upper surface, a second anode region formed within said first anode region, and an anode electrode formed on said second anode region. The second anode region is electrically isolated from the first anode region, and the anode electrode formed on the upper surface of the second anode region is independent of the anode electrode formed on the upper surface of the first anode region. In such semiconductor device having said second anode region, even though a small force current, measurement can be performed at a current density which is equal to or close to a rated current.

Abstract: A rectifier structure that exhibits a low turn-on voltage and allows rapid switching without ringing is provided. The structure utilizes a thin epitaxial layer interposed between the two layers comprising the rectifier junction. Preferably the epitaxial layer is of the same conductivity as the underlying layer while being comprised of the same material as the outermost layer.

Abstract: A capacitor structure is formed on a substrate member having one or more via holes therein. Metallization portions within the via holes of the substrate member form part of the plates of the capacitor.

Abstract: A diode for improved electrostatic discharge (ESD) protection against current failure includes a plurality of elongate anode and cathode conductor stripes each having first and second end portions of different widths to reduce current densities at feeder bus tie points, thereby reducing the possibility of current failure.

Abstract: The present invention provides a photovoltaic device being capable of generating a large amount of current even with thin joined semiconductor layers, has a high photoelectric conversion efficiency and can be manufactured inexpensively at a low temperature together with a manufacturing method of the same, a photovoltaic device integrated with a building material and a power-generating apparatus. The photovoltaic device is formed by depositing joined semiconductor layers on a substrate, wherein a ratio of projected areas of regions on a surface of the joined semiconductor layers that have heights not smaller than a center value of concavities and convexities to a projected area of the entire surface of the joined semiconductor layers is higher than a ratio of projected areas of regions on the surface of the substrate that have heights not smaller than a center value of concavities and convexities on a surface of the substrate to a projected area of the entire surface of the substrate.

Abstract: An insulator film provided on a region for arranging a Zener diode has a plurality of groove portions successively arranged in a direction D1 of extension of each semiconductor region forming the diode. Each groove potion extends in a width direction D2 of each semiconductor region, and has a depth T3. Each semiconductor region is arranged on the upper surface of the insulator film. Therefore, it follows that each semiconductor region has a plurality of irregular shapes arranged in the direction D1 of extension and the Zener diode has a peripheral length not only in the transverse direction D1 but also in a vertical direction D3, so that a p-n junction area in the Zener diode is increased. Thus, parasitic resistance of an input protection Zener diode is reduced for improving a gate insulator film protective function of the diode.

Abstract: A semiconductor device (102) comprises an N type semiconductor substrate (1). A P layer (22) is formed in a first surface (S1) of the semiconductor substrate (1), and a P layer (23) is formed in the semiconductor substrate (1) and in contact with the first surface (S1) and a second surface (S2) of the semiconductor substrate (1) corresponding to a beveled surface. The P layer (23) surrounds the P layer (22) in non-contacting relationship with the P layer (22). A separation distance (D) between the P layers (22, 23) is set at not greater than 50 &mgr;m. A distance (D23) between a third surface (S3) of the semiconductor substrate (1) and a portion of the P layer (23) which is closer to the third surface (S3) is less than a distance (D22) between the third surface (S3) and a portion of the P layer (22) which is closer to the third surface (S3).

Abstract: An electrical device such as a diode usable in high voltage applications wherein the electrical device is fabricated from a method which yields a plurality of high voltage electrical devices, the present method including providing a substrate of a semiconductor material having a predetermined substrate conductive type, the substrate being typically formed from a monocrystalline growth method, forming a second epitaxial layer contiguous with the upper surface of the substrate, the epitaxial layer having a predetermined second layer conductive type, and thereafter forming a top layer of dopant, material in a predetermined pattern upon the upper surface of the second epitaxial layer. This predetermined pattern of dopant material typically takes the form of an array of patches which can be achieved through either a masking and etching process, or through a screen printing process.

Abstract: A semiconductor device has improved reverse recovery characteristics and has greatly reduced the leakage current caused during application of a reverse bias voltage. The semiconductor device according to the invention includes a semiconductor chip having a first major surface and a second major surface facing opposite to the first major surface; an anode electrode on the first major surface; and a cathode electrode on the second major surface. The semiconductor chip includes a first laminate structure, a second laminate structure and a third laminate structure arranged in parallel to each other, the second laminate structure being interposed between the first laminate structure and the third laminate structure.

Abstract: The invention relates to a power diode structure having improved dynamic characteristics which comprises a semiconductor body of a first conduction type. A semiconductor zone of the other conduction type which is contrary to the first conduction type is embedded in the one surface of said semiconductor body. The power diode also comprises an anode which contacts the semiconductor zone, and has a cathode which contacts the semiconductor body. At least one floating region of the second conduction type is provided in the semiconductor body.

Abstract: A semiconductor device is provided which relieves the concentration of electric fields generated at a corner part and the like even, if the integration degree of the device is improved, and thus easily improves a current driving performance by improving the integration degree. In the semiconductor device, an N well is formed on a p type substrate, and a drain is formed inside the N well. A P base is formed outside the N well, and the P base and the drain have straight portions with a uniform interval. A corner part is formed at an end portion of the straight portions. At the corner part of the drain, the interval between the P base and the drain is larger than the interval between the straight portions, and the conductivity characteristics in the larger interval region are different from those of the N well along a predetermined width WI in order to relieve the concentration of electric fields at the corner part.

Abstract: An organic thin film device in which, as a junction interface shape between an organic thin film and an adjacent layer, a sectional contour shape of a device interface having a Hausdorff dimension, as one fractal dimension, falling within the range 1.5≦D≦2.0 is formed by defining the Hausdorff dimension and its scale length.

Abstract: A sense amplifier for use with a dynamic random access memory is formed in a silicon integrated circuit. The pitch of an array of such sense amplifiers is equal to the pitch of pairs of bit lines of a memory array. Each array of sense amplifiers is formed from four rows of transistors of a given n or p-channel type Metal Oxide Semiconductor (MOS) transistor having a U-shaped gate electrode. The gate electrode of the transistors in each row of transistors of the sense amplifier is offset from those in a previous row by a preselected amount. The bit lines passing through the sense amplifier are straight, with no offsets to affect photolithographic performance, and no protuberances to increase the capacitance of the bit lines. Such an array of sense amplifiers has a size equivalent to the minimum size of the pairs of bit lines, and thus does not cause any increase in the width of the array of memory cells.

Abstract: In a field-effect semiconductor device, for example a power MOSFET, a body portion separates a channel-accommodating region from a drain region at a surface of a semiconductor body. This body portion includes a drift region which serves for current flow of charge carriers of a first conductivity type from the conduction channel to the drain region, in a conducting mode of the device. Instead of being a single region, the body portion also includes field-relief regions of the second conductivity type, which are depleted together with the drift region in a voltage blocking mode of the device to provide a voltage-carrying space-charge region. The drain region extends at least partially around the body portion at the surface, and the relief regions are located radially in this body portion.

Abstract: The invention relates to a semiconductor device with a diode. The semiconductor body (10) comprises a stack of a first semiconductor region provided with a first connection conductor (5) and a second semiconductor region (2) connected to a second connection conductor (6), wherein a rectifying junction is present between the two semiconductor regions (1, 2) having opposite conductivity types. Such a device is—after a rotation through 90 degrees—suitable for surface mounting. However, in particular at high voltage and/or high power levels, the diode may suffer from breakdown or a high leakage current.