Abstract: An electronic package structure, an electronic substrate, and a method of manufacturing an electronic package structure are provided. The electronic package structure includes a substrate. The substrate includes a bonding region and an alignment structure. The bonding region is located at a side of the substrate and configured to bond with an electronic component. The alignment structure is located at the side of the substrate and out of the bonding region and configured to providing a fiducial mark for position-aligning, wherein the alignment structure comprises a first region and a second region visually distinct from the first region.

Abstract: An electronic package is formed by disposing an electronic element and a lead frame having a plurality of conductive posts on a carrier structure having an antenna function, and encapsulating the electronic element and the lead frame with an encapsulant. The encapsulant is defined with a first encapsulating portion and a second encapsulating portion lower than the first encapsulating portion. The electronic element is positioned in the first encapsulating portion, and the plurality of conductive posts are positioned in the second encapsulating portion. End surfaces of the plurality of conductive posts are exposed from a surface of the second encapsulating portion so as to be electrically connected to a connector.

Abstract: An electronic package is provided, which stacks an electronic structure as an integrated voltage regulator on an electronic component to facilitate close-range cooperation with the electronic component for electrical transmission.

Abstract: Provided are a power module and a heat sink system. The power module includes a first circuit board, a second circuit board, at least one discrete component and an encapsulation body. One discrete component includes a lead frame and at least one chip, the lead frame is disposed between the first circuit board and the second circuit board, the lead frame includes two end faces and multiple mounting lateral surfaces connected in sequence, an angle is formed between one end face and one mounting lateral surface, one of the two end faces is electrically connected to the first circuit board and the other of the two end faces is electrically connected to the second circuit board, and the chip is disposed on each of the multiple mounting lateral surfaces. The encapsulation body is configured to pot a space between the first circuit board and the second circuit board.

Abstract: A three-dimensional semiconductor memory device includes: a peripheral circuit structure; and a cell array structure on the peripheral circuit structure. The peripheral circuit structure includes a lower wiring on a substrate, a stopping insulating layer on the lower wiring, a contact via on the lower wiring, a floating via on the stopping insulating layer, and an upper wiring on the contact via. The floating via does not contact the lower wiring. The contact via contacts the lower wiring through a via hole in the stopping insulating layer. The upper wiring contacts the contact via.

Abstract: In one example, a semiconductor structure or device comprises a substrate comprising a conductive structure having a top side and a first shielding terminal on the top side of the conductive structure, an electronic component on the top side of the conductive structure, a package body on the top side of the conductive structure and contacting a side of the electronic component, a shield on a top side of the package body and a lateral side of the package body, and a shield interconnect coupling the shield to the first shielding terminal of the conductive structure. Other examples and related methods are also disclosed herein.

Abstract: A module comprises: a wiring board; a first component, a second component and a third component mounted on a first main surface; a shield structure mounted on the first main surface; a first sealing resin that seals the first component and the like; and a shield film that covers an upper surface of the first sealing resin and the like, the shield structure including a top side portion and at least one sidewall portion bent from the top side portion and thus extending therefrom, the top side portion including the top side portion's conductive layer and a magnetic layer therein, the sidewall portion including the sidewall portion's conductive layer therein, the top side portion's conductive layer and the sidewall portion's conductive layer being electrically connected to a ground conductor, the magnetic layer in the top side portion being located over the first component.

Abstract: In a coil component, a shield layer is provided after the unevenness of the surface of an element body is smoothened by the surface being covered with an insulating layer. A Cu layer of the shield layer is provided on a smooth surface, and thus a thickness variation can be suppressed and the Cu layer can be formed with a substantially uniform thickness. In the coil component, a point where the shield layer is thin or a point lacking the shield layer is unlikely to be generated and a functional degradation of the shield layer is effectively suppressed.

Abstract: A semiconductor package includes a semiconductor die, a redistribution structure and connective terminals. The redistribution structure is disposed on the semiconductor die and includes a first metallization tier disposed in between a pair of dielectric layers. The first metallization tier includes routing conductive traces electrically connected to the semiconductor die and a shielding plate electrically insulated from the semiconductor die. The connective terminals include dummy connective terminals and active connective terminals. The dummy connective terminals are disposed on the redistribution structure and are electrically connected to the shielding plate. The active connective terminals are disposed on the redistribution structure and are electrically connected to the routing conductive traces. Vertical projections of the dummy connective terminals fall on the shielding plate.

Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The method includes forming a semiconductor chip, forming an electromagnetic shield that covers the semiconductor chip, and forming a molding that covers the electromagnetic shield. The electromagnetic shield is electrically connected to a conductor on a side of the semiconductor chip.

Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into a first side of a wafer, the first side of the wafer including a plurality of electrical contacts. The method may also include coating the first side of the wafer and an interior of the plurality of notches with a molding compound, grinding a second side of the wafer to thin the wafer to a desired thickness, forming a back metal on a second side of the wafer, exposing the plurality of electrical contacts through grinding a first side of the molding compound, and singulating the wafer at the plurality of notches to form a plurality of semiconductor packages.

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a frame, a redistribution layer, and a first semiconductor die. The substrate has a wiring structure and is surrounded by a molding material. The frame is disposed in the molding material and surrounds the substrate. The redistribution layer is disposed over the substrate and electrically coupled to the wiring structure. The first semiconductor die is disposed over the redistribution layer.

Abstract: A semiconductor package includes a front redistribution structure having a first surface and a second surface, opposite to the first surface, a dielectric layer, an antenna substrate including a plurality of antenna members in the dielectric layer, a semiconductor chip having a connection pad connected to the plurality of antenna members, a conductive core structure having a first through-hole accommodating the antenna substrate and a second through-hole accommodating the semiconductor chip, and a rear redistribution structure including a conductive cover layer exposing an upper portion of the antenna substrate and covering an upper portion of the semiconductor chip, and a conductive via connecting the conductive cover layer to the conductive core structure.

Abstract: A package structure includes a first and a second conductive feature structures, a die, an insulator, an encapsulant, an adhesive layer, and a first through via. The die is located between the first conductive feature structure and the second conductive feature structure. The die is electrically connected to the second conductive feature structure. The insulator is disposed between the die and the first conductive feature structure. The insulator has a bottom surface in physical contact with a polymer layer of the first conductive feature structure. The encapsulant is located between the first conductive feature structure and the second conductive feature structure. The encapsulant is disposed on the insulator and laterally encapsulates the die and the insulator. The adhesive layer is disposed between the die and the insulator. The first through via extends through the encapsulant to connect to the first conductive feature structure and the second conductive feature structure.

Abstract: An electronic device includes a flexible substrate and a driving component. In the flexible substrate, a first side region, a second side region and a first cutting structure are disposed in a peripheral region, wherein a display region and the first side region are separated by a first edge of the display region, the display region and the second side region are separated by a second edge of the display region, the first edge and the second edge are respectively parallel to a first direction and a second direction perpendicular to the first direction, the first cutting structure has a first endpoint and two edges separated by the first endpoint and respectively belonging to the first side region and the second side region. The driving component overlaps the flexible substrate in a top view direction perpendicular to the first direction and the second direction.

Abstract: An electronic system in package, including at least: a support; one or more chips mechanically and electrically coupled to a front face of the support; an encapsulation material covering the front face of the support and encapsulating the chip(s); several side protection elements, comprising an opaque material and laterally surrounding the chip(s) and configured to form a barrier at least against laser attacks made through side faces of the electronic system in package that are substantially perpendicular to the front face of the support; and wherein the side protection elements are disposed in the encapsulation material or in one or more first blocks of material distinct from the support and disposed in the encapsulation material.

Abstract: A semiconductor device has a first substrate and a first electrical component disposed over the first substrate. A first support frame is disposed over the first substrate. The first support frame has a horizontal support channel extending across the first substrate and a vertical support brace extending from the horizontal support channel to the first substrate. The first support frame can have a vertical shielding partition extending from the horizontal support channel to the first substrate. An encapsulant is deposited over the first electrical component and first substrate and around the first support frame. A second electrical component is disposed over the first electrical component. A second substrate is disposed over the first support frame. A second electrical component is disposed over the second substrate. A third substrate is disposed over the second substrate. A second support frame is disposed over the second substrate.

Abstract: There is provided a radio-frequency module and a communication device with which miniaturization can be achieved and quality deterioration can be suppressed. A radio-frequency module includes a mount board on which a ground terminal is disposed, a first chip, a second chip, and a cover (a shield cover). The first chip is disposed on the mount board. The second chip is disposed on the first chip. The cover covers at least a part of the first chip and at least a part of the second chip. The second chip has a first connection terminal (a ground terminal) on an opposite side from the first chip in a thickness direction of the mount board. The cover includes a shield layer connected to the ground terminal disposed on the mount board. The first connection terminal is connected to the shield layer.

Abstract: A semiconductor device has a first package layer. A first shielding layer is formed over the first package layer. The first shielding layer is patterned to form a redistribution layer. An electrical component is disposed over the redistribution layer. An encapsulant is deposited over the electrical component. A second shielding layer is formed over the encapsulant. The second shielding layer is patterned. The patterning of the first shielding layer and second shielding layer can be done with a laser. The second shielding layer can be patterned to form an antenna.

Abstract: An electronic package structure and a method of manufacturing an electronic package structure are provided. The electronic package structure includes a substrate, a conductive element, and a support structure. The substrate has a bottom surface and a lateral surface angled with the bottom surface. The conductive element is on the lateral surface of the substrate. The support structure is on the bottom surface of the substrate and configured to space the bottom surface from an external carrier. A lateral surface of the support structure is spaced apart from the lateral surface of the substrate by a first distance.

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a semiconductor die disposed over the substrate, and a frame disposed over the substrate. The frame is adjacent to the semiconductor die, and an upper surface of the frame is lower than the upper surface of the semiconductor die. IN addition, a passive component is disposed on the substrate and located between the frame and the semiconductor die.

Abstract: A method of fabricating a semiconductor package includes providing a substrate having at least one contact and forming a redistribution layer on the substrate. The formation of the redistribution layer includes forming a dielectric material layer over the substrate and performing a double exposure process to the dielectric material layer. A development process is then performed and a dual damascene opening is formed in the dielectric material layer. A seed metallic layer is formed over the dual damascene opening and over the dielectric material layer. A metal layer is formed over the seed metallic layer. A redistribution pattern is formed in the first dual damascene opening and is electrically connected with the at least one contact.

Abstract: A semiconductor package includes a package substrate having a first insulating layer, a wiring layer disposed on the first insulating layer, and a second insulating layer disposed on the first insulating layer and covering at least a portion of the wiring layer, a pair of support members disposed to face each other on the second insulating layer of the package substrate, and a pair of semiconductor chips disposed between the pair of support members and electrically connected to the wiring layer, wherein the second insulating layer has an opening surrounding at least a portion of each of the pair of semiconductor chips.

Abstract: A chip package structure is provided. The chip package structure includes a chip structure. The chip package structure includes a first ground bump below the chip structure. The chip package structure includes a conductive shielding film disposed over the chip structure and extending onto the first ground bump. The conductive shielding film has a curved bottom surface.

Abstract: A chip package structure is provided. The chip package structure includes a chip. The chip package structure includes a conductive bump over and electrically connected to the chip. The chip package structure includes a ring-like structure over and electrically insulated from the chip. The ring-like structure surrounds the conductive bump, and the ring-like structure and the conductive bump are made of a same material.

Abstract: A semiconductor device includes a base plate, a substrate, a semiconductor element, a case, and a wiring terminal. The case is disposed on the base plate so as to cover the substrate and the semiconductor element. The wiring terminal is electrically connected to the semiconductor element. The case includes a first case unit and a second case unit that is separate from the first case unit. The wiring terminal includes a first wiring unit and a second wiring unit. The first wiring unit is disposed so as to protrude from an inside to an outside of the case, and is electrically connected to the semiconductor element. The second wiring unit is bent with respect to the first wiring unit and disposed outside the case. The first case unit and the second case unit are disposed so as to sandwich the first wiring unit.

Abstract: The present disclosure relates to a semiconductor module, especially a power semiconductor module, in which the heat dissipation is improved and the power density is increased. The semiconductor module may include at least two electrically insulating substrates, each having a first main surface and a second main surface opposite to the first main surface. On the first main surface of each of the substrates, at least one semiconductor device is mounted. An external terminal is connected to the first main surface of at least one of the substrates. The substrates are arranged opposite to each other so that their first main surfaces are facing each other.

Abstract: Embodiments include systems in packages (SiPs) and a method of forming the SiPs. A SiP includes a package substrate and a first modularized sub-package over the package substrate, where the first modularized sub-package includes a plurality of electrical components, a first mold layer, and a redistribution layer. The SiP also includes a stack of dies over the package substrate, where the first modularized sub-package is disposed between the stack of dies. The SiP further includes a plurality of interconnects coupled to the stack of dies, the first modularized sub-package, and the package substrate, wherein the redistribution layer of the first modularized sub-package couples the stack of dies to the package substrate with the plurality of interconnects. The SiP may enable the redistribution layer of the first modularized sub-package to couple the electrical components to the stacked dies and the package substrate without a solder interconnect.

Abstract: A vertical memory device includes a substrate with a cell region, a through via region on opposite sides of the cell region, and a mold region surrounding the cell and through via regions, gate electrodes spaced apart from each other along a first direction vertical to an upper surface of the substrate, and extending in a second direction parallel to the upper surface of the substrate, a channel extending in the first direction on the cell region, and extending through at least a portion of the stacked gate electrodes, and a first mold including first and second layers alternately and repeatedly stacked along the first direction on the mold region, the first and second layers including different insulation materials from each other, and each of the second layers of the first mold being at the same height as and contact a corresponding one of the gate electrodes.

Abstract: Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.

Abstract: A self-destructing device includes a frangible substrate having at least one pre-weakened area. A heater is thermally coupled to the frangible substrate proximate to or at the pre-weakened area. When activated, the heater generates heat sufficient to initiate self-destruction of the frangible substrate by fractures that propagate from the pre-weakened area and cause the frangible substrate to break into many pieces.

Abstract: The present invention discloses a system for protecting a MEMS product from an ESD event, including, a control circuit; a MEMS product, electrically connected with the control circuit; an ESD protection device, electrically connected with the control circuit, and electrically connected with the MEMS product in parallel; wherein, the ESD protection device comprises: a top electrode assembly electrically connected with the control circuit; a flexible beam comprising a first electrode layer electrically connected with the control circuit, a second electrode layer electrically connected with the MEMS product, and a moving metal contact electrically connected with the second electrode layer; a bottom electrode assembly having a bottom electrode layer electrically connected with the MEMS product and a fixed metal contact electrically connected with the bottom electrode layer and facing the moving metal contact.

Abstract: A module is provided with a substrate including a principal surface, a plurality of electronic components arranged on the principal surface, a sealing resin covering the principal surface and the plurality of electronic components and including a trench between any of the plurality of electronic components, a ground electrode arranged on the principal surface, a conductive layer covering the sealing resin, and a magnetic member. The conductive layer is electrically connected to the ground electrode by a connecting conductor arranged so as to penetrate the sealing resin. The magnetic member includes a magnetic plate member arranged so as to cover the sealing resin and a magnetic wall member arranged in a wall shape in the trench. The connecting conductor and the magnetic wall member both fill the trench in a state of being formed in the trench.

Abstract: A quantum device (100) includes an interposer (112), a quantum chip (111) mounted on the interposer (112), and a shield part (150) provided so as to surround a quantum circuit region of the interposer (112) and the quantum chip (111). Accordingly, the quantum device (100) is able to prevent interference in the quantum circuit region due to exogenous noise.

Abstract: A multichip module with a vertical stack of a logic chip, a translator chip, and at least one memory chip. The multichip module includes a logic chip, a translator chip over and vertically connecting to the logic chip, and at least one memory chip above and vertically connecting to the translator chip where the translator chip is one of a chip with active devices or a passive chip.

Abstract: A radio frequency (RF) system including first and second planar RF devices coupled by non-galvanic interconnect. According to various embodiments, a first RF device and a second RF device are separated by a dielectric layer, each of the first and second RF devices including a plurality of pads disposed on surface and surrounded by a common electrode, the common electrode configured as a grounded metal shield, wherein pads of the first RF device and pads of the second RF device face each other to provide capacitive coupling between the pads. The disclosure may reduce complexity and size of the system, and offer more reliable and easily producible interconnection between elements of the RF system.

Abstract: Semiconductor device assemblies with improved ground connections, and associated systems and methods are disclosed. In one embodiment, a semiconductor device assembly may include one or more semiconductor dies mounted on an upper surface of a package substrate. Further, the package substrate includes a bond pad disposed on the upper surface, which may be designated as a ground node for the semiconductor device assembly. The bond pad may be electrically connected to an electromagnetic interference (EMI) shield of the semiconductor device assembly through a conductive component attached to the bond pad and configured to be in contact with the EMI shield at a sidewall surface or a top surface of the semiconductor device assembly, thereby forming the ground connection. Such ground connection may reduce a processing time to form the EMI shield while improving yield and reliability performance of the semiconductor device assemblies.

Abstract: An electronic package and a manufacturing method thereof are provided, where a plurality of shielding wires are arranged on a carrier and spanning across an electronic component to cover the electronic component, so that the shielding wires serve as a shielding structure to protect the electronic component from the interference of external electromagnetic waves.

Abstract: A microelectromechanical system (MEMS) sensor package includes a laminate that provides physical support and electrical connection to a MEMS sensor. A resin layer is embedded within an opening of the laminate and a MEMS support layer is embedded within the opening by the resin layer. A MEMS structure of the MEMS sensor is located on the upper surface of the MEMS support layer.

Abstract: A semiconductor device package includes a substrate, a reflector, a radiator and a first director. The reflector is disposed on a surface of the substrate. The radiator is disposed over the reflector. The first director is disposed over the radiator. The reflector, the radiator and the first director have different elevations with respect to the surface of the substrate. The radiator and the first director define an antenna.

Abstract: A power module is disclosed. A power module according to an embodiment of the present disclosure may include a first substrate and a second substrate spaced apart from each other, an electronic device unit provided on at least either one of the first and second substrates, and a lead frame unit provided between the first and second substrates. One side of the lead frame unit may be connected to an external circuit, and the other side thereof may be configured to electrically connect the first and second substrates. Accordingly, the lead frame unit may perform a function of electrically connecting the first and second substrates instead of a via spacer in the related art.

Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes an electronic component, a conductive contact, and a first shielding layer. The electronic component has a first surface, a lateral surface angled with the first surface, and a second surface opposite to the first surface. The conductive contact is connected to the first surface of the electronic component. The first shielding layer is disposed on the lateral surface of the electronic component and a portion of the first surface of the electronic component. The first shielding layer contacts the conductive contact.

Abstract: Several aspects of the present technology are directed toward fan-out packaged semiconductor devices having an integrated shield. The shield can include a conductive wall and a conductive cap over a redistribution structure. The shield can surround or at least partially enclose circuits placed or formed on the redistribution structure. The circuits and/or the conductive cap can be covered by an encapsulant, and the conductive cap can be on an upper surface of an encapsulant.

Abstract: A multilayer electronic component includes a body including a dielectric layer and an internal electrode; and an external electrode including an electrode layer disposed on the body and connected to the internal electrode and a conductive resin layer disposed on the electrode layer, and the conductive resin layer includes a metal wire, a conductive metal, and a base resin.

Abstract: A method of making a semiconductor device may include providing a large semiconductor die comprising conductive interconnects with a first encapsulant disposed over four side surfaces of the large semiconductor die, over the active surface of the large semiconductor die, and around the conductive interconnects. A first build-up interconnect structure may be formed over the large semiconductor die and over the first encapsulant. Vertical conductive interconnects may be formed over the first build-up interconnect structure and around an embedded device mount site. An embedded device comprising through silicon vias (TSVs) may be disposed over the embedded device mount site. A second encapsulant may be disposed over the build-up structure, and around at least five sides of the embedded device. A second build-up structure may be formed disposed over the planar surface and configured to be electrically coupled to the TSVs of the embedded device and the vertical conductive interconnects.

Abstract: A semiconductor device package includes a substrate, a first solder paste, an electrical contact and a first encapsulant. The substrate includes a conductive pad. The first solder paste is disposed on the pad. The electrical contact is disposed on the first solder paste. The first encapsulant encapsulates a portion of the electrical contact and exposes the surface of the electrical contact. The electrical contact has a surface facing away from the substrate. A melting point of the electrical contact is greater than that of the first solder paste. The first encapsulant includes a first surface facing toward the substrate and a second surface opposite to the first surface. The second surface of the first encapsulant is exposed to air.

Abstract: A semiconductor module includes a main board and external terminals. A package substrate includes a core insulation layer, a conductive pattern disposed in the core insulation layer and electrically connected with the external terminals, an upper insulation pattern and a lower insulation pattern. At least one semiconductor chip is disposed on an upper surface of the package substrate and is electrically connected with the conductive pattern. A shielding plate is disposed on a molding member and lateral side surfaces of the package substrate and shields electromagnetic interference (EMI) emitted from the semiconductor chip. A shielding fence extends from an edge portion of a lower surface of the lower insulation pattern and directly contacts the upper surface of the main board. The shielding fence surrounds the external terminals and shields EMI emitted from the external terminals. A reinforcing member increases a strength of the shielding fence.

Abstract: A semiconductor package including a first lower stack on a substrate and including first lower semiconductor chips, a redistribution substrate on the first lower stack, a redistribution connector electrically connecting the substrate to the redistribution substrate, a first upper stack on the redistribution substrate and including first upper semiconductor chips, a first upper connector electrically connecting the redistribution substrate to the first upper stack, a second upper stack horizontally spaced apart from the first upper stack and including second upper semiconductor chips, and a second upper connector electrically connecting the redistribution substrate to the second upper stack may be provided. The redistribution connector may be on one side of the redistribution substrate. The first upper connector may be on one side of the first upper stack. The second upper connector may be on one side of the second upper stack.

Abstract: Encapsulated PCB assembly (1) for electrical connection to a high- or medium-voltage power conductor in a power distribution network of a national grid, comprising a) a PCB (10), delimited by a peripheral edge (20) and comprising a high-tension pad (60, 62) on a voltage of at least one kilovolt, b) an electrically insulating encapsulation body (70) in surface contact with, and enveloping, the high-tension pad and at least a portion of the PCB edge adjacent to the high-tension pad, c) a shielding layer (80) on an external surface (90) of the encapsulation body and for being held on electrical ground or on a low voltage to shield at least a low-voltage portion of the PCB. The high-tension pad extends to the peripheral edge of the PCB.

Abstract: A semiconductor package has a substrate, a first component disposed over the substrate, an encapsulant deposited over the first component, and a second component disposed over the substrate outside the encapsulant. A metal mask is disposed over the second component. A shielding layer is formed over the semiconductor package. The metal mask after forming the shielding layer. The shielding layer is optionally formed on a contact pad of the substrate while a conic area above the contact pad that extends 40 degrees from vertical remains free of the encapsulant and metal mask while forming the shielding layer. Surfaces of the metal mask and encapsulant oriented toward the contact pad can be sloped. The metal mask can be disposed and removed using a pick-and-place machine.