With Means For Controlling Lead Tension Patents (Class 257/674)
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Patent number: 11776929Abstract: A semiconductor device includes: an inner substrate on which a semiconductor chip is mounted, and has a surface on which terminals including electric path terminals are formed; a lead frame which has a chip connecting electrode portion which is electrically connected to a surface of the semiconductor chip via a conductive bonding member, substrate connecting electrode portions which are electrically connected to the electric path terminals of the inner substrate, and horizontal surface support portions which bulge to the outside from the chip connecting electrode portion or the substrate connecting electrode portions; and pin terminals which are mounted upright over the inner substrate in a direction perpendicular to flat surfaces of the substrate connecting electrode portions of the lead frame, wherein the horizontal surface support portions bulge to the outside of the inner substrate.Type: GrantFiled: December 4, 2020Date of Patent: October 3, 2023Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventors: Soichiro Umeda, Atsushi Kyutoku
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Patent number: 10910233Abstract: A semiconductor device package includes a substrate and a monolithic encapsulant. The substrate has a first surface, a second surface opposite to the first surface and a plurality of lateral surfaces extending between the first surface and the second surface. The substrate defines a first opening and a second opening that extend between the first surface and the second surface and respectively expose the plurality of lateral surfaces. The monolithic encapsulant includes a first portion disposed on the first surface of the substrate, a second portion disposed on the second surface of the substrate and a third portion disposed within the first opening and the second opening.Type: GrantFiled: April 11, 2018Date of Patent: February 2, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventor: Chanyuan Liu
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Patent number: 10868364Abstract: Solution is preparing a substrate; covering an electronic component mounting region and an antenna mounting region of the substrate with a resin material having viscosity or fluidity; curing the resin material to form a resin layer, and thereafter performing grinding or polishing so as to substantially flatten a surface of the resin layer on the electronic component mounting region and the antenna mounting region; and covering the flattened resin layer with a shielding material having viscosity or fluidity.Type: GrantFiled: November 30, 2017Date of Patent: December 15, 2020Assignee: TAIYO YUDEN CO., LTD.Inventors: Takehiko Kai, Masaya Shimamura, Mikio Aoki, Jin Mikata, Taiji Ito
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Patent number: 10535933Abstract: A connection element for an electronic component assembly includes a support, a first contact pad, and a second contact pad. The first contact pad and the second contact pad are electrically connected. A first contact conductor has a first conductor surface electrically connected to the first contact pad at a first section, and is configured to form a welded connection in a second section of the first conductor surface, and/or on the second conductor surface. The invention also relates to an electronic component assembly which includes such a connection element, and which has at least one component welded to the contact conductor.Type: GrantFiled: April 7, 2017Date of Patent: January 14, 2020Assignee: BIOTRONIK SE & Co. KGInventor: Martin Henschel
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Patent number: 10199300Abstract: A lead frame includes a first outer lead portion and a second outer lead portion which is arranged to oppose to the first outer lead portion with an element-mounting region between them. An inner lead portion has first inner leads connected to the first outer leads and second inner leads connected to the second outer leads. At least either the first or second inner leads are routed in the element-mounting region. An insulation resin is filled in the gaps between the inner leads located on the element-mounting region. A semiconductor device is configured with semiconductor elements mounted on both the top and bottom surfaces of the lead frame.Type: GrantFiled: February 9, 2017Date of Patent: February 5, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventor: Yoshiaki Goto
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Patent number: 9974178Abstract: Multipolar lead parts having plural leads and a retaining member, wherein the retaining member includes a cylindrical portion so as to cover peripheries of the leads, the cylindrical portion facing in a board direction; wherein the leads each include an upper-side board coupling portion and a lower-side board coupling portion; wherein the lower-side board coupling portion comprises a forward protruding portion that the other end side of each of the leads is bent in a direction orthogonal to an arrangement face of the leads, a vertical portion extending downward from a front end, a solder coupling portion extending backward from a lower end, and a rising portion extending upward from the solder coupling portion; and wherein said rising portion is formed as to have an obtuse angle from said solder coupling portion regardless of a bending angle of said vertical portion with respect to said solder coupling portion.Type: GrantFiled: September 10, 2015Date of Patent: May 15, 2018Assignee: NSK LTD.Inventors: Masakazu Morimoto, Noboru Kaneko, Tadayoshi Osakabe
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Patent number: 9475694Abstract: Vertical mount package assemblies and methods for making the same are disclosed. A method for manufacturing a vertical mount package assembly includes providing a base substrate having electrical connections for affixing to external circuitry, and providing a package having a mounting region configured to receive a device therein. Flexible electrical leads are formed between the base substrate and the package. The flexible leads can include a plurality of aligned grooves to guide bending. After forming the flexible electrical leads, the package is rotated relative to the base substrate. The aligned grooves can constrain the relative positions of the substrates during rotation, and the beveled edges of the base substrate and package can maintain a desired angular relationship (e.g., perpendicular) between the base substrate and the package after rotation.Type: GrantFiled: January 14, 2013Date of Patent: October 25, 2016Assignee: ANALOG DEVICES GLOBALInventors: Arturo Martizon, Jr., Thomas M. Goida
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Patent number: 9245832Abstract: A semiconductor module includes: a metal block; an insulation layer for heat radiation formed by directly depositing a ceramic material on at least a first surface of the metal block; an insulation layer for a relay electrode formed by directly depositing a ceramic material on a part of a second surface 1b of the metal block; a relay electrode formed by depositing a metal material on the upper surface of the insulation layer for the relay electrode; a circuit element bonded with the second surface of the metal block by solder; and an external lead terminal, wherein a bonding wire or a lead frame from the circuit element is bonded with the relay electrode, and the relay electrode and the external lead terminal are connected.Type: GrantFiled: October 10, 2014Date of Patent: January 26, 2016Assignee: FUJI ELECTRIC CO., LTD.Inventors: Akane Hasegawa, Kenji Okamoto
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Patent number: 9012262Abstract: A method of making a tiled array of semiconductor dies includes aligning and flattening. One end of each semiconductor die has attached thereto a respective printed circuit board. The aligning aligns the semiconductor dies into the tiled array in such a way that the semiconductor dies rest on a vacuum plate and the one end of each die extends beyond an edge of the vacuum plate. The flattening flattens the semiconductor dies against the vacuum plate with a vacuum after the semiconductor dies are aligned.Type: GrantFiled: April 17, 2012Date of Patent: April 21, 2015Assignee: Teledyne Rad-icon Imaging Corp.Inventors: Farrier Michael George, Roumbanis John Bernard
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Patent number: 9006869Abstract: A light emitting device package is provided comprising a light emitting device including at least one light emitting diode and a body including a first lead frame on which the light emitting device is mounted and a second lead frame spaced apart from the first lead frame, wherein at least one of the first and second lead frames is extending to a bending region in a first direction by a predetermined length on the basis of an outer surface of the body and is bent in a second direction intersecting the first direction.Type: GrantFiled: June 30, 2011Date of Patent: April 14, 2015Assignee: LG Innotek Co., Ltd.Inventor: JaeJoon Yoon
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Patent number: 8981578Abstract: A sensor array package can include a sensor disposed on a first side of a substrate. Signal trenches can be formed along the edges of the substrate and a conductive layer can be deposited in the signal trench and can couple to sensor signal pads. Bond wires can be attached to the conductive layers and can be arranged to be below a surface plane of the sensor. The sensor array package can be embedded in a printed circuit board enabling the bond wires to terminate at other conductors within the printed circuit board.Type: GrantFiled: March 15, 2013Date of Patent: March 17, 2015Inventors: Matthew E. Last, Lili Huang, Seung Jae Hong, Ralph E. Kauffman, Tongbi Tom Jiang
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Patent number: 8975733Abstract: There is provided a technology enabling the improvement of the reliability of a semiconductor device manufactured by physically fixing separately formed chip mounting portion and lead frame. A feature of an embodiment resides in that, a second junction portion formed in a suspension lead is fitted into a first junction portion formed in a chip mounting portion, thereby to physically fix the chip mounting portion and the suspension lead. Specifically, the first junction portion is formed of a concave part disposed in the surface of the chip mounting portion. The second junction portion forms a part of the suspension lead.Type: GrantFiled: February 20, 2013Date of Patent: March 10, 2015Assignee: Renesas Electronics CorporationInventors: Yukihiro Sato, Nobuya Koike
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Patent number: 8927342Abstract: The present invention specifies a leadframe for electronic components and a corresponding manufacturing process, in which the bonding islands are formed by welding individual, prefabricated segments of a bonding-capable material onto a stamped leadframe.Type: GrantFiled: October 12, 2009Date of Patent: January 6, 2015Assignee: Tyco Electronics AMP GmbHInventors: Peter Goesele, Friedrich Seger, Josef Sinder, Joachim Stifter, Oliver Werner
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Publication number: 20140264797Abstract: The method includes the steps of: providing a lead frame, including providing a concaved part in an upper face of a joint part of a die-pad-support lead of a lead frame for setting down a die pad and a tie-bar; bonding a semiconductor chip to a first principal face of the die pad via an adhesive-member layer; then, setting the lead frame between first and second molding dies having first and second cavities respectively so that the first and second cavities are opposed to each other, and the second principal face of the die pad faces toward the second cavity; and forming first and second resin sealed bodies on the sides of the first and second principal faces of the die pad respectively by resin sealing with the first and second molding dies clamping the tie-bar and a part of the lead frame surrounding the tie-bar.Type: ApplicationFiled: June 2, 2014Publication date: September 18, 2014Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Yusuke OTA, Fukumi SHIMIZU
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Patent number: 8836092Abstract: A lead frame for assembling a semiconductor device has a die pad surrounded by lead fingers. Each of the lead fingers has a proximal end close to but spaced from an edge of the die pad and a distal end farther from the die pad. A semiconductor die is attached to a surface of the die pad. The die has die bonding pads on its upper surface that are electrically connected to the proximal ends of the lead fingers with bond wires. An encapsulation material covers the bond wires, semiconductor die and the proximal ends of the lead fingers. Prior to assembly, hot spots of the die are determined and the lead fingers closest to the hot spots are selected to project closer to the die than the other lead fingers. These longer lead fingers assist in dissipating the heat at the die hot spot.Type: GrantFiled: October 29, 2012Date of Patent: September 16, 2014Assignee: FreeScale Semiconductor, Inc.Inventors: Chetan Verma, Piyush Kumar Mishra, Cheong Chiang Ng
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Patent number: 8816482Abstract: A flip-chip leadframe semiconductor package designed to improve mold flow around the leadframe and semiconductor die. An embodiment of the semiconductor package includes a leadframe, a semiconductor die attached to the leadframe, and an encapsulant covering the leadframe and semiconductor die, wherein a portion of the leadframe that is attached to the semiconductor die is below a portion of the leadframe that enters the encapsulant.Type: GrantFiled: December 9, 2008Date of Patent: August 26, 2014Assignee: United Test and Assembly Center Ltd.Inventors: Saravuth Sirinorakul, Kasemsan Kongthaworn
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Patent number: 8796826Abstract: A device and method for minimizing the forces that may compromise a lead frame mount to a support structure in an integrated circuit die package during various packaging method steps. When a window clamp is used to provide pressure during a lead frame bonding step or during a wire bonding step during packaging, the vertical force applied by the window clamp may be transferred in lateral direction by the physical contour of the top plate of the support structure. By changing the physical contour of the top plate of the support structure, such as by disposing a specific kind of contoured protrusion, one may minimize or eliminate the lateral forces that act against achieving a solid bond of the lead frame to the support structure. Further, during wire bonding, the same minimization or elimination of lateral forces lead to improved wire bonding.Type: GrantFiled: December 22, 2011Date of Patent: August 5, 2014Assignee: STMicroelectronics Pte LtdInventors: Xueren Zhang, Kim-Yong Goh, Wingshenq Wong
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Patent number: 8778739Abstract: A method of manufacturing a lead frame, includes forming a rectangular first dimple includes, first inclined side surfaces inclined to a depth direction, and arranged in two opposing sides in one direction, and standing side surfaces standing upright to a depth direction, and arranged in two opposing sides in other direction, on a backside of a die pad by a first stamping, and forming a second dimple having second inclined side surfaces inclined on the backside of the die pad by a second stamping, such that a second inclined side surfaces of the second dimple are arranged in side areas of the standing side surfaces of the first dimple, wherein the standing side surfaces are transformed into reversed inclined side surfaces inclined to a reversed direction to the first inclined side surfaces, and a front side of the die pad is semiconductor element mounting surface.Type: GrantFiled: January 28, 2013Date of Patent: July 15, 2014Assignee: Shinko Electric Industries Co., Ltd.Inventor: Hitoshi Miyao
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Patent number: 8772923Abstract: A semiconductor device includes: leads (5) in each of which a cutout (5a) is formed; a die pad (11); a power element (1) held on the die pad (11); and a package (6) made of a resin material, and configured to encapsulate inner end portions of the leads (5), and the die pad (11) including the power element (1). The cutout (5a) is located in a region of each of the leads (5) including a portion of the lead (5) located at a boundary between the lead (5) and the package (6), and is filled with a resin material.Type: GrantFiled: January 19, 2012Date of Patent: July 8, 2014Assignee: Panasonic CorporationInventor: Masanori Minamio
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Patent number: 8766418Abstract: A semiconductor device includes a first semiconductor chip; an extension formed at a side surface of the first semiconductor chip; a connection terminal formed on the first semiconductor chip; a re-distribution part formed over the first semiconductor chip and the extension and including an interconnect connected to the connection terminal and an insulating layer covering the interconnect; and an electrode formed above the extension on a surface of the re-distribution part and connected to the interconnect at an opening of the insulating layer. The electrode is mainly made of a material having an elastic modulus higher than that of the interconnect. The electrode includes a bonding region where the electrode is bonded to the interconnect at the opening, and an outer region closer to an end part of the extension. The interconnect is formed so as not to continuously extend to a position right below the outer region.Type: GrantFiled: January 9, 2014Date of Patent: July 1, 2014Assignee: Panasonic CorporationInventors: Teppei Iwase, Takashi Yui
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Patent number: 8759955Abstract: Conventional semiconductor devices have a problem that it is difficult to prevent the short circuit between chips and to improve accuracy in temperature detection with the controlling semiconductor chips. In a semiconductor device of the present invention, a first mount region to which a driving semiconductor chip is fixedly attached and a second mount region to which a controlling semiconductor chip is fixedly attached are formed isolated from each other. A projecting area is formed in the first mount region, and the projecting area protrudes into the second mount region. The controlling semiconductor chip is fixedly attached to the top surfaces of the projecting area and the second mount region by use of an insulating adhesive sheet material. This structure prevents the short circuit between the two chips, and improves accuracy in temperature detection with the controlling semiconductor chip.Type: GrantFiled: January 18, 2013Date of Patent: June 24, 2014Assignee: Semiconductor Components Industries, LLCInventors: Hideyuki Iwamura, Isao Ochiai
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Patent number: 8754510Abstract: A conduction path includes a first conduction path forming plate (11) made of a first metal and having a through hole (13), and a second conduction path forming plate (15) made of a second metal and having a press-fit portion (17) press-fitted into the through hole. A wall surface of the through hole and a side surface of the press-fit portion forms an inclined bonding surface (18) inclined relative to a normal line of an overlap surface of the first conduction path forming plate and the second conduction path forming plate, and a bonding portion (25) formed by metal flow is formed in a region located in a periphery of the inclined bonding surface.Type: GrantFiled: November 30, 2011Date of Patent: June 17, 2014Assignee: Panasonic CorporationInventors: Masanori Minamio, Zyunya Tanaka, Ryoutarou Imura
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Patent number: 8736080Abstract: A sensor array package can include a sensor disposed on a first side of a substrate. Signal trenches can be formed along the edges of the substrate and a conductive layer can be deposited in the signal trench and can couple to sensor signal pads. Bond wires can be attached to the conductive layers and can be arranged to be below a surface plane of the sensor. The sensor array package can be embedded in a printed circuit board enabling the bond wires to terminate at other conductors within the printed circuit board.Type: GrantFiled: September 30, 2012Date of Patent: May 27, 2014Assignee: Apple Inc.Inventors: Shawn X. Arnold, Terry L. Gilton, Matthew E. Last
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Publication number: 20140110827Abstract: A pressed-contact type semiconductor device includes a power semiconductor element, on an upper surface of which at least a first electrode is formed and on a lower surface of which at least a second electrode is formed, lead frames which face the first electrode and the second electrode of the power semiconductor element respectively, and a clip which applies a pressure to the lead frames while the power semiconductor element is sandwiched by the lead frames, wherein a metallic porous plating part is formed on a surface which faces the first electrode or the second electrode, the surface being a surface of at least one of the lead frames.Type: ApplicationFiled: October 19, 2012Publication date: April 24, 2014Applicant: Panasonic CorporationInventors: Norihito Tsukahara, Toshiyuki Kojima, Takayuki Hirose, Keiko Ikuta, Kohichi Tanda
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Patent number: 8704346Abstract: In a package wherein a lead part coupled to a semiconductor element by wire bonding, an element retention member to retain the semiconductor element on the top face side and radiate heat on the bottom face side, and an insulative partition part to partition the lead part from the element retention member with an insulative resin appear, a creeping route ranging from the top face to retain the semiconductor element to a package bottom face on a boundary plane between the element retention member and an insulative partition part includes a bent route having a plurality of turns. Consequently, it is possible to inhibit an encapsulation resin to seal a region retaining the semiconductor element from exuding toward the bottom face side of the package.Type: GrantFiled: November 16, 2010Date of Patent: April 22, 2014Assignee: Sumitomo Chemical Co., Ltd.Inventors: Tatsuhiko Sakai, Kiyomi Nakamura, Yasuo Matsumi
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Patent number: 8692367Abstract: A wafer-level packaged semiconductor device is described. In an implementation, the device includes one or more self-assembled resilient leads disposed on an integrated circuit chip. Each of the resilient leads are configured to move from a first position wherein the resilient lead is held adjacent to the chip and a second position wherein the resilient lead is extended away from the chip to interconnect the chip to a printed circuit board. A guard is provided to protect the resilient leads when the resilient leads are in the first position. One or more attachment bumps may also be furnished to facilitate attachment of the device to the printed circuit board.Type: GrantFiled: October 1, 2012Date of Patent: April 8, 2014Assignee: Maxim Integrated Products, Inc.Inventors: Chiung C. Lo, Arkadii V. Samoilov, Reynante T. Alvarado
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Patent number: 8650748Abstract: A method of fabricating chip carriers suitable for use in packaging integrated circuits and other electronic, electro-mechanical and opto-electronic devices is described. In general, a number of wires (or wires and rods) are arranged in parallel in a wiring fixture. After the wires are positioned, they are encapsulated to form an encapsulated wiring block. The wiring block is then sliced to form a number of discrete panels. Preferably, the various wires are geometrically positioned such that each resulting panel has a large number of device areas defined therein. The encapsulant in each panel effectively forms a substrate and the wire segments in each panel form conductive vias that extend through the substrate. The resulting panels/chip carriers can then be used in a wide variety of packaging applications.Type: GrantFiled: May 12, 2011Date of Patent: February 18, 2014Assignee: National Semiconductor CorporationInventors: Artur Darbinyan, David T. Chin, Kurt E. Sincerbox
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Patent number: 8643156Abstract: A lead frame has a flag, a peripheral frame, and main tie bars coupling the flag to the peripheral frame. At least one cross tie bar extends between two of the main tie bars and an inner row of external connector pads extending from an inner side of the cross tie bar and an outer row of external connector pads extending from an outer side of the cross tie bar. Both an inner non-electrically conductive support bar and an outer non-electrically conductive support bar are attached across the two of the main tie bars. The inner non-electrically conductive support bar is attached to upper surfaces of the two of the main tie bars and to upper surfaces of the inner row of the external connector pads.Type: GrantFiled: September 6, 2012Date of Patent: February 4, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Shunan Qiu, Zhigang Bai, Haiyan Liu
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Patent number: 8618643Abstract: A lead frame includes a first outer lead portion and a second outer lead portion which is arranged to oppose to the first outer lead portion with an element-mounting region between them. An inner lead portion has first inner leads connected to the first outer leads and second inner leads connected to the second outer leads. At least either the first or second inner leads are routed in the element-mounting region. An insulation resin is filled in the gaps between the inner leads located on the element-mounting region. A semiconductor device is configured with semiconductor elements mounted on both the top and bottom surfaces of the lead frame.Type: GrantFiled: July 6, 2011Date of Patent: December 31, 2013Assignee: Kabushiki Kaisha ToshibaInventor: Yoshiaki Goto
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Patent number: 8614502Abstract: A semiconductor assembly board includes a supporting board, a coreless build-up circuitry and a built-in electronic device. The supporting board includes a bump, a flange and a via hole in the bump. The built-in electronic device extends into the via hole and is electrically connected to the build-up circuitry. The build-up circuitry extends from the flange and the built-in electronic device and provides signal routing for the built-in electronic device. The supporting board provides mechanical support, ground/power plane and heat sink for the coreless build-up circuitry.Type: GrantFiled: April 26, 2012Date of Patent: December 24, 2013Assignee: Bridge Semiconductor CorporationInventors: Charles W.C. Lin, Chia-Chung Wang
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Patent number: 8610253Abstract: A lead frame includes a die stage; an inner lead provided near the die stage; and a bus bar provided between the die stage and the inner lead and supported by a hanging lead, wherein the hanging lead is inclined with respect to the inner lead, and a wire connection face of the bus bar is displaced with respect to a wire connection face of the inner lead in a direction of a frame thickness.Type: GrantFiled: June 27, 2011Date of Patent: December 17, 2013Assignee: Fujitsu Semiconductor LimitedInventors: Takahiro Yurino, Hiroshi Aoki, Tatsuya Takaku
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Patent number: 8525307Abstract: A semiconductor device includes a lead frame, a semiconductor element mounted on the lead frame, and a frame-like member formed on the lead frame, surrounding the semiconductor element, and covering a side surface of the lead frame and exposing a lower surface of the lead frame. The frame-like member has at least one concave portion in a side surface thereof. The concave portion has a ceiling portion located at the same height as or lower than an upper surface of the lead frame, and a bottom portion located higher than the lower surface of the lead frame.Type: GrantFiled: July 27, 2011Date of Patent: September 3, 2013Assignee: Panasonic CorporationInventors: Kenichi Ito, Shigehisa Oonakahara, Yoshikazu Tamura, Kiyoshi Fujihara
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Patent number: 8525311Abstract: A lead frame for a semiconductor device has a die pad with a first major surface for receiving an semiconductor die and a connection bar that encircles the die pad. First lead fingers that project from the connection bar towards the die pad have proximal ends close to the die pad and distal ends connected to the connection bar. The proximal ends of the first lead fingers lie in a first plane. Second lead fingers that project from the connection bar towards the die pad have proximal ends close to the die pad and distal ends connected to the connection bar. The proximal ends of the second lead fingers lie in a second plane that is parallel and spaced from the first plane. An isolation frame is disposed between the proximal ends of the first and second lead fingers. The isolation frame separates but supports the proximal ends of the first and second lead fingers.Type: GrantFiled: June 28, 2011Date of Patent: September 3, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Zhigang Bai, Jinzhong Yao, Xuesong Xu
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Patent number: 8492882Abstract: A semiconductor device has a die pad, a heat dissipating plate in the form of a frame arranged between the die pad and leads so as to surround the die pad, members that connect the die pad and the inner edge of the heat dissipating plate, and a suspension lead linked to the outer extension of the heat dissipating plate. A semiconductor chip larger than the die pad is mounted over the die pad and the members. Top surfaces of the die pad and the members in opposition to the back surface of the chip are bonded to the back surface of the chip with silver paste. Heat is conducted from the back surface of the chip to the heat dissipating plate via the silver paste, the die pad, and the members, and dissipated to the outside of the semiconductor device via the leads.Type: GrantFiled: May 4, 2012Date of Patent: July 23, 2013Assignee: Renesas Electronics CorporationInventors: Junichi Arita, Kazuko Hanawa, Makoto Nishimura
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Publication number: 20130168840Abstract: A semiconductor integrated device is provided with: a die having a body of semiconductor material with a front surface, and an active area arranged at the front surface; and a package having a support element carrying the die at a back surface of the body, and a coating material covering the die. The body includes a mechanical decoupling region, which mechanically decouples the active area from mechanical stresses induced by the package; the mechanical decoupling region is a trench arrangement within the body, which releases the active area from an external frame of the body, designed to absorb the mechanical stresses induced by the package.Type: ApplicationFiled: December 18, 2012Publication date: July 4, 2013Applicants: STMICROELECTRONICS S.R.L., STMICROELECTRONICS (GRENOBLE 2) SASInventors: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics S.r.l.
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Patent number: 8445998Abstract: A semiconductor package includes a lead structure upon which a semiconductor die is mounted with at least some portion of at least some of the leads extending to, at, or across an axis or axis of the package to militate against thermally induced growth of the package and the reduce or minimize strain within the package and reliability issue associated therewith.Type: GrantFiled: February 24, 2010Date of Patent: May 21, 2013Assignee: Intersil Americas Inc.Inventors: Young-Gon Kim, Nikhil Vishwanath Kelkar, Louis Elliott Pflughaupt
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Patent number: 8410587Abstract: An integrated circuit package system includes a leadframe with leads configured to provide electrical contact between an integrated circuit chip and an external electrical source. Configuring the leads to include outer leads, down set transitional leads, and down set inner leads. Connecting the integrated circuit chip electrically to the down set inner leads. Depositing an encapsulating material to prevent exposure of the down set inner leads.Type: GrantFiled: August 20, 2009Date of Patent: April 2, 2013Assignee: STATS ChipPAC Ltd.Inventors: Taesung Lee, Jae Soo Lee, Geun Sik Kim
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Patent number: 8390105Abstract: A lead frame substrate, including: a metal plate having a first surface and a second surface; a semiconductor element mount portion and a semiconductor element electrode connection terminal that are formed on the first surface; an external connection terminal formed on the second surface and electrically connected to the semiconductor element electrode connection terminal; a conducting wire that connects the semiconductor element electrode connection terminal and the external connection terminal to each other; a resin layer formed on the metal plate; a hole portion that is partly formed in the second surface of the metal plate and does not penetrate the metal plate; and a plurality of protrusions that are formed on a bottom surface of the hole portion and protrude in a direction away from the metal plate, the protrusions having a height lower than a position of the second surface, not being in electrical conduction with the conducting wire, and being dispersed separately.Type: GrantFiled: September 28, 2009Date of Patent: March 5, 2013Assignee: Toppan Printing Co., Ltd.Inventors: Junko Toda, Susumu Maniwa, Yasuhiro Sakai, Takehito Tsukamoto
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Patent number: 8384228Abstract: Embodiments of a microelectronic package are generally described herein. A microelectronic package may include a lead frame including a major surface, and a die having including a bond pad. A wire may electrically couple a location of the major surface of the lead frame with the bond pad of the die, the wire being situated such that the wire is substantially unbent from the location of the major surface to an edge of the lead frame.Type: GrantFiled: April 29, 2009Date of Patent: February 26, 2013Assignee: Triquint Semiconductor, Inc.Inventors: Howard Bartlow, William McCalpin, Binh Le
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Patent number: 8378469Abstract: Apparatus and methods are provided for integrally packaging antennas with semiconductor IC (integrated circuit) chips to provide highly-integrated and high-performance radio/wireless communications systems for millimeter wave applications including, e.g., voice communication, data communication, and radar applications. For example, wireless communication modules are constructed with IC chips having receiver/transmitter/transceiver integrated circuits and planar antennas that are integrally constructed from BEOL (back end of line) metallization structures of the IC chip.Type: GrantFiled: July 30, 2007Date of Patent: February 19, 2013Assignee: International Business Machines CorporationInventors: Brian P. Gaucher, Duixian Liu, Ullrich R. Pfeiffer, Thomas M. Zwick
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Patent number: 8355258Abstract: An orthogonal array is formed by performing electromagnetic field analysis only once and determining a range by using the mount position and type of a capacitor and the number of capacitors as parameters to perform circuit analysis a small number of times. An estimation equation is formed by using as an index a result of the absolute value of the calculated power source impedance, and a capacitor is disposed to reduce noises by using the estimation equation.Type: GrantFiled: June 7, 2011Date of Patent: January 15, 2013Assignee: Hitachi, Ltd.Inventors: Hideki Osaka, Yutaka Uematsu
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Patent number: 8334467Abstract: An electronic device package 100 comprising a lead frame 150 having at least one lead 110 with a notch 205. The notch includes at least one reentrant angle 210 of greater than 180 degrees and the notch is located distal to a cut end 1010 of the lead.Type: GrantFiled: June 17, 2009Date of Patent: December 18, 2012Assignee: LSI CorporationInventors: Larry W. Golick, Qwai Hoong Low, John W. Osenbach, Matthew E. Stahley
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Publication number: 20120280375Abstract: In a package wherein a lead part coupled to a semiconductor element by wire bonding, an element retention member to retain the semiconductor element on the top face side and radiate heat on the bottom face side, and an insulative partition part to partition the lead part from the element retention member with an insulative resin appear, a creeping route ranging from the top face to retain the semiconductor element to a package bottom face on a boundary plane between the element retention member and an insulative partition part includes a bent route having a plurality of turns. Consequently, it is possible to inhibit an encapsulation resin to seal a region retaining the semiconductor element from exuding toward the bottom face side of the package.Type: ApplicationFiled: November 16, 2010Publication date: November 8, 2012Applicant: SUMITOMO CHEMICAL CO., LTD.Inventors: Tatsuhiko Sakai, Kiyomi Nakamura, Yasuo Matsumi
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Patent number: 8304868Abstract: A pallet (501) supporting a half-etched leadframe with cantilever-type leads (403) without metallic supports during the step of attaching components (510) to the leads in order to assemble an electronic system. After assembly, the pallet is removed before the molding step that encapsulates (601a) the components on the leadframe and mechanically supports (601b) the cantilever leads. The pallet is machined from metal or inert plastic material, tolerates elevated temperatures during soldering, and is reusable for the next assembly batch.Type: GrantFiled: October 12, 2010Date of Patent: November 6, 2012Assignee: Texas Instruments IncorporatedInventors: Michael G Amaro, Steven A Kummerl, Taylor R Efland, Sreenivasan K Koduri
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Patent number: 8278748Abstract: A wafer-level packaged semiconductor device is described. In an implementation, the device includes one or more self-assembled resilient leads disposed on an integrated circuit chip. Each of the resilient leads are configured to move from a first position wherein the resilient lead is held adjacent to the chip and a second position wherein the resilient lead is extended away from the chip to interconnect the chip to a printed circuit board. A guard is provided to protect the resilient leads when the resilient leads are in the first position. One or more attachment bumps may also be furnished to facilitate attachment of the device to the printed circuit board.Type: GrantFiled: February 17, 2010Date of Patent: October 2, 2012Assignee: Maxim Integrated Products, Inc.Inventors: Chiung C. Lo, Arkadii V. Samoilov, Reynante Alvarado
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Patent number: 8258609Abstract: An integrated circuit package system is provided including forming a paddle having an integrated circuit die thereover, an outer lead, and an inner lead between the paddle and the outer lead. The integrated circuit package system is also provided including placing a lead support over the inner lead without traversing to an inner body bottom side of the inner lead, connecting the integrated circuit die and the inner lead, and encapsulating the inner lead having the lead support thereover and the inner lead exposed.Type: GrantFiled: March 21, 2007Date of Patent: September 4, 2012Assignee: Stats Chippac Ltd.Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Jose Alvin Caparas, Arnel Trasporto
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Patent number: 8241958Abstract: To provide a semiconductor device and a semiconductor module in which breakage of a semiconductor element due to a pressing force given from the outside is prevented. A semiconductor device according to the present invention has a configuration mainly including an island, a semiconductor element mounted on a front surface of the island, a lead that functions as an external connection terminal, and a sealing resin that covers these components in an integrated manner and mechanically supports them. Further, a through-hole is provided so as to penetrate the sealing resin. A front surface of the sealing resin around the through-hole forms a flat part. The front surface of the sealing resin that overlaps the semiconductor element is depressed inward with respect to the flat part to form a depressed part.Type: GrantFiled: October 14, 2010Date of Patent: August 14, 2012Assignees: SANYO Semiconductor Co., Ltd., Semiconductor Components Industries, LLCInventor: Haruhiko Sakai
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Patent number: 8237250Abstract: The advanced quad flat non-leaded package structure includes a carrier, a chip, a plurality of wires, and a molding compound. The carrier includes a die pad and a plurality of leads. The leads include first leads disposed around the die pad, second leads disposed around the first leads and at least an embedded lead portion between the first leads and the second leads. The wires are disposed between the chip, the first leads and the embedded lead portion. The advanced quad flat non-leaded package structures designed with the embedded lead portion can provide better electrical connection.Type: GrantFiled: April 17, 2009Date of Patent: August 7, 2012Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Pao-Huei Chang Chien, Ping-Cheng Hu, Po-Shing Chiang, Wei-Lun Cheng
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Patent number: 8193041Abstract: The yield of a semiconductor device is improved. Inside the resin sealing body which forms a semiconductor device, the semiconductor chip is sealed in the state where it has arranged aslant to the upper and lower sides of a resin sealing body. In the suspension lead which supports the die pad carrying this semiconductor chip, the small recess is formed in the fifth surface of the opposite side with the surface on which the semiconductor chip was mounted. This recess is a portion used as the starting point when making die pad 2a slanting. The side surface of the side near a die pad between two side surfaces of this recess is formed in the state where it inclined rather than the side surface of the side near the periphery of a resin sealing body.Type: GrantFiled: October 31, 2007Date of Patent: June 5, 2012Assignee: Renesas Electronics CorporationInventor: Shigeki Tanaka
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Patent number: RE43443Abstract: In order to improve the package body cracking resistance of an LSI package at the reflow soldering and to provide both a leadframe suitable for fabricating the LSI package according to the flexible manufacturing system and an LSI using the leadframe, the adhered area between a semiconductor chip 2 and a resin is enlarged by making the external size of a die pad 3 smaller than that of the semiconductor chip to be mounted thereon. Moreover, a variety of semiconductor chips 2 having different external sizes can be mounted on the die pad 3 by cutting the leading ends of leads 5 to a suitable length in accordance with the external sizes of the semiconductor chips 2.Type: GrantFiled: November 16, 2001Date of Patent: June 5, 2012Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.Inventors: Yujiro Kajihara, Kazunari Suzuki, Kunihiro Tsubosaki, Hiromichi Suzuki, Yoshinori Miyaki, Takahiro Naito, Sueo Kawai