Abstract: A highly reliable assembly structure is provided by surely reducing a stress to be exerted on leads of a TCP device. Part of a soldered portion of outer leads that is located closer to a semiconductor chip of the TCP device is reinforced by a support ring formed on a side of the outer leads opposite from a circuit board, so that a stress to be exerted on the outer leads is dispersed to the leads, the support ring and solder to thereby prevent the possible occurrence of metal fatigue of the leads.

Abstract: A light-emitting diode (LED) device has a plurality of mutually separated terminal plates disposed on the bottom part of a horizontally elongated rectangular reflector case having an open front surface. Where a pair of these terminal plates is adjacent to each other with a gap in between, a LED chip is bonded to one of them and connected through a wire to the other. Terminal lead lines are extended from the terminal plates downward through the reflector case. The end parts of such a pair are shaped such that the gap therebetween has an horizontally extended part. When such a LED device is inserted into a groove formed in a light-conducting plate with a specified thickness to form an illuminator with a light-emitting surface, shearing stress is developed inside the reflector case as the terminal lead lines are passed through throughholes in the reflector case but is absorbed by the parts adjacent to such a horizontally extended portion of the gap.

Abstract: An inexpensive pre-molded package for electronic semiconductor circuit with increased thermal extraction capability, improved electrical performance, improved dielectric constant of sealing medium, optically transmissive sealing lid, and partially reduced electromagnetic radiation. In one embodiment, the pre-molded package includes electronic semiconductor circuit, a plurality of electrically conductive leads, a heat spreader, a plurality of electrically conductive bond wires, and a seal lid. Preferably, a surface of the heat spreader remains exposed to the exterior of the pre-molded package. In another embodiment, the pre-molded package includes a semiconductor circuit, a plurality of electrically conductive leads, a heat spreader, a plurality of electrically conductive bond wires, and an optically transmissive seal lid.

Abstract: A microelectronic assembly includes first and second microelectronic elements having confronting surfaces that are spaced apart from one another. Vertically extensive flexible lead elements interconnect electrical connections on the microelectronic elements. Each of the flexible lead elements may include a plurality of curved conductors that are electrically connected and parallel to one another. The lead elements may initially be formed on a lead bearing surface, and have a terminal end for connection to the first microelectronic element, and a tip end for connection to the second microelectronic element. The terminal end is disposed on the lead bearing surface and fixed to it, while the tip end is releasably connected to the lead bearing surface, and spaced apart from the terminal end on an offset axis. Curved leads interconnect the tip end and the terminal end.

Abstract: A rail of non-conductive material is applied to a semiconductor die and/or to the carrier substrate to which it is or will be bonded. The rail underlies those wires joining the die bond pads and substrate traces, which wires have an inordinate length, i.e. greater than about 100 mils for 1.0 mil diameter wires, to prevent sagging wires from contacting the die edge and breaking, or shorting to active areas on the die or substrate. A pattern of rails may be formed on the dice of an undivided wafer by, for example, screen printing. Rails may also be formed on the substrate, and rails on the substrate employed in combination with rails on dice carried thereon.

Abstract: A thin semiconductor device in which a strength of a lead frame and a heat dissipation efficiency can be improved. The semiconductor device has a semiconductor chip, a lead having an inner lead and an a outer lead continuing to the inner lead, said inner lead having a thin plate portion thinner than the other portion therof, said thin plate portion being electrically connected to said semiconductor chip through a wire and said outer lead serving as an outer connecting terminal, and a sealing resin sealing said semiconductor chip and at least a part of said lead, wherin said inner lead of said lead is positioned on said semiconductor chip.

Abstract: Resin tie bars are formed between leads of external leads extending out from a resin-sealed region. The external leads are formed such that lead width at portions beyond the portion where the resin tie bars are formed is less than the lead width at portions where the resin tie bars are formed. With this construction, resin extending between the leads from the periphery of the resin-sealed region, including the resin tie bars, can be easily removed after resin-sealing when the resin tie bars are subjected to water sprayed at high pressure.

Abstract: A semiconductor device has a semiconductor chip mounted on the mounting portion of a lead frame and sealed with resin. The chip is affixed to the lead frame by melting. A groove is formed in the lead frame in a cruciform, radial, lattice or similar pattern capable of reducing thermal stress during intermittent performance test and cycling test while insuring heat radiation.

Abstract: Improved manufacturability, yield, and reliability are achieved during wirebonding of a semiconductor die of reduced size by employing two rows of staggered conductive connectors, or bond pads, for wirebonding the die to a semiconductor package. An outer row of conductive connectors is positioned closer to the edge of the die than an inner row of conductive connectors and includes a greater number of connectors than the inner row. The die can be wirebonded to a package substrate having either a single row of bondfingers or multiple rows of bondfingers. In one embodiment, bond wires attaching the inner row of conductive pad connectors to the package substrate have a greater loop height than bond wires attaching the outer row of conductive pad connectors to the package substrate.

Abstract: A lead frame includes first slits in a lead frame edge in a direction parallel to a longitudinal direction of the lead frame edge at spaced intervals and a plurality of slits in the lead frame edge in a direction parallel to the first slits at spaced intervals so that the second slits are separated from the first slits wherein each end of each of the second slits is located near the center of a corresponding first slit.

Abstract: Disclosed herein are a method of fabricating a power semiconductor device having joiners that (205) vertically extend from outer sides of leads (203, 204) of a tie bar (201) of a power circuit lead frame (20) respectively, while joiners (308) vertically extend from outer sides of leads (303, 307) of a tie bar (301) of a control circuit lead frame (30) respectively to be opposed thereto. Forward end portions (205a) of the joiners (205) are joined to rear surfaces of forward end portions (308a) of the joiners (308) at a device center portion.

Abstract: Between an IC and an IC receptacle is interposed a flexible wiring sheet, via which contact pieces of the IC and contacts of the IC receptacle are held in contact with one another. In this case, lateral deviation and flexing of the wiring sheet are prevented satisfactorily, and proper contact between the IC and IC receptacle is ensured. A back-up frame is applied by adhesive to the flexible wiring sheet to form a contact agency. The back-up frame 11 has a central window 11 to form a non-backed-up region in a central portion of the flexible wiring sheet 3 that covers the window. The IC 3 and flexible wiring sheet are held in forced contact with each other in the non-backed-up region. The back-up frame has an outer edge portion forming a back-up region for backing up an edge portion of the wiring sheet. In this back-up region, the IC receptacle and the flexible wiring sheet 1 are held in contact with each other.

Abstract: A novel radio frequency transponder (tag) with a minimum of components and connects is thin and flexible because these components and connects can be unsupported by a substrate layer. This is accomplished by using a conducting leadframe structure not only as a connection medium but also as a circuit element, i.e., the transponder antenna. In various preferred embodiments, the leadframe is mechanically positioned and fixably attached to a circuit chip so that the leadframe (antenna) is self supporting. A protective coating can be added where the leadframe is attached to the circuit chip. Further a protective surrounding can envelops the entire leadframe antenna, circuit chip, and, if provided, the protective coating.

Abstract: Extension areas of a metal layer electrically connected to the original die bond pad allow for testing connections to be made. In this way, the connection area used for the final packaging of the die will not be damaged. The extension areas can be removed along with the testing connections. The use of perforations and/or underlayer sections can aid in the removal of the extension area. The extension area can extend over a passivation layer so that the basic die design need not be changed.

Abstract: A resin sealing type semiconductor device includes a radiator, a semiconductor element, a frame lead arranged at a distance around this semiconductor element and displaced from the radiator, and a plurality of leads extending from this frame lead and attached to a mounting surface with a insulating lead support therebetween. The leads are pressed downward by an upper mold so that the radiator is pressed against a lower mold in such a manner that resin cannot seep therebetween. Thin portions are formed in the leads to ensure that the leads do not peel away from the insulating lead support.

Abstract: A semiconductor device includes a rigid member embedded in a resin package body for supporting thereon outer leads that extend from the resin package body and test pads provided on the outer leads for testing the semiconductor device.

Abstract: A connection component for a microelectronic device such as a semiconductor chip incorporates a dielectric layer and leads extending across a surface of the dielectric layer. Each lead has one end permanently fastened to the dielectric layer and another end releasably bonded to the dielectric layer. The releasable end is held in place by a bond having a relatively low peel strength, desirably less than about 0.35.times.10.sup.6 dynes/cm.

Abstract: A semiconductor device includes a semiconductor chip; leads including first inner leads and second inner leads extending substantially radially from a central point of the semiconductor chip; electrical conductors electrically connecting the semiconductor chip to the lead frame; and an encapsulating resin encapsulating the semiconductor chip, the electrical conductors, and the inner leads, Each of the first inner leads has a first inner end located proximate the central point and each of the second inner leads has a second inner end located farther from the central point than the first inner ends. The first and second inner leads are alternatingly arranged. Thus, at least some of the inner leads extend under the semiconductor chip, providing heat conducting paths. The lead frame includes a frame and leads supported by the frame and including first inner leads and second inner leads extending substantially radially toward a central point of the frame.

Abstract: A semiconductor chip mounted on an island is electrically connected to inner leads through tape-automated bonding leads supported by an insulating suspender tape, and a support ring is connected between the insulating suspender tape and suspender pins connected to the island so as to maintain an original relative position between the semiconductor chip and the tape-automated bonding leads during a molding stage.

Abstract: The present invention relates to a semiconductor package having lead pins of lead frame for outwardly extending terminals of electrodes of a semiconductor chip embedded in a mold resin. The semiconductor package according to the present invention comprises flat lead fins connected to respective sides of a bed portion of a lead frame, an insulation film for covering at least one side of each of the lead fins, and lead pins formed on a surface of the insulation film, the lead pins being disposed at a predetermined pitch.

Abstract: A chip mounting plate construction of lead frames for semiconductor packages which provides a chip mounting plate having a greatly reduced area to obtain a small bonding area between the chip mounting plate and a semiconductor chip mounted on the chip mounting plate, thereby capable of minimizing thermal strain generated at the chip mounting plate due to a thermal expansion thereof. The chip mounting plate is constructed to have a smaller area than the semiconductor chip, to have a central opening, or to have recesses.

Abstract: A semiconductor device includes a semiconductor chip having electrode pads on the semiconductor chip, the electrode pads including a predetermined electrode. A plurality of leads are electrically connected to the electrode pads on the semiconductor chip, the leads including a predetermined lead electrically connected to the predetermined electrode. A resin package encloses the semiconductor chip and partially encloses the leads. A bypass lead portion electrically connects one of the leads, not adjacent to the predetermined electrode, to a location adjacent to the predetermined electrode, the bypass lead portion being enclosed in the resin package. A supporting lead supports the bypass lead portion such that the supporting lead prevents a deformation of the bypass lead portion, the supporting lead being enclosed in the resin package.

Abstract: A lead frame for use with a plastic encapsulated semiconductor device includes a tab on which the semiconductor chip is mounted, chip pad supporting leads, inner leads to be electrically coupled with the semiconductor chip, outer leads formed in a monoblock structure together with the inner leads, and a frame for supporting the chip pad supporting leads and outer leads. In the lead frame, there is disposed a dam member only between the outer leads. Alternatively, dummy outer leads are formed between the frame and leads adjacent thereto so as to connect the dummy leads to the outer leads by the dam member. The frame is removed after the semiconductor device is assembled.

Abstract: In order to improve the package body cracking resistance of an LSI package at the reflow soldering and to provide both a leadframe suitable for fabricating the LSI package according to the flexible manufacturing system and an LSI using the leadframe, the adhered area between a semiconductor chip 2 and a resin is enlarged by making the external size of a die pad 3 smaller than that of the semiconductor chip to be mounted thereon. Moreover, a variety of semiconductor chips 2 having different external sizes can be mounted on the die pad 3 by cutting the leading ends of leads 5 to a suitable length in accordance with the external sizes of the semiconductor chips 2.

Abstract: In a remote tie-bar lead frame 10 rising an island 4 for bearing a semiconductor chip, one pair of hanger pins 1 for supporting the island 4, a number of outwardly extending leads 2 located to surround the island 4 separately from the island 4, and a pair of tie-bars 6 for mutually tying the leads so as to prevent a flow-out of a resin when a resin packaging is carried out, one pair of wing leads 3A outwardly extend from a pair of opposite sides of the island 4 orthogonal to the pair of opposite sides from which the hanger pins 1 extends. Each of the wing leads 3A extends between a pair of adjacent leads, but terminates to slightly outwardly project from a mold line 5.

Abstract: A leadframe for semiconductor derides having patterned die-mounting structures arranged along the longitudinal axis of the leadframe. Each of the structures contains a die pad for mounting a semiconductor device chip thereon, die pad supports for supporting the die pad, fingers for forming inner leads and outer leads, and tiebars for preventing leakage of a molding material during a molding process. At least one of the die pad supports has a first communication path through which a molding material flows from one side of the body to the other thereof. The molding material supplied into one side of the leadframe can flow to the other side thereof through not only the gaps between the die pad and the body but also the first communication path during a molding process, resulting in a small flow rate difference of the molding material. Failures such as visible voids and no fillings are not produced in the plastic-molding package.

Abstract: A semiconductor package including a semiconductor chip having at its upper surface a plurality of bonding pads and a tape lead frame having a paddle on which a semiconductor chip is laid, a plurality of inner leads each having a sufficient length to be directly connected with each corresponding bonding pad of the semiconductor chip and a plurality of outer leads each connected with each corresponding inner lead and having a thickness larger than that of the inner lead. The semiconductor chip is die bonded on the paddle of the tape lead frame. An insulating layer is formed over the upper surface of the semiconductor chip except for portions corresponding the bonding pads. Each inner lead has at its one end a bonding bumper for electrically connecting the inner lead with each corresponding bonding pad. Using the epoxy molding compound, the inner leads and the paddle of the tape lead frame, the semiconductor and the insulating layer are molded.

Abstract: In a TCP (tape carrier package) semiconductor device having opposing, inner lead arrays bonded to a semiconductor device, a projection or projections are provided on each of the inner leads disposed at intervals of a greater distance on one side of the semiconductor, within a range for allowing the resin to flow out.

Abstract: Semiconductor rectifier devices having oppositely extending terminals lying in a common plane are fabricated using upper and lower lead frames each comprising a pair of parallel side rails and spaced apart cross bars extending between the side rails. Cantilevered terminals are mounted along the cross bars. The cross bars of the upper frame lie in a plane downwardly off-set from the plane of the upper frame, and the cross bars of the lower frame lie in a plane upwardly off-set from the plane of the lower frame. Free ends of the terminals of the upper frame lie in a plane upwardly off-set from the plane of the upper frame cross bars, and free ends of the terminals of the lower frame are off-set downwardly from the plane of the lower frame cross bars. Semiconductor chips are mounted on the terminal free ends of the lower frame, and the upper frame is disposed on top of the lower frame with the upper frame terminals contacting the chips.

Abstract: A lead frame includes a die pad on which a semiconductor chip is mounted, a plurality of leads each having an end which faces the die pad, and tie bars connecting the leads, wherein each of the tie bars is formed so as to project from a surface of each of the leads by an amount sufficient to break a boundary between a tie bar and a lead when the tie bar is pushed back so that the tie bar and lead is separated. The method for producing a semiconductor device using the above lead frame includes steps of clamping by molding dies the lead frame having the semiconductor chip mounted on the die pad so that the tie bar is pushed back and cut off and encapsulating the semiconductor chip by resin so that a package made of the resin is formed, and releasing the lead frame from clamping by the molding dies and removing the tie bar pushed back by the clamping from the lead frame.

Abstract: A low-cost leadframe in which leads are stably and securely retained. The leadframe is provided with a lead retaining section for securely retaining internal leads together. Such a lead retaining section is molded from the same thermosetting resin as used for molding a resin encapsulated package and formed on the internal leads on the side of a die pad such that it extends, in the form of a strip, over the surfaces of the internal leads arranged in rows and such that it is adhered to the internal leads and embedded in the gaps between the internal leads.

Abstract: A lead on chip (LOC) semiconductor leadframe package provides notched lead-fingers to eliminate mechanical shear-stress at the peripheral edge of a semiconductor chip. Opposite rows of substantially flat cantilevered lead-fingers are attached by double-sided adhesive tape in thermal contact with the active face of a chip. The lead-fingers are routed in personalized paths over the face of the chip to cover a large surface area to aid heat dissipation. All wirebond connections between the lead-fingers and the chip are made at a centerline connection strip running down the center of the chip. Each of the cantilevered lead-fingers has a notched portion positioned directly over the vulnerable peripheral chip edge to reduce thermal, mechanical shear-stress. Additionally, since corrosion typically follows a lead path, the notch provides an increasing path length to prevent corrosive ingress over the chip face.

Abstract: A lead frame for use in producing of a semiconductor integrated circuit comprises a lead frame member, a plurality of leads, a tie bar, a plurality of auxiliary leads, a support-stay portion and a connecting portion. A semiconductor element such as an IC chip is mounted on a semiconductor-element-mounting portion of the lead frame member, while the leads are arranged along and extending from a side portion of the lead frame member. The tie bar is connected among the leads and auxiliary leads at their tip-edge portions. Herein, the auxiliary leads are electrically unconnected from the semiconductor element. Further, the support-stay portion is provided at a corner portion of the lead frame member. The connecting portion is provided between a base-edge portion of the support-stay portion and a base portion of the auxiliary lead. A location of the connecting portion is selected in such a manner than the connecting portion will be unaffected by bending of the leads.

Abstract: Lead systems of the subject invention include "coplanar leads" and "aplanar leads", which differ in structure at the inner bond finger. Coplanar leads are generally planar along the lead body and the inner bond finger. Aplanar leads are bent or deformed at the inner bond finger, such that the inner bond finger terminus is not in the plane of the lead body but instead is above or below the plane of the lead body. Deforming select inner bond fingers out of the general plane of the lead system provides a spatial separation for the bonding wires which are attached to the inner bond fingers. This spatial separation acts to minimize wire crossing and shorting during fill processes and results in improved semiconductor package yield.

Abstract: A flagless semiconductor device (10) includes a semiconductor die (22) having a plurality of bond pads (26) which are electrically coupled to a plurality of leads (16) by wire bonds (28). The die is supported by two cantilevered tie bars (18). Use of cantilevered tie bars decreases the total plastic-metal interface area in a plastic encapsulated device, thereby lessening the probability of internal delamination and package cracking. The cantilevered tie bars also permit a variety of die sizes to be used with the same lead frame design. Suitable configurations for cantilevered tie bars include, but are not limited to, U-shape, T-shape, and H-shape configurations.

Abstract: There is provided a base for an electronic package. The base includes a peripheral portion for a polymer adhesive and a central portion for one or more semiconductor devices. A lead support is adjacent the substrate and located between the peripheral portion and the central portion. When a polymer adhesive bonds a leadframe to the package base, the lead support prevents deflection of the inner lead tips.

Abstract: A lead frame having layered conductive planes is disclosed for use in semiconductor devices. The lead frame includes a plurality of long leads each having a lead tip and a plurality of short leads. Electrically conductive layers are attached to the long leads around such that they don't cover the tips of the long leads and are radially inward of the short leads. The conductive layers are insulated from the long lead and each other by adhesive insulating layers. In a preferred embodiment, the top conductive layer has a smaller width than the bottom conducting layer and is positioned to expose an inner and outer ledge on the bottom conducting layer. The exposed outer ledge allows bonding to the shorter leads. The use of shorter leads decreases the amount of inductance in the leads. The conductive layers also may act as capacitors. In one embodiment of the present application the short leads may correspond to ground and/or power leads.

Abstract: A semiconductor device includes a rectangular semiconductor chip bonded to a die pad of a lead frame in which a plurality of leads are arranged around the die pad. An area where the semiconductor ship is electrically connected with the leads around the semiconductor chip and the semiconductor chip are sealed with a resin. A distance between the semiconductor chip and a peripheral wall of the die pad is larger at a central portion of each side of the chip than at each corner of the chip. The leads are arranged such that a line connecting all lead ends is substantially parallel with the peripheral wall of the die pad.

Abstract: A semiconductor integrated circuit device and method of making same wherein recessed bus bar regions are provided in an elongated bus bar to accommodate bonding wires which couple the device's chip pads and associated inner leads. Fillets are formed of insulative adhesive material (from the tape used to secure the leads and bus bar to the chip) up about the bus bar region sides to thereby engage the bonding wires to prevent contact between the wires and bus bar.

Abstract: A leadframe according to this invention is formed by bonding a single leadframe with a substrate using adhesive film or double-sided adhesive resin film, which is divided and attached to two or more predetermined points between them. This reduces the quantity of gas or contaminants generated from adhesives. Also, this results in the reduction of the stress generated during heat treatment of the leadframe and also in the elimination of warping of the lead frame due to thermal stress. Cracking does not occur on the resin because resin is removed easily and assuredly, and no air is left behind. This contributes to high reliability and increased productivity. The lead frame is further formed by bonding a plurality of metal substrates of different materials to single leadframe. This through more stable thermal behavior high reliability.

Abstract: A semiconductor device (10) includes a lead frame (12) having tie bars (16). In one form of the invention, the tie bars are used to support a semiconductor die (20) to alleviate package cracking problems caused by stress and to provide a universal lead frame which is suitable for use with many different die sizes. In another embodiment, a semiconductor device (45) includes a lead frame (40) having a mini-flag (42) to accomplish these same objectives.

Abstract: A tape carrier package has a base film and leads formed on one side of the base film. The base film defines a device hole therein, while the leads have outer portions to be bonded to a substrate and inner lead portions extending into the device hole. The tape carrier package can be mounted on a substrate by applying a high-frequency electromagnetic field to a portion of each lead which is to be bonded to the substrate, whereby solder applied to the lead or substrate in advance is heated and melted to bond the package to the substrate.

Abstract: A semiconductor device (10) has a lead-on-chip (LOC) configuration. Leads (24) of the device have central portions (36) which are electrically coupled to peripheral bond pads (14) by conductive wires (30). Inner portions (38) of the leads extend from the central portions toward centerline A--A for improved adhesion and to provide an internal clamping area (41) which stabilizes the leads during wire bonding. In one embodiment, tie bar (22) of leadframe (16) is used to distribute power across semiconductor chip (12). The leadframe may also include chip alignment features (50) and tape alignment features (52) to align chip (12) and insulating tape (18) to the leadframe, respectively.

Abstract: A semiconductor device (10) includes a lead frame (12) having tie bars (16). In one form of the invention, the tie bars are used to support a semiconductor die (20) to alleviate package cracking problems caused by stress and to provide a universal lead frame which is suitable for use with many different die sizes. In another embodiment, a semiconductor device (45) includes a lead frame (40) having a mini-flag (42) to accomplish these same objectives.

Abstract: A lead frame has a die pad with an array of surrounding leads connected at their sides by tie bars and at their ends by coupling bars which are connected through narrow supports to surrounding side rails or partition frames. Positioning holes are provided as positioning references in the coupling bars when the coupling parts of the leads such as the tie bars are removed to separate the leads from the lead frame.

Abstract: A low inductance lead frame (10) is formed to have a die attach area (11). A plurality of intermediate connection bars (12,13,14,15) are positioned to be parallel to sides of the die attach area (11), and to be in a plane that is displaced perpendicularly from the die attach area (11). Each end of each intermediate connection bar is separated from an end of each other intermediate connection bar. Supports (17) extend from the die attach area (11) to the intermediate connection bars (12,13,14,15) to provide support for the intermediate connection bars 12,13,14,15). A plurality of leads (19,33,34) are positional in a plane and have a proximal end near the intermediate connection bars (12,13,14,15).

Abstract: A semiconductor assembly comprises a semiconductor die which is attached by a carrier material to a lead frame. The carrier material is coated on the die side with one type of adhesive and on the lead frame side with a different adhesive. The lead frame has a small surface area to connect to the carrier material, while the semiconductor die has a large surface area to connect to the carrier material. As used with one inventive embodiment, the adhesive between the die and the carrier softens at a low temperature preventing the die from cracking at elevated temperatures. The adhesive on the lead frame side of the carrier material softens at a higher temperature than the adhesive of the die side of the adhesive, thereby firmly connecting the lead frame having a small surface area to the carrier.

Abstract: A semiconductor device has a lead, an inner lead of which is upwardly bent while an outer lead is downwardly bent. A junction part of the outer lead is guided from a resin block on a level which is lower than that of an upper major surface of the semiconductor chip. In fabrication of this semiconductor device, a guide frame of a lead frame, a suspending lead and a die pad held by the same are flush with each other.

Abstract: The invention involves a TAB (tape automated bonding) tape which includes an electrically conductive layer and a supporting layer. Significantly, the supporting layer includes at least one peeling-prevention slit adjacent a part of the electrically conductive layer which is apt to peel off from the supporting layer when the TAB tape is subjected to stresses, such as thermally-induced stresses and bending stresses.

Abstract: Deformation of TAB tapes due to temperature changes is prevented by thermo-mechanical leads. In one embodiment of the invention, a semiconductor device (30) includes an electronic component (31) and a TAB tape. The tape includes a carrier film (12) and electrical leads (20) formed on the carrier film. The electrical leads are electrically coupled to the electronic component. Also included on the carrier film are thermo-mechanical leads (32) which are formed in opposing regions of the carrier film, regions which are typically void of leads. The thermo-mechanical leads have approximately the same lead pitch as the electrical leads in order to provide a uniform distribution of stresses across the TAB tape upon exposure to varying temperatures.