Abstract: A power semiconductor device is disclosed having a power semiconductor element with an upper and lower side, the upper side being located opposite to the lower side; a first and second electrode, and a housing, wherein the power semiconductor element is arranged between the first and second electrode such, that the upper side comprises a first contact portion being in contact with the first electrode and a first free portion not being in contact with the first electrode, and wherein the lower side at least comprises a second contact portion being in contact with the second electrode, and wherein a channel is provided fluidly connecting at least a part of the first free portion with a predetermined degassing point of the housing for guiding an overpressure, which overpressure results from plasma and/or gas occurring in a failure mode, from the first free portion to the predetermined degassing point.

Abstract: Routing of a gate signal for controlling a discrete power switching device (such as in an inverter for an electric vehicle drive) is configured to compensate for the common source inductance inherent in the switching device as a result of its integrated circuit packaging. The power device has a gate signal path via a gate pin and a power signal path via first and second power pins, wherein the gate signal path and the power signal path have a first mutual inductance. A circuit board apparatus provides a gate wiring loop juxtaposed with the power signal path, wherein the gate wiring loop and the power signal path have a second mutual inductance substantially canceling the first mutual inductance. The resulting reduction in common source inductance avoids the reductions in switching speed and the increased switching losses otherwise introduced by the common source inductance.

Abstract: The baseplate of a power semiconductor device module makes reliable and superior thermal contact with a heatsink when fixed to the heatsink. The baseplate includes a rectangular plate portion, a first downward-extending peripheral heel extension portion, and a second downward-extending peripheral heel extension portion. In one example, the plate portion has four mounting holes for receiving mounting bolts. There is one mounting hole located adjacent each of four corners of the rectangular plate portion. The central portion of the bottom surface of the plate portion has a slightly convex downward shape. The strip-shaped first heel extension portion extends along a first edge of the bottom surface. The strip-shaped second heel extension portion extends along a second edge of the bottom surface opposite the first edge. Each of the first and second heel extension portions extends downward from the bottom surface for a distance of between thirty and five hundred microns.

Abstract: A device arrangement may include an electronic device at least partially enclosed in a device casing. A casing may at least partially delimit a casing interior. The device casing may be disposed in the casing interior. A pressure reduction device may be arranged in the device casing and be configured to reduce a gas pressure of an ignitable gas mixture disposed in at least one of the casing and the device casing. The pressure reduction device may include at least one damping element and a stabilizing device at least partially encasing the at least one damping element.

Abstract: A semiconductor device 100 includes a first insulating material 110 attached to a second main surface 106b of a semiconductor chip 106, and a second insulating material 112 attached to side surfaces of the semiconductor chip 106, the first insulating material 110 and an island 102. The semiconductor chip 106 is fixed to the island 102 via the first insulating material 110 and the second insulating material 112. The first insulating material 110 ensures a high dielectric strength between the semiconductor chip 106 and the island 102. Though the second insulating material 112 having a modulus of elasticity greater than that of the first insulating material 110, the semiconductor chip 106 is firmly attached to the island 102.

Abstract: A housing for a power semiconductor, providing a compartment for installation of a power semiconductor, and including a first and a second terminal. The terminals are for connection of a power semiconductor installed in the compartment, and for leading current to and from the compartment. The housing includes a contact mechanism for bypassing the compartment, the contact mechanism including at least one movable contact arranged for electrically connecting the first and second terminal, the at least one movable contact being movable between a disconnected first position and a connected second position. The contact mechanism further includes a bypass actuator arranged inside the compartment and provided for transforming a pressure from an exploding semiconductor into motion, the bypass actuator is operatively connected to the movable contact and arranged to move the movable contact from the first to the second position when subjected to the pressure of an exploding semiconductor.

Abstract: A semiconductor module has a carrier, a semiconductor chip mounted on the carrier, a bond wire, a module housing, and a first sound absorber. The module housing has a housing side wall. The bond wire is arranged in the module housing. At least a section of the first sound absorber is arranged between the semiconductor chip and the housing side wall.

Abstract: A semiconductor module includes an electrically conductive lower contact piece and an electrically conductive upper contact piece spaced apart from one another in a vertical direction. The module further includes a semiconductor chip having a first load connection and a second load connection. The semiconductor chip is electrically conductively connected by the second load connection to the lower contact piece, and electrically conductively connected to the upper contact piece by at least one bonding wire bonded to the first load connection. An explosion protection means is arranged between the first load connection and the upper contact piece and into which each of the bonding wires is embedded over at least 80% or over at least 90% of its length.

Abstract: Provided is a stress-relieving, second-level interconnect structure that is low-cost and accommodates thermal coefficient of expansion (TCE) mismatch between low-TCE packages and printed circuit boards (PCBs). The interconnect structure comprises at least a first pad, a supporting pillar, and a solder bump, wherein the first pad and supporting pillar are operative to absorb substantially all plastic strain, thereby enhancing compliance between the two electronic components.

Abstract: Methods of and devices for providing escaping routes for the flux and gases generated to move away from the solder joint in the process of solder joint formation.

Abstract: Methods and apparatus for flip chip substrates with guard rings. An embodiment comprises a substrate core with a die attach region for attaching an integrated circuit die; at least one dielectric layer overlying a die side surface of the substrate core; and at least one guard ring formed adjacent a corner of the substrate core, the at least one guard ring comprising: a first trace overlying the dielectric layer having rectangular portions extending in two directions from the corner of the substrate core and in parallel to the edges of the substrate core; a second trace underlying the dielectric layer; and at least one via extending through the dielectric layer and coupling the first and second traces; wherein the first trace, the at least one via, and the second trace form a vertical via stack. Methods for forming the flip chip substrates with the guard rings are disclosed.

Abstract: A housing for a power semiconductor, providing a compartment for installation of a power semiconductor, and including a first and a second terminal. The terminals are for connection of a power semiconductor installed in the compartment, and for leading current to and from the compartment. The housing includes a contact mechanism for bypassing the compartment, the contact mechanism including at least one movable contact arranged for electrically connecting the first and second terminal, the at least one movable contact being movable between a disconnected first position and a connected second position. The contact mechanism further includes a bypass actuator arranged inside the compartment and provided for transforming a pressure from an exploding semiconductor into motion, the bypass actuator is operatively connected to the movable contact and arranged to move the movable contact from the first to the second position when subjected to the pressure of an exploding semiconductor.

Abstract: A semiconductor module includes an electrically conductive lower contact piece and an electrically conductive upper contact piece spaced apart from one another in a vertical direction. The module further includes a semiconductor chip having a first load connection and a second load connection. The semiconductor chip is electrically conductively connected by the second load connection to the lower contact piece, and electrically conductively connected to the upper contact piece by at least one bonding wire bonded to the first load connection. An explosion protection means is arranged between the first load connection and the upper contact piece and into which each of the bonding wires is embedded over at least 80% or over at least 90% of its length.

Abstract: A power semiconductor module system. One embodiment provides a power semiconductor module and a mounting adapter. The mounting adapter and the power semiconductor module can be latched to one another in two different latching stages such that a contact element of the power semiconductor module makes electrical contact with a contact element of the mounting adapter assigned to the contact element in a second one of the latching stages but not in a first one of the latching stages.

Abstract: A power semiconductor module for energy distribution, includes at least one power semiconductor, connection terminals for connecting the power semiconductor module, and a housing, in which protection from explosion is ensured in the module even in the event of electric arcs. Therefore, each power semiconductor and each connection terminal is disposed in the housing, and the housing includes an exhaust gas channel for the controlled withdrawal of hot gases and/or plasma in the event of an explosion.

Abstract: A potted electrical circuit is enclosed within a housing and has a first and second fiberglass layer that is laid upon a top surface of the potted electrical circuit. A lid of the housing seals the electrical circuit there within and an opening formed in a side wall allows circuitry wiring to extend there from out. The first fiberglass layer is a woven layer while the second fiberglass layer is a padding-like layer. Circuitry wiring pushes through the woven first fiberglass layer before extending out through the opening in the housing. The first fiberglass layer is tucked in and around the electrical circuit and adheres to the inside of the housing by attaching to the potting material while it hardens. In a preferred embodiment, the electrical circuit in combination with the insulation material is used within a transient voltage surge suppression device.

Abstract: A potted electrical circuit is enclosed within a housing and has a first and second fiberglass layer that is laid upon a top surface of the potted electrical circuit. A lid of the housing seals the electrical circuit there within and an opening formed in a side wall allows circuitry wiring to extend there from out. The first fiberglass layer is a woven layer while the second fiberglass layer is a padding-like layer. Circuitry wiring pushes through the woven first fiberglass layer before extending out through the opening in the housing. The first fiberglass layer is tucked in and around the electrical circuit and adheres to the inside of the housing by attaching to the potting material while it hardens. In a preferred embodiment, the electrical circuit in combination with the insulation material is used within a transient voltage surge suppression device.

Abstract: An airtight sealed package with a device sealed therein in an airtight manner under vacuum, the device being placed in a space defined in the airtight sealed package by a lid and a substrate, includes at least one pressure adjustment unit provided on at least one of the lid and the substrate, and configured to receive energy from an outside of the airtight sealed package, with the device sealed in the airtight manner in the airtight sealed package, to adjust pressure in the space. An energy transmission member transmits the energy to the pressure adjustment unit.

Abstract: A method and apparatus for protecting a heat sensitive component from high temperature, mechanical shock and moisture are provided. An enclosure includes an outer housing surrounding an inner cavity configured to receive a heat sensitive component therein, a cover configured to matingly engage the outer housing such that the inner cavity is sealed from an environment external to the enclosure, wherein at least one of the outer housing and the cover are formed from a ceramic material.

Abstract: The present invention connects a first wiring portion located at one side of a substrate and a second wiring portion located at the other side. A side electrode connected to the first wiring portion is formed, and the second wiring portion is formed on an insulating layer formed on the substrate. An exposed end of the second wiring portion formed when singulated into individual semiconductor package and the side electrode are wired by ink jet system using nano metal particles. Particularly, when copper is used, the wiring by the ink jet system is performed by the reduction of a metal surface oxidation film and/or removal of organic matters by atomic hydrogen.

Abstract: An energy supply unit for a measuring device for determining and/or monitoring a physical or chemical, process variable of a medium. Included is at least one voltage limiting unit and/or at least one current limiting unit in the energy supply unit, wherein the voltage limiting unit is embodied in such a manner that arising voltages remain under a value, which leads to an explosion in an explosion-endangered area, and wherein the current limiting unit is embodied in such a manner that arising currents and/or heatings associated therewith remain under a value, which leads to an explosion in an explosion-endangered area.

Abstract: A semiconductor device is disclosed. One embodiment provides a device including a carrier, an electrically insulating layer arranged over the carrier and a first semiconductor chip arranged over the electrically insulating layer, wherein the first semiconductor chip has a first contact element on a first surface and a second contact element on a second surface.

Abstract: One aspect is a circuit arrangement including a first semiconductor switching element, a second semiconductor switching element connected in series with the first semiconductor switching element and a freewheeling element connected in parallel with the second semiconductor switching element.

Abstract: A power semiconductor module for energy distribution, includes at least one power semiconductor, connection terminals for connecting the power semiconductor module, and a housing, in which protection from explosion is ensured in the module even in the event of electric arcs. Therefore, each power semiconductor and each connection terminal is disposed in the housing, and the housing includes an exhaust gas channel for the controlled withdrawal of hot gases and/or plasma in the event of an explosion.

Abstract: An apparatus is provided and includes a label layer, disposed in a user visible interface of a front bezel, in which an icon is etched, a multi-layer printed circuit board (PCB), abutting a rear surface of the label layer and being configured to form a light source housing that positionally corresponds to that of the icon, a light source assembly, including a substrate, which is fixedly recessed in a rear portion of the light source housing, and a light emitting portion, supported by the substrate, from which light is emitted toward at least the icon, and solder plating to reflect light emitted by the light source away from the preselected icon toward the preselected icon.

Abstract: A power semiconductor module of the present invention comprises: a heat sink 1; a circuit substrate 2 mounted on the heat sink 1; a conductive pattern 10 provided on the circuit substrate 2; a low dielectric constant film 11 covering the conductive pattern 10; a case 7 provided on the heat sink 1 so as to enclose the circuit substrate 2; and a soft insulator 9 filling the space within the case 7. The low dielectric constant film 11 is preferably formed of silicon rubber, polyimide, or epoxy resin.

Abstract: A semiconductor device includes: a substrate; a semiconductor element mounted on the substrate; a sealing structure for sealing the semiconductor element, the sealing structure being mounted on the substrate; and an adhesive for bonding the sealing structure and the substrate, wherein the sealing structure has a groove for storing the adhesive.

Abstract: The invention relates to a method for producing a rewiring printed circuit board with a substrate wafer having passage connections between a first and a second surface. One embodiment of the method comprises applying and patterning masking layers on the first and the second surfaces, thereby uncovering a first contact location on the first surface and a second contact location on the second surface; applying a protective layer to the second surface in order to protect the corresponding masking layer and the second contact location during subsequent method steps; applying a first conductor structure to the first surface, the first conductor structure on the first surface covering the first contact location; removing the protective layer on the second surface; and applying a second conductor structure to the second surface, the second conductor structure on the second surface covering the second contact location.

Abstract: A pressure-contact semiconductor device (100) includes thermal buffer plates (2) and main electrode blocks (3) having flanges (4), by which semiconductor substrate (1) having a pair of electrodes is sandwiched, disposed opposed to each side thereof, wherein the semiconductor substrate (1) is sealed in a gastight space by joining the flanges (4) to insulating container (5). The semiconductor device (100) is configured such that the outermost periphery of the semiconductor substrate (1) is enclosed by hollow cylindrical insulator (9) fitted on outer peripheries of the main electrode blocks (3) in the gastight space with O-rings (8) fitted between the main electrode blocks (3) and the cylindrical insulator (9), and sealed with reaction force from the O-rings (8).

Abstract: A method of forming an interconnection that includes introducing a barrier material in a via of a dielectric to a circuit device on a substrate in such a manner to deposit the barrier material on the circuit device, introducing a seed material into the via in manner that leaves the barrier material overlying the circuit device substantially exposed, substantially removing the barrier material overlying the circuit device, and introducing a conductive material into the via to form the interconnection.

Abstract: A semiconductor chip package includes an interconnection substrate, a central substrate, a peripheral substrate and a semiconductor chip sandwiched between the interconnection substrate and the central substrate. The interconnection substrate has a recessed cavity for receiving the semiconductor chip. The peripheral substrate is separated from the central substrate thereby decreasing the stresses caused by CTE mismatch of the semiconductor chip package. Furthermore, both the central substrate and the peripheral substrate are mechanically and electrically connected to the interconnection substrate such that the semiconductor chip is electrically connected to the peripheral substrate through the central substrate and the interconnection substrate.

Abstract: A system and method is disclosed for venting pressure from an integrated circuit package that is sealed with a lid. During a surface mount process for mounting a ball grid array integrated circuit package to a circuit board the application of heat (1) weakens the solder that seals a soldered lid, and (2) increases vapor pressure within the integrated circuit package. This may cause the soldered lid to move out of its soldered position. The present invention solves this problem by providing an integrated circuit with a solder mask that has a plurality of solder mask vents that form a plurality of vapor pressure vents through the solder. The vapor pressure vents prevent the occurrence of any increase in vapor pressure that would shift the soldered lid out of its soldered position. An alternate embodiment vents pressure through an epoxy layer that is used to attach a lid by epoxy.

Abstract: Packaged microelectronic devices, interconnecting units for packaged microelectronic devices, and methods and apparatuses for packaging microelectronic devices with pressure release elements. In one aspect of the invention, a packaged microelectronic device includes a microelectronic die, an interconnecting unit coupled to the die, and a protective casing over the die. The interconnecting unit can have a substrate with a first side and a second side to which the die is attached, a plurality of contact elements operatively coupled to corresponding bond-pads on the die, and a plurality of ball-pads on the first side of the substrate electrically coupled to the contact elements. The protective casing can have at least a first cover encapsulating the die on the first side of the substrate. The packaged microelectronic device can also include a pressure relief element through at least a portion of the first cover and/or the substrate.

Abstract: The invention relates to an electronic component and a panel, the electronic component having a semiconductor chip with a wiring board and a plastic package. The plastic package is made up of two layers of plastic package molding compound arranged one on top of the other. These layers are created with the aid of a printing operation under normal atmosphere.

Abstract: In one embodiment there is provided a method comprising performing a sawing operation on a wafer; and treating the wafer to at least reduce a propagation of micro-cracks formed in the wafer during the sawing. In another embodiment there is provided a semi-conductor die comprising a substrate having a central first portion, and a peripheral second portion around the central first portion; an integrated circuit formed on the central first portion; and a guard ring disposed between the first and second portions of the substrate to prevent a propagation of cracks found in that second portion to the first portion, wherein the second portion includes micro-cracks filled with a crack-healing material to arrest propagation of the micro-cracks beyond the guard ring and into the central first portion.

Abstract: A panel assembly of packaged integrated circuit devices including a conductive substrate panel having an array of device areas and a plurality of locking passageways. The locking passageways are positioned about an inactive buffer area which surrounds the periphery of the array of device areas. The panel assembly also includes a molded cap that is molded over the topside of the panel to encapsulate the array of device areas and the inactive buffer area. The molded cap includes conforming locking stem portions that extend into each of the locking passageways in a manner locking the molded cap to the substrate panel such that during singulation of the device areas, the molded cap will not separate from the substrate panel at the inactive buffer area. In another aspect of the invention, a method for producing the panel assembly having the locking passageways is described.

Abstract: A hydrogen diffusion port for use in a packaged electronic device. In one embodiment, the hydrogen window is characterized by a substantial absence of plating from the external surfaces of the cover the base. The hydrogen diffusion port is selected from the group of materials consisting of palladium and its alloys, platinum and its alloys and titanium and its alloys The cover is welded to the base, and the hydrogen diffusion port is affixed to an aperture in the cover. The port is affixed by a low temperature process that can be accomplished after the cover is attached to the base to form a housing and the housing is degassed, without compromising the electronics within the housing and that does not require a partial pressure of hydrogen (which may be reintroduced into the materials) to accomplish, such as by soldering the diffusion port into the cover aperture, or by swaging the diffusion port into the cover aperture.

Abstract: A semiconductor device includes an electrically insulating board; conductive interconnections formed on a first face of the board and on a second face opposite to the first face; a semiconductor chip fixed to the board through at least the interconnections on the first face, said semiconductor chip having a semiconductor element electrically connected to the interconnections; a conductive bump formed on the second face of the board and electrically connected to the interconnections on the second face; and a first through-hole passing through the board to ventilate at least a part of the region between the board and the semiconductor chip.

Abstract: An electronic component includes stacked electronic elements with external contacts. The external contacts are connected to contact terminal pads of an interconnect layer disposed on an isolating body. This isolating body extends over underlying side edges of a further electronic element, and its interconnect layer is connected to another interconnect layer of the stack via its external contact surfaces.

Abstract: A method for forming semiconductor device packages including one or more semiconductor dice, leads in communication with bond pads of the dice, and a protective layer, or package, over at least the active surfaces of the semiconductor dice. The protective layer covers at least the bond pads, the proximate regions of the corresponding leads, and the conductive elements between the bond pads and their corresponding leads. The leads are at least electrically exposed through the protective layer. A portion of each lead may be physically exposed through the protective layer so as to facilitate connection of each lead to external circuitry. The packages may also include protective layers over the back sides or the edges of the semiconductor dice. A stereolithographic process is used for precisely forming the protective layers of the package. A machine vision system is used in connection with stereolithographic equipment to locate individual dice, features thereof, or leads.

Abstract: A semiconductor device provided with a semiconductor chip having one surface bonded to a substrate, and the other surface bonded to a warp preventing sheet. Preferably, the warp preventing sheet has a coefficient of elasticity substantially equal to that of the substrate, or a coefficient of thermal expansion substantially equal to that of the substrate. Preferably, the base of the warp preventing sheet is made of material identical with that of the base of the substrate, and more preferably, the warp preventing sheet and the substrate are substantially equal in thickness to each other.

Abstract: A chip carrier, a semiconductor package and a fabricating method thereof are proposed, in which on one side of the chip carrier finally removed from an engaged surface of a mold in a de-molding process there is formed at least one grounding means corresponding in position to an eject pin of the mold, so as to allow a gear amount of electrical static generated on a surface of the semiconductor package during molding and de-molding to be discharged to the outside, instead of being retained on a semiconductor chip, conductive elements and conductive traces of the semiconductor package. This therefore can prevent electrical leakage and damage to the semiconductor chip from occurrence, and improve the quality and production efficiency for the semiconductor package.

Abstract: In a pressure sensor module according to the prior art, which is intended for detecting the pressure of a corrosive medium, the conventional sensor cell with a pressure sensor chip is modified in order to protect it from corrosion, which results in a large volume for a pressure-transmitting fluid. This is disadvantageous for the calibration and for a high degree of measurement precision.

Abstract: A panel assembly of packaged integrated circuit devices including conductive substrate panel having an array of device areas and a plurality of locking passageways. The locking passageways are positioned about an inactive buffer area which surrounds the periphery of the array of device areas. The locking passageways extend from a topside of the panel toward a bottom side of the panel. The panel assembly also includes a molded cap that is molded over the topside of the panel to encapsulate the array of device areas and the inactive buffer area. The molded cap includes conforming locking stem portions that extend into each of the locking passageways in a manner locking the molded cap to the substrate panel such that during singulation of the device areas, the molded cap will not separate from the substrate panel at the inactive buffer area. In another aspect of the invention, a method for producing the panel assembly having the locking passageways is described.

Abstract: Packaged microelectronic devices, interconnecting units for packaged microelectronic devices, and methods and apparatuses for packaging microelectronic devices with pressure release elements. In one aspect of the invention, a packaged microelectronic device includes a microelectronic die, an interconnecting unit coupled to the die, and a protective casing over the die. The interconnecting unit can have a substrate with a first side and a second side to which the die is attached, a plurality of contact elements operatively coupled to corresponding bond-pads on the die, and a plurality of ball-pads on the first side of the substrate electrically coupled to the contact elements. The protective casing can have at least a first cover encapsulating the die on the first side of the substrate. The packaged microelectronic device can also include a pressure relief element through at least a portion of the first cover and/or the substrate.

Abstract: A structure of a cross guard ring along the edge of a semiconductor chip is disclosed. A first guard ring, a second guard ring and a third guard ring are formed along the edge of a semiconductor chip. Each guard ring comprises several rectangle shaped vias which are positioned along the edge of the chip structure, wherein each rectangle via is separated from an adjacent rectangle via by a gap. Further, each rectangle via of the second guard ring is positioned opposite the said gap of the first guard ring and are crossed over and have some overlay with rectangle vias of the first guard ring which are separated by the said gap as shown in FIG. 2. Similarly the third guard ring is positioned with respect to the second guard ring.

Abstract: A semiconductor device includes a lead electrode connected to a lead, a case electrode having a projection part around its periphery, and a semiconductor chip having a rectification function and connected electrically between the lead electrode and the case electrode through connection members, wherein an electrically conductive plate is provided between the semiconductor chip and the lead electrode. Thereby, any of cracks is prevented from being generated in the semiconductor chip due to the mutual thermal deformation difference between the electrically conductive plate and the semiconductor chip which are electrically joined to each other through a joining member.

Abstract: A hermetically sealed protective package for a space-deployable electronic circuit includes a pressure relief valve. The pressure relief valve is closed during assembly and testing of the circuit in an earth borne environment, so as to prevent the entry of moisture and foreign matter and maintain pressure equalization between the interior volume and the exterior of the hermetically sealed package. The valve is opened when the package is placed in the ‘clean’ vacuum ambient of a spaceborne environment, so as to vent atmospheric pressure from the interior volume of the package and prevent differential pressure-induced stresses on the package.

Abstract: The present invention relates to a BGA semiconductor device using an insulating film. The BGA semiconductor device using the insulating film has purge holes (a) made between through-holes 2 in a base film 1 as a substrate, so that stagnant air is purged from voids (s) formed between the insulating film 4 set on the upper face of a wiring pattern 3 and the wiring pattern 3 via the purge holes (a) before electronic elements formed with chip bonding are packaged with a sealing resin 5.

Abstract: A packaged semiconductor device having high reliability that allows for a large number of pins and that provides good heat removal properties, and that can discharge the high pressure moisture in a gas state from the inside thereof to the exterior. The device includes a strengthening ring arranged around a semiconductor chip that includes a process type electrode and that is mounted on an isolated substrate; a resin to fill spaces between the semiconductor chip and the isolated substrate; and a cap on the semiconductor chip and the strengthening ring, wherein at least one vent is formed perpendicular to the direction of the thickness of the semiconductor chip.