Abstract: A semiconductor device includes a housing made of a thermoplastic resin and having an internal space that is opened on one side and an inner wall portion that has an inner peripheral surface defining the internal space; and a core portion engaged in the internal space of the housing. The core portion includes a substrate, a semiconductor element mounted on the substrate, a wire electrically connecting the substrate and the semiconductor element, and a mold resin sealing the substrate, the semiconductor element and the wire. The core portion has a side surface provided with a convex portion that is in contact with the inner peripheral surface of the inner wall portion. Accordingly, a semiconductor device allowing a lengthened life and improved productivity, and a method of manufacturing the semiconductor device can be provided.

Abstract: A semiconductor module includes: an insulating plate; a plurality of metal patterns formed on the insulating plate and spaced apart from each other; a power device chip solder-joined on one the metal pattern; a lead frame solder-joined on the metal pattern to which the power device chip is not solder-joined, and on the power device chip; an external main electrode provided to an outer casing, and joined by wire bonding to the lead frame above the metal pattern to which the power device chip is not joined; and a sealing resin formed by potting to seal the power device chip, the lead frame, and the metal patterns.

Abstract: A wafer level integrated circuit assembly method is conducted as follows. First, a mother device wafer with plural first posts is provided. The first posts are used for electrical connection and are made of copper according to an embodiment. Solder is sequentially formed on the first posts. The solder is preferably pre-formed on a wafer, and the locations of the solder correspond to the first posts of the mother device wafer. Consequently, the solder can be formed on or adhered to the first posts by placing the wafer having pre-formed solder onto the first posts. Plural dies having plural second posts corresponding to the first posts are placed onto the mother device wafer. Then, the solder is reflowed to bond the first and second posts, and the mother device wafer is diced.

Abstract: The present power converter includes a power conversion semiconductor device, an electrode connection conductor which electrically connects multiple electrodes having the same potential, and also has a generally flat upper surface for electrically connecting to an exterior portion, and a sealing material provided so as to cover the power conversion semiconductor device, and also to expose the generally flat upper surface of the electrode connection conductor.

Abstract: A semiconductor device including a metal frame having a penetrating opening; a semiconductor chip provided in the opening; an insulating layer provided on the upper surface of the metal frame such that the insulating layer covers the upper surface, which is the circuit-formed surface of the semiconductor chip; an interconnect layer provided only on the upper-surface side of the metal frame with intervention of the insulating material and electrically connected to a circuit of the semiconductor chip; a via conductor provided on the upper surface of said semiconductor chip to electrically connect the circuit of the semiconductor chip and the interconnect layer; and a resin layer provided on the lower surface of the metal frame.

Abstract: A semiconductor device having a structure that can reduce stress due to difference in coefficients of thermal expansion and prevent or suppress generation of cracks, and a semiconductor device manufacturing method, are provided. The semiconductor device includes a single crystal silicon substrate having a main face on which semiconductor elements are formed and a side face intersecting with the main face, and a sealing resin provided covering at least a portion of the side face. The side face covered by the sealing resin is equipped with a first face with a plane direction forming an angle of ?5° to +5° to the plane direction of the main face.

Abstract: A manufacturing method of a semiconductor element substrate including: forming a first photoresist pattern on a first surface of a metallic plate, to form a semiconductor element mounting part, a semiconductor element electrode connection terminal, a wiring, an outer frame part, and a slit; forming a second photoresist pattern on the second surface of the metallic plate; forming the slit by half etching to connect the metallic chip with a four corners of the outer frame part; forming a plurality of concaved parts on the second surface of the metallic plate; forming a resin layer by injecting a resin to the plurality of concaved parts; and etching the first surface of the metallic plate and forming the semiconductor element electrode connection terminal and the outer frame.

Abstract: An integrated circuit assembly comprises an integrated circuit die, and a routable metal layer comprising metal traces linking a plurality of wire bond pads to a plurality of external connection pads such that the metal traces are routable under the die area. An electrically nonconductive adhesive layer couples the integrated circuit die to the routable metal layer, and a plurality of wire bonds link circuitry on the integrated circuit die to the wire bond pads in the routable metal layer. An overfill material encapsulates at least the integrated circuit die and the plurality of wire bonds, and a plurality of solder balls are formed on the plurality of external connection pads.

Abstract: In one implementation, an apparatus includes a semiconductor die, a lead, a non-conductive epoxy, and a conductive epoxy. The semiconductor die includes an upper surface and a lower surface opposite the upper surface. The lead is electrically coupled to the upper surface of the semiconductor die. The non-conductive epoxy is disposed on a first portion of the lower surface of the semiconductor die. The conductive epoxy is disposed on a second portion of the lower surface of the semiconductor die. In some implementations, a conductive wire extends from the lead to the upper surface of the semiconductor die to electrically couple the lead to the upper surface of the semiconductor die.

Abstract: A semiconductor device includes a substrate, a transistor formed over the substrate, insulating layers formed over the substrate, a multilayer wiring formed in the insulating layers, a first inductor formed in the insulating layers, and a second inductor formed over the first inductor and overlapping the first inductor. The insulating layers contain a silicon, wherein at least the two insulating layers are formed between the first inductor and the second inductor, and the first inductor and the second inductor are a spiral wiring pattern.

Abstract: In a semiconductor package, a stamp is provided on at least one of at least a pair of opposed sides on an outer peripheral portion in contact with an edge of the package, which is a blank space up to now. With this configuration, the amount of stamp can be increased even in a narrow stamp area.

Abstract: An exemplary LED module includes a ceramic substrate, a heat spreader, a heat sink, an LED die, and a packaging layer. The substrate defines a hole extending therethrough from a top side to a bottom side thereof. The heat spreader is disposed in the hole with a top side thereof substantially coplanar with the top side of the substrate. An outer circumferential surface of the heat spreader contacts an inner circumferential surface of the substrate around the hole. The heat sink is attached to the top sides of the substrate and the heat spreader. The LED die is attached to a bottom side of the heat spreader, and the packaging layer encapsulates the LED die.

Abstract: Some embodiments include a device having a number of memory cells and associated circuitry for accessing the memory cells. The memory cells of the device may be formed in one or more memory cell dice. The associated circuitry of the device may also be formed in one or more dice, optionally separated from the memory cell dice.

Abstract: An LED package is provided. The LED package includes a carrier, an LED chip, a conductive structure, a first encapsulant, a lens and a heat sink. The carrier is cup shaped and comprises a bottom portion and a lateral wall. The LED chip is received in the carrier and disposed on the bottom portion. The conductive structure is electrically connected to the LED chip. The first encapsulant is received in the carrier and fixing the carrier and the conductive structure. The lens is corresponding to the LED chip. The carrier is embedded in the heat sink, and heat generated by the LED chip is transmitted to the heat sink via the bottom portion and the lateral wall of the carrier.

Abstract: The present invention provides an electronic assembly 400 and a method for its manufacture 800, 900, 1000 1200, 1400, 1500, 1600, 1700. The assembly 400 uses no solder. Components 406, or component packages 402, 802, 804, 806 with I/O leads 412 are placed 800 onto a planar substrate 808. The assembly is encapsulated 900 with electrically insulating material 908 with vias 420, 1002 formed or drilled 1000 through the substrate 808 to the components' leads 412. Then the assembly is plated 1200 and the encapsulation and drilling process 1500 repeated to build up desired layers 422, 1502, 1702. Assemblies may be mated 1800. Within the mated assemblies, items may be inserted including pins 2202a, 2202b, and 2202c, mezzanine interconnection devices 2204, heat spreaders 2402, and combination heat spreaders and heat sinks 2602. Edge card connectors 2802 may be attached to the mated assemblies.

Abstract: A package substrate has wires that electrically connect to a semiconductor chip, and surface side terminals that are solid and cylindrical and ends of which are electrically connected to the wires. The semiconductor chip is sealed by a sealing resin layer that is formed by molding a sealing resin so as to cover the semiconductor chip. A surface of the sealing resin layer is made to have a height that is the same as that of end surfaces of other ends of the surface side terminals by grinding. Thus, the surface of the sealing resin layer is a ground surface that is a rough surface and is formed by grinding. The end surfaces of the surface side terminals are exposed at the ground surface of the sealing resin layer.

Abstract: A semiconductor laser device includes a Si(100) substrate in which a recess having an opening and a bottom face surrounded by inner wall surfaces is formed, a semiconductor laser element placed on the bottom face, and a translucent sealing glass, mounted on top of the Si(100) substrate, which seals the opening. The laser light emitted from the semiconductor laser element is reflected by a metallic reflective film formed on the inner wall surface and then transmits through the sealing glass so as to be emitted externally.

Abstract: A semiconductor die having a functional circuit (e.g., a memory array) and a decode circuit suitable for use in a stacked die semiconductor component (e.g., a random access memory component) is described. The decode circuit permits individual die in a stacked die structure to automatically determine their location or position in the stack and, in response to this determination, selectively pass one or more external control signals (e.g., chip select and clock enable signals) to the decode circuit's associated functional circuit based on inter-die connection patterns. This “self-configuring” capability permits all die designated for a specified functionality (e.g., a memory module including four vertically aligned die) to be uniformly or consistently manufactured. This, in turn, can reduce the cost to manufacture stacked die components.

Abstract: The invention relates to an electronic device, having a front face 8 and a rear face 8?, fitted with at least one discrete integrated component, comprising: a) the active face 10 of the component appearing to the side of the front face 8; b) coating material 3, present at least laterally relative to the component, ensuring the so-called component is held in the device; and c) an insulating buffer layer 6, absent from the active face 10 of the component, separating the coating material 3 from this component 4.

Abstract: A method of fabricating a substrate core structure comprises: providing first and second patterned conductive layers defining openings therein on each side of a starting insulating layer; providing a first and a second supplemental insulating layers onto respective ones of a first and a second patterned conductive layer; laser drilling a set of via openings extending through at least some of the conductive layer openings of the first and second patterned conductive layers; filling the set of via openings with a conductive material to provide a set of conductive vias; and providing a first and a second supplemental patterned conductive layer onto respective ones of the first and the second supplemental insulating layers, the set of conductive vias contacting the first supplemental patterned conductive layer at one side thereof and the second supplemental patterned conductive layer at another side thereof.

Abstract: To improve manufacture of an electronic circuit, the electronic circuit is composed of modules of sub-circuits arranged on a common substrate, such as a cooling body, and that are electrically interconnected by a planar electrical contact element.

Abstract: The present application is directed to a reservoir for use with a micro-electromechanical device having a first surface area to be lubricant. The reservoir comprises a solid component with a porous structure having a second surface area. The second surface area is greater than the first surface area. The reservoir also comprises a lubricant capable of reversibly reacting with either the solid component or the first surface area of the micro-electromechanical device.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package substrate having a foldable segment, a base segment, and a stack segment; connecting a base substrate connector directly on the base segment; connecting a stack substrate connector directly on the stack segment; mounting a base integrated circuit over the base segment with the base substrate connector outside a perimeter of the base integrated circuit; and folding the package substrate with the stack segment over the base segment and the stack substrate connector directly on the base substrate connector.

Abstract: A semiconductor device mountable to a substrate is provided. The device includes a semiconductor package having at least one semiconductor die, an electrically conductive attachment region, and a packaging material in which is embedded the semiconductor die and a first portion of the electrically conductive attachment region contacting the die. A metallic shell encloses the embedded semiconductor die and the first portion of the electrically conductive attachment region.

Abstract: A semiconductor device includes a first semiconductor chip, a buffer body, and a terminal lead. The first semiconductor chip includes a first electrode and a second electrode provided on a side opposite to the first electrode. The first semiconductor chip is configured to allow a current to flow between the first electrode and the second electrode. The buffer body includes a lower metal foil, a ceramic piece, and an upper metal foil. The lower metal foil is electrically connected to the second electrode. The ceramic piece is provided on the second electrode with the lower metal foil interposed. The upper metal foil is provided on a side of the ceramic piece opposite to the lower metal foil to be electrically connected to the lower metal foil. The terminal lead has one end provided on the upper metal foil and electrically connected to the upper metal foil.

Abstract: According to one embodiment, the base plate includes first and a second faces that are opposed to each other; the second face has a contoured rear surface, and the first area is set in the center of the plate. There is a second area with via holes in the peripheral areas of the center part. Also, the thickness of the second area is less than the thickness of the first area.

Abstract: Provided are a semiconductor package and a method for fabricating the same. The semiconductor package includes a lower package comprising a lower substrate, a lower semiconductor chip mounted on the lower substrate and comprising a redistribution, and a molding layer molding the lower semiconductor chip, an upper package comprising an upper substrate and an upper semiconductor chip mounted on the upper substrate, with the upper package being stacked on the lower package. The semiconductor package further includes an electrical interconnector extending from the upper substrate into the molding layer and connected to the redistribution to electrically connect the upper and lower packages to each other, and a dummy interconnector extending from the upper substrate into the molding layer to physically couple the upper and lower packages to each other.

Abstract: A plurality of chip sealing bodies stacked on a wiring substrate with a connection terminal. The chip sealing body includes a semiconductor chip having a semiconductor integrated circuit, a pad and a conductive connecting material, and a resin sealing the semiconductor chip. The chip sealing body is shaped into a cubic form in which a portion of the conductive connecting material except an end portion located on an external device side and all surfaces of semiconductor chip is sealed by the resin and the end portion of the conductive connecting material located on the external device side is exposed from the cubic form. A conductive bonding wire connects the end portions of the conductive connecting materials and the connection terminal respectively. A resin sealing material seals the plurality of chip sealing bodies, the conductive bonding wire, and the wiring substrate.

Abstract: An apparatus for packaging MEMS and ICs can include a semiconductor substrate, one or more MEMS devices, an enclosure, and one or more bonding structures. The semiconductor substrate can be bonded to a portion of the surface region. The semiconductor substrate can include one or more integrated circuits. Also, the semiconductor substrate can have an upper surface region. The one or more MEMS devise can overlie an inner region of the upper surface region formed by the semiconductor substrate. The enclosure can house the one or more MEMS devices. The enclosure can overlie a first outer region of the upper surface region. Also, the enclosure can have an upper cover region. The one or more bonding structures can be provided within a second outer region of the supper surface region.

Abstract: A method of manufacture of an integrated circuit packaging system includes: fabricating a base package substrate; coupling a conductive column lead frame to the base package substrate by: providing a lead frame support, patterning a conductive material on the lead frame support including forming an interconnect securing structure, and coupling the conductive material to the base package substrate; forming a base package body between the base package substrate and the conductive column lead frame; and removing the lead frame support from the conductive column lead frame for exposing the interconnect securing structure from the base package body.

Abstract: An electronic device includes a support substrate 12, an electric circuit 14 provided in a sealing region set on the support substrate 12, a sealing member 16 provided on the support substrate 12 to surround the sealing region, a sealing substrate 17 bonded to the support substrate 12 with the sealing member 16 interposed therebetween, and a spacer 23 arranged between the support substrate 12 and the sealing substrate 17. The electric circuit 14 includes an electronic element 24 having an organic layer. The sealing member 16 and the spacer 23 are formed using the same material.

Abstract: A structural member for use in semiconductor packaging is disclosed. The structural member includes a plurality of packaging regions to facilitate packaging dies in, for example, a wafer format. A packaging region has a die attach region surrounded by a peripheral region. A die is attached to the die attach region. In one aspect, the die attach region has opening through the surfaces of the structural member for accommodating a die. Through-vias disposed are in the peripheral regions. The structural member reduces warpage that can occur during curing of the mold compound used in encapsulating the dies. In another aspect, the die attach region does not have an opening. In such cases, the structural member serves as an interposer between the die and a substrate.

Abstract: In order to easily inject underfill resin and perform molding with reliability, groove sections are formed on a surface of a circuit board such that the ends of the groove sections extend to semiconductor elements. Low-viscosity underfill resin applied dropwise is guided by the groove sections and flows between the circuit board and the semiconductor elements. The underfill resin hardly expands to regions outside the semiconductor elements.

Abstract: A computer or microchip comprising an outer chamber and at least one inner chamber inside the outer chamber. The outer chamber and the inner chamber being separated at least in part by an internal sipe, and at least a portion of a surface of the outer chamber forming at least a portion of a surface of the internal sipe. The internal sipe has opposing surfaces that are separate from each other and therefore can move relative to each other, and at least a portion of the opposing surfaces are in contact with each other in a unloaded condition. The outer chamber including a Faraday Cage. A computer, comprising a semiconductor wafer having a multitude of microchips. The multitude of microchips forming a plurality of independently functioning computers, each computer having independent communication capabilities.

Abstract: A method for manufacturing an integrated circuit package system includes: providing an integrated circuit; mounting a lead on the periphery of the integrated circuit; connecting the integrated circuit to the lead with an interconnect; and forming a conformable material by pressing the conformable material on the integrated circuit, the lead, and the interconnect.

Abstract: Provided is a stacked package of a semiconductor device and a method of manufacturing the same. The stacked package of a semiconductor device may include at least one first semiconductor chip, at least one second semiconductor chip, at least one interposer between the at least one first semiconductor chip and the at least one second semiconductor chip, and a third semiconductor chip on the at least one first semiconductor chip. The at least one first semiconductor chip and the at least one second semiconductor chip may be configured to perform a first function and a second function and each may include a plurality of bonding pads. The third semiconductor chip may be configured to perform a third function which is different from the first and the second functions. The package may further include external connection leads may be configured to electrically connect the third semiconductor chip to the outside.

Abstract: A method, in which the semiconductor components forming part of an electronic circuit, or at least some of them, are embedded in a base, such as a circuit board, during the manufacture of the base, when part of the base structure is, as it were, manufactured around the semiconductor components. Through-holes for the semiconductor components are made in the base, in such a way that the holes extend between the first and second surface of the base. After the making of the holes, a polymer film is spread over the second surface of the base structure, in such a way that the polymer film also covers the through-holes made for the semiconductor components from the side of the second surface of the base structure. Before the hardening, or after the partial hardening of the polymer film, the semiconductor components are placed in the holes made in the base, from the direction of the first surface of the base.

Abstract: A conductor having a projecting portion is formed which forms a terminal portion. An uncured prepreg including a reinforcing material is closely attached to the conductor and the prepreg is cured to form an insulating film including the reinforcing material. When the prepreg is closely attached, the prepreg is stretched by the projecting portion, so that a region of the prepreg, which is closely attached to the conductor, can be thinner than the other region of the prepreg. Then, by reducing the thickness of the entire insulating film, an opening can be formed in the portion having a smaller thickness. The step of reducing the thickness can be performed by etching. Further, it is preferable not to remove the reinforcing material in this step. The strength of a terminal and an electronic device can be increased by leaving the reinforcing material at the opening.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching a flip chip to the substrate; attaching a heat slug to the substrate and the flip chip; and forming a moldable underfill having a top underfill surface on the substrate, the flip chip, and the heat slug, the moldable underfill having a characteristic of being liquid at room temperature and the top underfill surface over the flip chip.

Abstract: Embodiments of the present disclosure provide a substrate having (i) a first laminate layer, (ii) a second laminate layer, and (iii) a core material that is disposed between the first laminate layer and the second laminate layer; and a die attached to the first laminate layer, the die having an interposer bonded to a surface of an active side of the die, the surface comprising (i) a dielectric material and (ii) a bond pad to route electrical signals of the die, the interposer having a via formed therein, the via being electrically coupled to the bond pad to further route the electrical signals of the die, wherein the die and the interposer are embedded in the core material of the substrate. Other embodiments may be described and/or claimed.

Abstract: A thermally enhanced electronic package comprises a chip, a substrate, an adhesive, and an encapsulation. The adhesive or the encapsulation is mixed with carbon nanocapsules. The substrate includes an insulation layer and a wiring layer formed on the substrate. The adhesive covers the chip and the substrate. The chip is electrically connected to the wiring layer. The encapsulation covers the chip and the substrate.

Abstract: An integrated circuit package comprising an enclosure including a dielectric housing, a first electrical contact, and a second electrical contact. The dielectric housing, the first electrical contact, and the second electrical contact are configured to form a contact side of the enclosure. In addition, the first and second electrical contacts are sized to be substantially alignment insensitive for electro-mechanical connection to corresponding contacts of an end-use equipment. The enclosure encapsulates an integrated circuit die which is electrically coupled to the first and second electrical contacts. The alignment insensitive first and second electrical contacts may be electro-mechanically connected to corresponding contacts of an end-use equipment (e.g., a printer). Further, the integrated circuit package may be hosted by a peripheral device (e.g., a printer cartridge).

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a mountable assembly includes: forming an integrated circuit device having a non-horizontal device side, an active device side, and a passive device side, providing a first integrated circuit die having an active side, a passive side, and an internal interconnect on the active side, applying a die attach adhesive on the passive side, attaching the passive side to the passive device side with the die attach adhesive, and applying an underfill on the passive device side and the internal interconnect, the underfill having a non-horizontal underfill side coplanar with the non-horizontal device side; and mounting on a substrate the mountable assembly.

Abstract: This invention discloses an electronic package for containing a vertical semiconductor chip that includes a laminated board having a via connector and conductive traces distributed on multiple layers of the laminated board connected to the via connector. The semiconductor chip having at least one electrode connected to the conductive traces for electrically connected to the conductive traces at a different layer on the laminated board and the via connector dissipating heat generated from the vertical semiconductor. A ball grid array (BGA) connected to the via connector functioning as contact at a bottom surface of the package for mounting on electrical terminals disposed on a printed circuit board (PCB) wherein the laminated board having a thermal expansion coefficient in substantially a same range the PCB whereby the BGA having a reliable electrical contact with the electrical terminals.

Abstract: Various embodiments of the present invention include a semiconductor device and a fabrication method therefor, the semiconductor device including a first semiconductor chip disposed on a substrate, a first sealing resin sealing the first semiconductor chip, a built-in semiconductor device disposed on the first sealing resin, and a second sealing resin sealing the first sealing resin and the built-in semiconductor device and covering a side surface of the substrate. According to an aspect of the present invention, it is possible to provide a high-quality semiconductor device and a fabrication method therefor, in which downsizing and cost reduction can be realized.

Abstract: A through silicon via reaching a pad from a second surface of a semiconductor substrate is formed. A penetration space in the through silicon via is formed of a first hole and a second hole with a diameter smaller than that of the first hole. The first hole is formed from the second surface of the semiconductor substrate to the middle of the interlayer insulating film. Further, the second hole reaching the pad from the bottom of the first hole is formed. Then, the interlayer insulating film formed on the first surface of the semiconductor substrate has a step shape reflecting a step difference between the bottom surface of the first hole and the first surface of the semiconductor substrate. More specifically, the thickness of the interlayer insulating film between the bottom surface of the first hole and the pad is smaller than that in other portions.

Abstract: A semiconductor device includes: a semiconductor chip mounted on a mounting substrate; a first resin filling a gap between the chip and the substrate; a frame-shaped stiffener surrounding the chip; a first adhesive for bonding the stiffener to the substrate; a lid for covering the stiffener and an area surrounded by the stiffener; and a second resin filling a space between the stiffener and the chip. A thermal expansion coefficient of the second resin is smaller than that of the first resin. The first resin includes an underfill part filling a gap between the chip and the substrate and a fillet part extended from the chip region.

Abstract: A power semiconductor module comprising a substrate, a circuit formed thereon and having a plurality of conductor tracks that are electrically insulated from one another and power semiconductor components arranged on the conductor tracks. The latter are connected in a circuit-conforming manner by a connection device, which has an alternating layer sequence of at least two electrically conductive layers with at least one electrically insulating layer between them. In this case, the substrate has a first sealing area, which uninterruptedly encloses the circuit. Furthermore, this sealing area is connected to an assigned second sealing area on a layer of the connection device by a connection layer. According to the invention, this power semiconductor module is produced by applying pressure to the substrate, to the power semiconductor components and to the connection device.

Abstract: Provided is a manufacturing method of a semiconductor element substrate including: a step of forming a first photoresist pattern on a first surface of a metallic plate, to form a semiconductor element mounting part, a semiconductor element electrode connection terminal, a wiring, an outer frame part, and a slit; a step of forming a second photoresist pattern on the second surface of the metallic plate; a step of forming the slit by half etching to connect the metallic chip with a four corners of the outer frame part; a step of forming a plurality of concaved parts on the second surface of the metallic plate; a step of forming a resin layer by injecting a resin to the plurality of concaved parts; and a step of etching the first surface of the metallic plate and forming the semiconductor element electrode connection terminal and the outer frame.

Abstract: A semiconductor device having an improved whisker resistance in an exterior plating film is disclosed. The semiconductor device includes a tab with a semiconductor chip fixed thereto, plural inner leads, plural outer leads formed integrally with the inner leads, a plurality of wires for coupling electrode pads of the semiconductor chip and the inner leads with each other, and a sealing body for sealing the semiconductor chip. The outer leads project from the sealing body and an exterior plating film, which is a lead-free plating film, is formed on a surface of each of the outer leads.