Abstract: Example embodiments may be directed to a printed circuit board having an insulating substrate, pads disposed on the surface of the insulating substrate, a solder resist, and a solder moving portion. Leads of a semiconductor package may be mounted on the insulating substrate. The pads to which the leads of the semiconductor package are connected may be disposed on the surface of the insulating substrate. The solder resist layer may cover the insulating substrate, but may also contain openings exposing at least a portion of the pads to which the leads of the semiconductor package are connected. During the process by which each semiconductor lead is connected to a pad, the solder moving portion on the pad may allow an adhesion solder coating each of the leads of the semiconductor package to move towards a shoulder portion of the semiconductor package leads.

Abstract: A lead frame structure comprises a side rail, a first paddle, a second paddle, a plurality of leads, and an downset anchor bar. The first paddle is connected to the side rail via at least one first tie bar, and the second paddle is connected to the side rail via at least one-second tie bar. The first paddle and the second paddle separated from each other are used to define an area to support a chip. These leads set on the side rail expends toward to the chip supporting area. One end of the downset anchor bar is connected to the side rail, and the other end of the downset anchor bar has a protrusion portion which is between the first paddle and the second paddle and is downset from the side rail.

Abstract: A stacked assembly of semiconductor packages primarily comprises a plurality of stacked semiconductor packages. Each semiconductor package includes an encapsulant, at least a chip, and a plurality of external leads of a leadframe, where the external leads are exposed and extended from a plurality of sides of the encapsulant. Each external lead of an upper semiconductor package has a U-shaped cut end when package singulation. The U-shaped cut ends are configured for locking to the soldered portion of a corresponding external lead of a lower semiconductor package where the U-shaped cut ends and the soldered portions by soldering materials. Therefore, the stacked assembly has a larger soldering area and stronger lead reliability to enhance the soldering points to against the effects of impacts, thermal shocks, and thermal cycles.

Abstract: An integrated circuit package system including: forming a die pad, wherein the die pad has a tiebar at a corner; forming a lead wherein the lead is connected to the tiebar; connecting an integrated circuit die to the die pad; and forming an encapsulation, having an edge, over the integrated circuit die with the lead extending from and beyond the edge.

Abstract: A chip package (200) includes a carrier (20), a chip (22), a second conductive means (26) and a transparent cover (28). The carrier (20) includes a base (24). The chip is mounted on the base and has an active area (222). The second conductive means electronically connects the chip with the conductive means. The first adhesive means is applied around the active area of the chip. The transparent cover is mounted to the base of the carrier. The cover is adhered with the first adhesive means so as to define a sealing space (32) for sealing the active area of the chip therein. It can be seen that the active area of the chip is sufficiently protected from pollution by the small volume of the sealing space.

Abstract: A micro device that is manufactured by semiconductor process and is electrically connected to outside for its operation. The micro device includes a circuit board, an electrode pad being provided on the circuit board, a lead substrate being provided substantially parallel to the circuit board, and a lead of conductive member being electrically connected to the electrode pad by being bent in a direction away from a surface of the lead substrate, one end of the lead being adhered to the lead substrate and the other end being a free end.

Abstract: A plurality of vertically spaced-apart microsprings are provided to increase microspring contact force, contact area, contact reliability, and contact yield. The microspring material is deposited, either as a single layer or as a composite of multiple sub layers, to have a tailored stress differential along its cross-section. A lower microspring may be made to push up against an upper microspring to provide increased contact force, or push down against a substrate to ensure release during manufacture. The microsprings may be provided with similar stress differentials or opposite stress differentials to obtain desired microspring profiles and functionality. Microsprings may also be physically connected at their distal ends for increased contact force. The microsprings may be formed of electrically conductive material or coated with electrically conductive material for probe card and similar applications.

Abstract: A semiconductor device package comprises a container including a base and sidewalls. The base is configured to support a semiconductor device chip, and a lead frame extends through at least one of the sidewalls. A portion of the lead frame within the sidewall has at least one aperture penetrating into the lead frame. The sidewall material extends into the aperture, thereby forming a strong interfacial bond that provides a low leakage, sidewall-lead-frame interface. The base has a reentrant feature that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby forming a low leakage base-sidewall interface. The top surface of the base has a groove that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby enhancing the low leakage base-sidewall interface.

Abstract: A semiconductor chip assembly includes a semiconductor chip that includes a conductive pad, a conductive trace that includes a routing line, a bumped terminal and a filler, a connection joint that electrically connects the routing line and the pad, an encapsulant and an insulative base. The routing line contacts the bumped terminal and the filler and extends laterally beyond the bumped terminal and the filler, the filler contacts the bumped terminal in a cavity that extends into the bumped terminal, and the insulative base contacts the routing line and the bumped terminal.

Abstract: An integrated circuit package-on-package stacking system is provided including, forming a leadframe interposer including: forming a leadframe; forming a molded base on the leadframe; and singulating the leadframe interposer from the leadframe.

Abstract: A multi-chip package with a single die pad is provided. The multi-chip package includes a leadframe having a die pad and a plurality of leads surrounding the die pad. Each of the leads includes an upper lead, a lower lead and an intermediate lead substantially perpendicularly connected to the upper and lower leads, wherein the upper and lower leads are substantially parallel to the die pad. The upper and lower surfaces of the die pad are attached with upper and lower chips respectively. The upper chip is electrically connected to the upper surface of one part of the upper leads by a plurality of first bonding wires and the lower chip is electrically connected to the lower surfaces of the other part of the upper leads by a plurality of second bonding wires. A sealant is used to encapsulate the chips and bonding wires to protect these elements from damage.

Abstract: Products and assemblies are provided for socketably receiving elongate interconnection elements, such as spring contact elements, extending from electronic components, such as semiconductor devices. Socket substrates are provided with capture pads for receiving ends of elongate interconnection elements extending from electronic components. Various capture pad configurations are disclosed. Connections to external devices are provided via conductive traces adjacent the surface of the socket substrate. The socket substrate may be supported by a support substrate. In a particularly preferred embodiment the capture pads are formed directly on a primary substrate such as a printed circuit board.

Abstract: A semiconductor package having improved adhesiveness between the chip paddle and the package body and having improved ground-bonding of the chip paddle. A plurality of through-holes are formed in the chip paddle for increasing the bonding strength of encapsulation material in the package body. A plurality of tabs are formed in the chip paddle may also be used alone or in conjunction with the through-holes to further increase the bonding strength of the encapsulation material in the package body. The tabs provide additional area for the bonding site to ground wires from the semiconductor chip by increasing the length of the chip paddle.

Abstract: An integrated circuit (IC) package that comprises a lead frame. The lead frame has a downset portion and leads. The downset portion has an exterior surface that is configured to face away from a mounting board, and an interior surface that is configured to face towards the mounting board. The leads are bent away from the exterior surface, and each of the leads have a first end coupled to an IC and a second end configured to pass through one of a plurality of mounting holes extending through the mounting board. The IC is coupled to the interior surface.

Abstract: An electronic device (100) with one or more semiconductor chips (102) has an inductor (101) assembled on or under the chips. The inductor includes a ferromagnetic body (111) and a wire (104) wrapped around the body to form at least a portion of a loop; the wire ends (104a) are connected to the chips. The assembly is attached to a substrate (103), which may be a leadframe. The device may be encapsulated in molding compound (140) so that the inductor can double as a heat spreader (111c), enhancing the thermal device characteristics.

Abstract: A semiconductor die package is disclosed. In one embodiment, the die package includes a semiconductor die including a first surface and a second surface, and a leadframe structure having a die attach region and a plurality of leads extending away from the die attach region. The die attach region includes one or more apertures. A molding material is around at least portions of the die attach region of the leadframe structure and the semiconductor die. The molding material is also within the one or more apertures.

Abstract: An integrated circuit package system includes providing a substrate having a first plurality of conductive traces having a first width. An integrated circuit die is attached to the substrate. A mold clamp line is identified on the substrate. A critical area around the mold clamp line is determined. A plurality of widened conductive traces having a second width in the critical area is provided. An encapsulant encapsulates the integrated circuit die.

Abstract: A package structure for a semiconductor device comprises a substrate having a main surface and a back surface, a semiconductor chip formed on the main surface of the substrate, a package covering the semiconductor chip, radiation protrude electrodes and connection protrude electrodes. The radiation protrude electrodes are formed on the back surface of the substrate in a chip area where said semiconductor chip is located. Each of the radiation protrude electrodes are formed with a first pitch so that the radiation protrude electrodes make one body joining layer when the package structure is subjected to a heat treatment. The connection protrude electrodes are formed on the back surface of the substrate in a peripheral area of the chip area. Each of the connection protrude electrodes formed with a second pitch which is larger than the first pitch so that the connection protrude electrodes stay individual when the package structure is subjected to a heat treatment.

Abstract: The present invention relates to a three-dimensional semiconductor module having at least one unit semiconductor device connected to the outer-facing side surfaces of a multi-side ground block. The unit semiconductor device has a structure in which a semiconductor package (or semiconductor chip) is mounted on a unit wiring substrate. Ground pads to be connected to the outer-facing side surfaces of the ground block are formed on the first surface of the unit wiring substrate, the semiconductor chip is mounted on the second surface opposite to the first surface, and contact terminals electrically connected to the semiconductor chip are formed on the second surface.

Abstract: The present invention is directed to an interposer for packaging a microchip device, which includes a plurality of electrical contacts on an outer side of the interposer, for electrically contacting the packaged microchip device and to be electrically connected with the microchip device. There is an aperture extending from the outer side into the interposer. The aperture may be divided into at least two openings, and at least a first of the openings may extend from the outer side through the interposer in order to allow connection to the microchip device.

Abstract: A semiconductor device includes: a substrate; a semiconductor element mounted on the substrate; a sealing structure for sealing the semiconductor element, the sealing structure being mounted on the substrate; and an adhesive for bonding the sealing structure and the substrate, wherein the sealing structure has a groove for storing the adhesive.

Abstract: An efficient chip stacking structure is described that includes a leadframe having two surfaces to each of which can be attached stacks of chips. A chip stack can be formed by placing a chip active surface on a back surface of another chip. Electrical connections between chips and leads on the leadframe are facilitated by bonding pads on chip active surfaces and by via that extend from the bonding pads through the chips to the back surfaces.

Abstract: One of the aspects of the present invention is to provide a semiconductor module, which includes at least one semiconductor device including a semiconductor element molded with a resin package having a main surface and a side surface, and a plurality of terminals extending from the side surface and being bent towards a direction away from the main surface. It also includes a box-shaped hollow casing including a base member having a plurality of through-holes and an opening opposing to the base member, for receiving the semiconductor device with the terminals of the semiconductor device inserted into the through-holes. Further, the semiconductor module includes an insulating resin member filling up a gap defined between the semiconductor device and the casing so as to cover portions of the terminals at the side surface of the resin package of the semiconductor device.

Abstract: Provided are a stack semiconductor package manufactured by multiple molding that can prevent the breakage due to stress concentration at a connecting portion between separate semiconductor packages and a method of manufacturing the same. The stacked semiconductor packages are combined together through sealing resins by molding them multiple times, resulting in uniform stress distribution across substantially the entire interface between the semiconductor packages.

Abstract: Impact resistant circuit modules are disclosed for enclosing a die having a sensor area. Preferred modules include a flexible circuit and a die coupled thereto. The flexible circuit is preferably folded over compressible material to help absorb applied forces. A gap may be provided between sides of the die and the compressible material to help prevent peeling. A metal reinforcing layer may be bonded to the back of the die. A low modulus material including a patterned gap underneath the die may be used to absorb forces. A dry film adhesive may be placed between at least part of the upper surface of the die and the flexible circuit, preferably to provide further point impact resistance and protection. High and low modulus material may be combined in ruggedizing structures. Consumer devices employing such circuit modules are also taught, as well as module construction methods.

Abstract: A metal backing tab supports the semiconductor device and has an extending portion extending from an edge. A top leg, a middle leg and a bottom leg are all coupled to the semiconductor device and each has a lead terminal portion extending beyond the boundary of said molded housing. The top leg has a first top leg section that protrudes directly away from the molded housing, a second top leg section that bends toward a direction of a face of the molded housing, and a third top leg section bending downward. The middle leg has a first middle leg section connected to the package that protrudes away from the molded housing, and a middle leg downward section that points downward. The bottom leg has a first bottom leg section that protrudes away from the molded housing face, a second bottom leg section that points away from the molded housing face, and third bottom leg section that points downward.

Abstract: A semiconductor die featuring vertical rows of bonding pad structures is disclosed. The rows of bonding pad structures are located vertically in the Y direction, or traversing the width of the semiconductor die. A vertical row of bonding pad structures is located on each side of the semiconductor die while a third vertical row of bonding pad structures is located in the center of the semiconductor die. A first set of wire bonds connect each bonding pad structure located on the sides of the semiconductor die to a conductive lead structure located on a ceramic package. A second set of wire bonds connect each bonding pad structure located in the center of the semiconductor die to a lead on chip (LOC) structure located on the semiconductor die.

Abstract: A package on package structure includes a first chip package, a second chip package and a conductive film. The first chip package has a portion of first conductive lead which is exposed to the encapsulation body of the first chip package. The conductive film is arranged between the first chip package and the second chip package to adhere to them and electrically connect the first conductive lead and the second chip package. The above-mentioned package on package structure can improve short-circuit phenomenon between leads.

Abstract: A lead frame structure is provided, which includes a die pad having a first mounting portion and a second mounting portion separated from the first mounting portion by a gap. The first and second mounting portions are formed with corresponding blocking surfaces bordering the gap, so as to allow a flow rate of an encapsulating resin flowing through the gap during a molding process to be reduced by the blocking surfaces, such that different portions of the encapsulating resin respectively flowing above, in and below the die pad can have substantially the same flow rate, thereby preventing bonding wires from being deformed to cause short circuit and avoiding formation of voids. A semiconductor package with the lead frame structure is also provided.

Abstract: Output pads on an integrated circuit (IC) chip are arranged along a first longer side and are arranged along a second longer side with input pads. The output pads are connected to respective output patterns formed on top and bottom surfaces of a base film. All the output patterns may pass over the first longer side. Alternatively, the output patterns connected to the output pads at the second longer side may pass over a shorter side. These pattern structures establish an effective pad arrangement without increasing the size of a TAB package, yet allowing reduced the chip size.

Abstract: A semiconductor chip assembly includes a semiconductor chip that includes a conductive pad, a conductive trace that includes a routing line and a filler, a connection joint that electrically connects the routing line and the pad, an encapsulant and an insulative base. The routing line contacts the filler and extends laterally beyond the filler, and the filler contacts the insulative base in an aperture that extends through the insulative base.

Abstract: Application form of and demand for an IC chip formed with a silicon wafer are expected to increase, and further reduction in cost is required. An object of the invention is to provide a structure of an IC chip and a process capable of producing at a lower cost. A feature of the invention is to use a metal film and a reactant having the metal film as a separation layer. An etching rate of the metal film or the reactant having metal is high, and a physical means in addition to a chemical means of etching the metal film or the reactant having metal can be used in the invention. Thus, the IDF chip can be manufactured more simply and easily in a short time.

Abstract: An image sensor and a method for manufacturing the same. The image sensor includes a substrate, a photosensitive chip mounted to the substrate, a plurality of wires for electrically connecting the photosensitive chip to the substrate, a frame layer mounted to the substrate to surround the photosensitive chip. And a transparent layer is fixed and encapsulated by the frame layer such that the photosensitive chip may receive optical signals passing through the transparent layer.

Abstract: A semiconductor chip assembly includes a semiconductor chip that includes a conductive pad, a conductive trace that includes a routing line, a bumped terminal and a filler, a connection joint that electrically connects the routing line and the pad, and an encapsulant. The routing line contacts the bumped terminal and the filler and extends laterally beyond the bumped terminal and the filler, and the filler contacts the bumped terminal in a cavity that extends through the bumped terminal.

Abstract: A reflection type light-emitting diode device of a kind capable of emitting rays of light to the outside after having been reflected by a reflecting surface includes a recessed casing (22) having a cavity defining the reflecting surface (15) and also having a pair of bearing grooves (17a and 17b) defined in a peripheral wall thereof, a light-emitting element (11), and first and second lead members each made up of a small width lead segment (12a or 12b) having a relatively small width and a large width lead segment (18a or 18b) having a relatively large width, with the light-emitting element (11) mounted on the small width lead segment (12a) of the first lead members. The first and second lead members are fitted to the recessed casing (22) with the small width lead segments (12a and 12b) thereof received immovably within respective bearing grooves (17a and 17b) in the recessed casing.

Abstract: Impact resistant circuit modules are disclosed for enclosing a die having a sensor area. Preferred modules include a flexible circuit and a die coupled thereto. The flexible circuit is preferably folded over compressible material to help absorb applied forces. A gap may be provided between sides of the die and the compressible material to help prevent peeling. A metal reinforcing layer may be bonded to the back of the die. A low modulus material including a patterned gap underneath the die may be used to absorb forces. A dry film adhesive may be placed between at least part of the upper surface of the die and the flexible circuit, preferably to provide further point impact resistance and protection. High and low modulus material may be combined in ruggedizing structures. Consumer devices employing such circuit modules are also taught, as well as module construction methods.

Abstract: An integrated circuit comprises a package and having adjacent connection pins on two opposite sides of the package, with every second connection pin being inwardly bent so that the connection pins are offset. The ends of the inwardly bent connection pins and the ends of the outer connection pins each lie on a straight line, where the offset connection pins are bent by different angles out of the plane of the package.

Abstract: The present invention provides a printed circuit board having an area of non-resist portion, where each non-resist portion expands gradually toward the back end of a land array in the dipping direction A. Thus the area of solder deposition also expands in the region of the land array, thereby excessive solder does not remain up to the back end of the land array, and resultantly the amount of solder buildup at the backside in the dipping direction A can be reduced. Further, the present invention makes it unnecessary to dispose a dummy land for the prevention of solder buildup at the backmost portion of the land array, and thus the space used for a dummy land can be utilized effectively.

Abstract: A wafer-level package includes a semiconductor wafer having at least one semiconductor chip circuit forming region each including a semiconductor chip circuit each provided with test chip terminals and non test chip terminals, at least one external connection terminal, at least one redistribution trace provided on the semiconductor wafer, at least one testing member, and an insulating material. A first end of the redistribution trace is connected to one of the test chip terminals and a second end of said redistribution trace is extended out to a position offset from the chip terminals. The testing member is provided in an outer region of the semiconductor chip circuit forming region, and the second end of the redistribution trace is connected to the testing member.

Abstract: A semiconductor integrated circuit package having a leadframe (108) that includes a leadframe pad (103a) disposed under a die (100) and a bonding metal area (101a) that is disposed over at least two adjacent sides of the die. The increase in the bonding metal area (101a) increases the number of interconnections between the metal area (101a) and the die (100) to reduce the electric resistance and inductance. Furthermore, the surface area of the external terminals radiating from the package's plastic body (106) is increased if not maximized so that heat can be dissipated quicker and external terminal resistances reduced. The integrated circuit is applicable for MOSFET devices and the bonding metal area (101a) is used for the source terminal (101). The bonding metal area may have a “L” shape, a “C” shape, a “J” shape, an “I” shape or any combination thereof.

Abstract: A light emitting device package and method for making the package utilizes a first leadframe having a first surface and a second leadframe having a second surface that are relatively positioned such that the second surface is at a higher level than the first surface. The light emitting device package includes a light source, e.g., a light emitting diode die, which is mounted on the first surface of the first leadframe and electrically connected to the second surface of the second leadframe.

Abstract: The present invention provides a system and method for selectively stacking and interconnecting leaded packaged integrated circuit devices with connections between the feet of leads of an upper IC element and the upper shoulder of leads of a lower IC element while traces that implement stacking-related intra-stack connections between the constituent ICs are implemented in interposers or carrier structures oriented along the leaded sides of the stack and which extend beyond the perimeter of the feet of the leads of the constituent ICs or beyond the connective pads of the interposer. This leaves open to air flow, most of the transit section of the lower lead for cooling, but provides a less complex board structure for implementation of intra-stack connections.

Abstract: Thinning and stacking are essential for circuit modules used for mobile devices of various kinds, smart cards, memory cards and the like. These demands make the manufacture of the circuit modules more complicated or less reliable due to delamination. A circuit module of a multilayer structure is provided which is formed by embedding semiconductor chips and passive components in a sheet made from a thermoplastic resin; folding a module sheet, which is formed of circuit blocks provided with wiring patterns thereon, at the boundaries of the circuit blocks so as to be stacked into layers; and thermal-bonding and integrating the module sheet by applying heat and pressure. As a result, a highly reliable circuit module can be manufactured in a simple manner.

Abstract: An integrated circuit package bond pad includes an insulating layer and an electrode located over the insulating layer. The electrode has a first surface configured to be bonded to external circuitry and a second surface opposite the first surface. A plurality of conductive members is located in the insulating layer, wherein ones of the plurality of conductive members contact the second surface of the electrode.

Abstract: In a semiconductor device (1), semiconductor elements (2) and (3) are mounted on a lead frame (5) having leads (4). The semiconductor elements (2) and (3) are connected with the leads (4) by metallic wires (6) and (7). The semiconductor device (1) also has a heat sink (8). The members (2) to (8) are sealed with a plastic package (10). The leads (4) are exposed outward. Each of the end leads (4a) to (4d) has a wide first lead portion, a narrow second lead portion, a third lead portion to be inserted into an external substrate, and a protruding gap-controlling portion (9) for keeping the gap between the semiconductor device (1) and the external substrate constant. Because the heat resistance from the leads (4) to the plastic package (10) increases, the temperature-rise property of the lead is improved so that the solderability is improved.

Abstract: A semiconductor device includes a base plate, at least one first conductive layer carried by the base plate, and a semiconductor constructing body formed on or above the base plate, and having a semiconductor substrate and a plurality of external connecting electrodes formed on the semiconductor substrate. An insulating layer is formed on the base plate around the semiconductor constructing body. A plurality of second conductive layers are formed on the insulating layer and electrically connected to the external connecting electrodes of the semiconductor constructing body. A vertical conducting portion is formed on side surfaces of the insulating film and base plate, and electrically connects the first conductive layer and at least one of the second conductive layers.

Abstract: The present invention stacks packaged integrated circuits into modules that conserve PWB or other board surface area. The invention provides techniques and structures for aggregating chip scale-packaged integrated circuits (CSPs) or leaded packages with other CSPs or with monolithic or stacked leaded packages into modules that conserve PWB or other board surface area. The present invention can be used to advantage with packages of a variety of sizes and configurations ranging from larger packaged base elements having many dozens of contacts to smaller packages such as, for example, die-sized packages such as DSBGA. In a preferred embodiment devised in accordance with the present invention, a base element CSP and a support element CSP are aggregated through a flex circuit having at least two conductive layers that are patterned to selectively connect the two CSP elements.

Abstract: A semiconductor die package. It includes (a) a semiconductor die including a first surface and a second surface, (b) a source lead structure including protruding region having a major surface, the source lead structure being coupled to the first surface, (c) a gate lead structure being coupled to the first surface, and (d) a molding material around the source lead structure and the semiconductor die. The molding material exposes the second surface of the semiconductor die and the major surface of the source lead structure.

Abstract: There is provided herein exemplary embodiments of a semiconductor device constructed in accordance with the present invention. The device comprises: a semiconductor chip having a lateral power transistor device formed therein. The chip has an upper surface and source, drain and gate contact terminals on the upper surface thereof. Each of the source, drain and gate contact terminals have a conductive ball or pillar bump thereon. A metal lead frame spans the upper surface of the chip, the metal lead frame being in electrical contact with the conductive balls or pillar bumps. A capsule encases the chip and at least a portion of the metal lead frame such that opposite ends of the metal lead frame protrudes from opposite sides of the capsule.

Abstract: An integrated circuit package is disclosed. The package comprises a plurality of leads, each lead having a first face and a second face opposite to the first face. The package also comprises a die pad having a first face and a second face opposite to the first face. The second face of the die pad is orthogonally offset from the second face of the leads so that the second face of the die pad and the second face of the leads are not coplanar. The package also comprises an integrated circuit chip substantially laterally disposed between the plurality of leads, and having a first face and a second face opposite to the first face. The first face of the integrated circuit chip is proximate to the second face of the die pad and the first face of the integrated circuit chip is coupled to the second face of the die pad. The package further comprises a plurality of wires that link the plurality of leads to the integrated circuit chip.