Abstract: An electronic device including: a semiconductor device including plural terminals input with voltages having a same potential; and a wiring board including a mounting region at which the semiconductor device is mounted, wherein the wiring board includes a board wiring line formed on the wiring board from a connection portion at which one terminal of the plural terminals is connected, via an inside of the mounting region, to a connection portion at which another terminal of the plural terminals is connected.

Abstract: A semiconductor device includes: a first insulating circuit substrate; a first semiconductor chip mounted on a top surface of the first insulating circuit substrate; a printed circuit board arranged over the first insulating circuit substrate; a first external terminal inserted to the printed circuit board and having one end bonded to the top surface of the first insulating circuit substrate; and a first pin inserted to the printed circuit board and having one end bonded to a top surface of the first semiconductor chip, wherein the first insulating circuit substrate and the printed circuit board having warps complimentary to each other.

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes conductive materials located in different levels of the apparatus, dielectric materials located in different levels of the apparatus, a first conductive contact, and a second conductive contact. One of the conductive materials is between two of the dielectric materials. One of the dielectric materials is between two of the conductive materials. The first conductive contact has a length extending through the conductive materials and the dielectric materials in a direction perpendicular to the levels of the apparatus. The first conductive contact is electrically separated from the conductive materials. The second conductive contact contacts a group of conductive materials of the conductive materials.

Abstract: Provided is a semiconductor device having excellent heat dissipation capacity and electromagnetic wave suppression effect. A semiconductor device 1 includes a semiconductor device 30; a tubular conductive shield can 20 provided to surround a side surface 30a of the semiconductor device 30; a conductive cooling member 40; and a conductive thermally conductive sheet 10 formed between the semiconductor device 30 and the cooling member 40. The conductive shield can 20 and the cooling member 40 are electrically connected through the conductive thermally conductive sheet 10 therebetween.

Abstract: A semiconductor device includes a flexible wiring substrate. The wiring substrate includes at least two mounting portions and at least one connecting portion. The mounting portions are stacked spaced apart from each other. Each connecting portion is bent to connect two mounting portions that are adjacent in a stacking direction. The semiconductor device further includes at least one semiconductor chip mounted on at least one of the at least two mounting portions and a plurality of conductive connecting members connecting the mounting portions to each other in the stacking direction.

Abstract: A high performance connector that provides heat dissipation sufficient to support operation of high power consuming QSFP-DD transceivers. The connector may be housed in a cage with a first channel to receive a transceiver. A connector port may be aligned with the first channel, and a heat transfer element comprising a compressible portion may make mechanical and thermal contact with a transceiver inside the first channel. The compressible portion may be urged to contact a transceiver by a biasing element. The heat transfer element may be thermally coupled to a heat dissipating element outside the cage. The cage may have multiple channels, and the heat transfer element may be installed in a channel between other channels, each receiving transceivers such that the heat transfer element may receive heat from multiple transceivers.

Abstract: A semiconductor package includes a base having an upper surface and a lower surface opposite to the upper surface. An antenna array structure is embedded at the upper surface of the base. An IC die is mounted on the lower surface of the base in a flip-chip manner so that a backside of the IC die is available for heat dissipation. Solder ball pads are disposed on the lower surface of the base and arranged around the IC die. The semiconductor package further includes a metal thermal interface layer having a backside metal layer that is in direct contact with the backside of the IC die, and a solder paste conformally printed on the backside metal layer.

Abstract: A bottom side interposer provides a structurally balanced chip carrier module to reduce thermal warp and increase package robustness. The bottom side interposer is attached to the bottom of a chip carrier which carries semiconductor chips on the top side of the chip carrier. The top side of the chip carrier typically includes a top side interposer between the semiconductor chips and the chip carrier. The bottom side interposer has a coefficient of thermal expansion (CTE) that is similar to the chips and top side interposer, or tailored to have a CTE intermediate to the chips and the chip carrier. Pads on the bottom side interposer may be plated or fitted with solder balls to complete the module so the module can be connected to a printed circuit board.

Abstract: A method of fabricating a semiconductor package structure is provided. The method includes applying a plurality of first adhesive portions onto a carrier; applying a second adhesive portion onto the carrier; disposing a plurality of micro pins respectively in the first adhesive portions, such that each of the micro pins has a first portion embedded in a corresponding one of the first adhesive portions and a second portion protruding from said corresponding one of the first adhesive portions; bonding a die to the second adhesive portion; forming a molding compound surrounding the micro pins and the die; and removing the carrier from the molding compound after forming the molding compound.

Abstract: An electronic device including: a semiconductor device including plural terminals input with voltages having a same potential; and a wiring board including a mounting region at which the semiconductor device is mounted, wherein the wiring board includes a board wiring line formed on the wiring board from a connection portion at which one terminal of the plural terminals is connected, via an inside of the mounting region, to a connection portion at which another terminal of the plural terminals is connected.

Abstract: A packaged power device includes a ceramic package body having a top drain pad having a first area, a top source pad having a second area smaller than the first area, and a top gate pad having a third area smaller than the second area; a power device having a bottom surface affixed to a top drain pad, a die source pad coupled to the top source pad, and a die gate pad coupled to the top gate pad; and a ceramic lid affixed to the ceramic package body to form the packaged power device.

Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor die formed over an interconnect structure, an encapsulating layer formed over the interconnect structure to cover and surround the semiconductor die, and an interposer structure formed over the encapsulating layer. The interposer structure includes an insulating base having a first surface facing the encapsulating layer, and a second surface opposite the first surface. The interposer structure includes island layers arranged on the first surface of the insulating base and corresponding to the semiconductor die. A portion of the encapsulating layer is sandwiched by at least two of the island layers. Alternatively, the interposer structure includes a passivation layer covering the second surface of the insulating base and having a recess that is extended along a peripheral edge of the insulating base.

Abstract: The present invention relates to a heat dissipation module and an assembly method thereof. The heat dissipation module includes a heat conductive plate and a buffer member. The heat conductive plate includes a cover section and a first extension section. The cover section covers a heat zone. The buffer member is provided at the heat conductive plate to interferingly match with a housing, so as to conduct heat energy produced by the heat zone to the housing. Accordingly, by configuring the buffer member between the heat conductive plate and the housing, the heat conductive plate is allowed to be reliably thermally adhered to the housing, thereby achieving enhanced heat dissipation efficiency for the heat dissipation module.

Abstract: A semiconductor device includes first, second, and third metallization layers, on top of one another, that are disposed above a substrate, wherein each of the first, second, and third metallization layer includes a respective metallization structure formed in a respective dielectric layer, wherein the second metallization layer is disposed between the first and third metallization layers; and a via tower structure that extends from the first metallization layer to the third metallization layer so as to electrically couple at least part of the respective metallization structures of the first and third metallization layers.

Abstract: The microphone and pressure sensor package comprises a carrier (1) with an opening (16), a microphone device (20) including a diaphragm (21) and a perforated back plate (22) arranged above the opening (16), an ASIC device (6), and a cover (9) forming a cavity (17) between the carrier (1) and the cover (9). The ASIC device (6) and the microphone device (20) are arranged in the cavity (17). A sensor element (7) provided for a pressure sensor is integrated in the ASIC device (6). The pressure outside the cavity (17) is transferred to the sensor element (7) through the opening (16), the diaphragm (21), and the back plate (22).

Abstract: A printed circuit board including at least one blind metal-plated hole, for receiving a pin of the printed circuit board being covered by a first layer of a protective film on which there extends a second layer of electrically insulating flexible material, the first layer and second layer are for piercing by the pins when they are engaged in the metal-plated holes, the first and second layers being for claming between a support of the pins and the printed circuit board. An electronic unit including such a device. A method of fabricating a printed circuit card for such a device.

Abstract: A packaged Integrated Circuit (IC) includes an IC and a package. The package has a bottom dielectric layer and a plurality of redistribution layers (RDLs) formed on the bottom dielectric layer. Each the RDLs includes patterned conductors, a dielectric layer, and a plurality of vias that extend between the patterned conductors to a differing RDL or to external connections. The package includes a plurality of package pads that have a first lateral separation pitch. The IC includes a plurality of IC pads that electrically connect to the plurality of package pads that have a first lateral separation pitch. The package also includes a plurality of Printed Circuit Board (PCB) pads that extend through the bottom dielectric layer and contact the plurality of patterned conductors of the first RDL. Power PCB pads and ground PCB pads of the plurality of PCB pads have a second lateral separation pitch that exceeds the first lateral separation pitch.

Abstract: A package substrate including a fine redistribution circuitry, a first redistribution circuitry disposed on the fine redistribution circuitry and a core disposed on the first redistribution circuitry opposite to the fine redistribution circuitry. The fine redistribution circuitry includes a fine conductive pattern. The first redistribution circuitry includes a first conductive pattern electrically connected to the fine conductive pattern. A thickness of the fine redistribution circuitry is less than a thickness of the first redistribution circuitry and a dimension of the fine conductive pattern is less than a dimension of the first conductive pattern. The core is electrically connected to the first conductive pattern. The Young's modulus of the core is greater than the Young's modulus of the first redistribution circuitry. A package structure is also provided.

Abstract: An electronic package comprising a first substrate; a second substrate; at least one standoff substrate positioned between the first substrate and the second substrate, wherein the at least one standoff substrate is affixed to each of the first substrate and the second substrate, wherein the at least one standoff substrate forms a clearance between the first substrate and the second substrate, and wherein the at least one standoff substrate comprises an intervening plurality of through-substrate vias passing through the entire thickness of the at least one standoff substrate, and wherein a portion of the second plurality of through-substrate vias are electrically connected to a portion of the first through-substrate vias by way of a portion of the intervening through-substrate vias; and at least three electronic components located within the clearance.

Abstract: Various applications of interconnect substrates in power management systems are described.

Abstract: A high strength hinge mechanism is described herein. In one or more implementations, a computing device includes a display portion which includes a display device, and a base portion which includes a keyboard. A hinge mechanism is attached to the display portion and the base portion to enable rotation of the display portion relative to the base portion. The hinge mechanism includes a friction element and a cylindrical shaft secured to the friction element and to a chassis of the display portion. The friction element is configured to apply friction to the shaft in a radial direction as the shaft is rotated. The rotation of the shaft enables the display portion to be rotated from a closed position to a fully-open position. The hinge mechanism also includes a frame structure to support the friction element and the shaft.

Abstract: A method for making an interposer includes forming a plurality of wire bonds bonded to one or more first surfaces of a first element. A dielectric encapsulation is formed contacting an edge surface of the wire bonds which separates adjacent wire bonds from one another. Further processing comprises removing at least portions of the first element, wherein the interposer has first and second opposite sides separated from one another by at least the encapsulation, and the interposer having first contacts and second contacts at the first and second opposite sides, respectively, for electrical connection with first and second components, respectively, the first contacts being electrically connected with the second contacts through the wire bonds.

Abstract: Various embodiments of mechanisms for forming through package vias (TPVs) with multiple conductive layers and/or recesses in a die package and a package on package (PoP) device with bonding structures utilizing the TPVs are provided. One of the multiple conductive layers acts as a protective layer of the main conductive layer of the TPVs. The protective layer is less likely to oxidize and also has a slower formation rate of intermetallic compound (IMC) when exposed to solder. The recesses in TPVs of a die package are filled by solder from the other die package and the IMC layer formed is below the surface of TPVs, which strengthen the bonding structures.

Abstract: A semiconductor device and a semiconductor device manufacturing method that may prevent positional displacement of an electronic component mounted on a lead frame. The semiconductor device includes a lead frame, and an electronic component that has a protruding or recessed structure at a bonding face that bonds to the lead frame and is bonded to the lead frame, in a state in which a portion of the lead frame is fitted together with the protruding or recessed structure.

Abstract: A semiconductor device is disclosed that may include a first semiconductor die comprising a copper pillar, a second semiconductor die comprising a copper pillar, and a conductive bump connecting the copper pillar of the first semiconductor die to the copper pillar of the second semiconductor die. The first semiconductor die may comprise a metal dam formed between the copper pillar and a bond pad on the first semiconductor die. The conductive bump may have a melting point lower than melting points of the copper pillar of the first semiconductor die and the copper pillar of the second semiconductor die. The first semiconductor die may be coupled to a substrate with a conductive wire coupled to the bond pad and to the substrate. The first semiconductor die may comprise a redistribution layer formed beneath the copper pillar on the first semiconductor die.

Abstract: An apparatus is disclosed that comprises an integrated circuit and a thermal detector array configured to detect thermal radiation from the integrated circuit. A method is disclosed that comprises providing an integrated circuit and disposing a thermal detector array so as to detect thermal radiation from the integrated circuit. Another apparatus is disclosed that comprises means for processing and means for detecting thermal radiation from the means for processing.

Abstract: A package includes a bottom substrate and a bottom die over and bonded to the bottom substrate. A metal-particle-containing compound material is overlying a top surface of the bottom die, wherein the metal-particle-containing compound material comprises metal particles. A molding material molds at least a lower part of the bottom die therein, wherein the molding material is overlying the bottom substrate.

Abstract: A packaged integrated circuit and method of forming the same. The package integrated circuit includes an integrated circuit formed on a semiconductor die affixed to a surface of a multi-layer substrate, and a switch-mode regulator formed on the semiconductor die (or another semiconductor die) affixed to the surface of the multi-layer substrate. The integrated circuit and the switch-mode regulator are integrated within a package to form the packaged integrated circuit.

Abstract: The described embodiments include an interposer with signal routes located therein. The interposer includes a set of sites arranged in a pattern, each site including a set of connection points. Each connection point in each site is coupled to a corresponding one of the signal routes. Integrated circuit chiplets may be mounted on the sites and signal connectors for mounted integrated circuit chiplets may coupled to some or all of the connection points for corresponding sites, thereby coupling the chiplets to corresponding signal routes. The chiplets may then send and receive signals via the connection points and signal routes. In some embodiments, the set of connection points in each of the sites is the same, i.e., has a same physical layout. In other embodiments, the set of connection points for each site is arranged in one of two or more physical layouts.

Abstract: A hybrid PCB system has a hybrid redistribution layer that redistributes a large pad-to-pad pitch to a smaller, finer pad-to-pad pitch and applies hybrid materials to balance the thermal-mechanical stress. The hybrid PCB system combines wafer level packaging, IC substrate and high density PCB technologies within a single hybrid PCB. The hybrid PCB system addresses the opportunity for interconnect reliability, design and assembly of a electronic components with pad pitches less than 400 microns directly to a PCB without need of an IC substrate or interposer.

Abstract: A power module includes: a ceramic substrate that includes a principal surface and a back surface, and is provided with a plurality of metal wirings on the principal surface; a semiconductor chip mounted on any metal wiring of the plurality of metal wirings; and a resin part disposed around each of the plurality of metal wirings. Further, side faces of the metal wirings each have: a first region in which a plating film is formed; a second region that is positioned above the first region and that is a non-plating region; and a third region that is positioned between the first region and the second region and in which metal particles are formed. The resin part is bonded to the metal particles, the plating film, and the principal surface of the ceramic substrate.

Abstract: The invention provides a device module including a base, a plastic part, and an external connection. The plastic part is provided on the base. The device is provided on the base and embedded in the plastic part. The device is a sensor, an electronic device, or a circuit board. The external connection includes an embedded portion and a lead-out portion. The embedded portion is connected to the device, extends along the base, and is embedded in the plastic part. The lead-out portion is contiguous with the embedded portion and led out of the plastic part.

Abstract: In one embodiment, a ball grid array (BGA) of a packaged semiconductor device and a corresponding landing pad array of a printed circuit board each have a layout defined by an interconnection array having (i) an inner sub-array of locations having connectors arranged in rows and columns separated by a specified pitch and (ii) an outer rectangular ring of locations having connectors arranged in rows and columns separated by the specified pitch. The outer rectangular ring is separated from the inner sub-array by a depopulated rectangular ring having a width of at least twice the specified pitch, wherein the depopulated rectangular ring has no connectors. The outer rectangular ring has empty locations having no connectors. Some of those empty locations define depopulated sets that divide the outer rectangular ring into a number of different contiguous sets of locations having connectors that enable pin escape for connectors of the device's BGA.

Abstract: Semiconductor packages are described which increase the density of electronic components within. The semiconductor package may incorporate interposers with cavities formed into the top and/or bottom. The cavities may then be used as locations for the electronic components. Alternatively, narrow spacer interposers may be used to space apart standard more laterally elongated interposers to form the indentations used to house the electronic components. The semiconductor package designs described herein may be used to reduce footprint, reduce profile and increase electronic component and transistor density for semiconductor products.

Abstract: A capacitor arrangement structure includes a casing, a housing, and a heat sink. The casing accommodates a capacitor. The casing includes a casing bottom. The housing includes a bottom wall. The housing has a height from the bottom wall which includes an inner surface and an outer surface opposite to the inner surface in a height direction. The casing is mounted on the inner surface so that the casing bottom opposes a mounting surface in the inner surface. The heat sink includes a heat sink top. The heat sink is provided on the outer surface of the bottom wall not to overlap the casing viewed along the height direction. The heat sink top opposes the outer surface. A distance between the casing bottom and the mounting surface in the height direction is smaller than a distance between the heat sink top and the mounting surface in the height direction.

Abstract: An electronic apparatus includes a first electronic part with a first terminal, a second electronic part with a second terminal opposite the first terminal, and a joining portion which joins the first terminal and the second terminal. The joining portion contains a pole-like compound extending in a direction in which the first terminal and the second terminal are opposite to each other. The joining portion contains the pole-like compound, so the strength of the joining portion is improved. When the first terminal and the second terminal are joined, the temperature of one of the first electronic part and the second electronic part is made higher than that of the other. A joining material is cooled and solidified in this state. By doing so, the pole-like compound is formed.

Abstract: Cooling apparatus cooling for an electrical or electronic device, comprising an at least partially hollow body containing a refrigerant and having a plurality of electrically conductive sections Each electrically conductive section has a respective coupling portion suitable to be operatively associated with a corresponding electrically conductive part of the electrical or electronic device, wherein the at least partially hollow body further comprises one or more electrically insulating sections. Each electrically insulating section is positioned between and electrically insulates from each other two adjacent electrically conductive sections.

Abstract: A method and structure for packaging a semiconductor device are provided. In an embodiment a first substrate is bonded to a second substrate, which is bonded to a third substrate. A thermal interface material is placed on the second substrate prior to application of an underfill material. A ring can be placed on the thermal interface material, and an underfill material is dispensed between the second substrate and the third substrate. By placing the thermal interface material and ring prior to the underfill material, the underfill material cannot interfere with the interface between the thermal interface material and the second substrate, and the thermal interface material and ring can act as a physical barrier to the underfill material, thereby preventing overflow.

Abstract: An integrated circuit device and a method of fabricating the same are presented. The integrated circuit device (1) includes two or more active components (30a, 30b), possibly fabricated by different semiconductor technologies, and an interposer structure (10) adapted for carrying the two or more active components such that at least one of the active components is carried on a top surface of the interposer structure. The integrated circuit device also includes at least one metal cap (40), furnished on the top surface of the interposer structure and encapsulating at least one of the active components. Some variants of the integrated circuit device of the invention are suited for operation under extreme conditions.

Abstract: A semiconductor package includes a first semiconductor package, a second semiconductor package disposed on the first semiconductor package, and a flexible wing interconnection substrate disposed between the first and second semiconductor packages.

Abstract: The invention relates to a detection system (1) for detecting a soldered joint (16, 17) of an electronic component (10), particularly an integrated circuit. The component comprises a cuboid enclosure. The detection system comprises a detection device (2) with an emitter (5) for electromagnetic radiation and a detector (6) for the electromagnetic radiation. The detection device is designed to generate electromagnetic radiation (18, 19) with the emitter and to transmit said radiation to the component. The detector is arranged and designed to detect electromagnetic radiation (18?, 19?) reflected by the component and to generate an image data set representing the reflected radiation.

Abstract: A semiconductor device includes: a substrate; a semiconductor chip mounted over the substrate and having a solder bump coupled by soldering with an electrode over the substrate; and a heating unit for locally generating heat in a corner part within the horizontal plane of the semiconductor chip when an operating temperature of the semiconductor chip is equal to or less than a prescribed temperature.

Abstract: An integrated circuit device including a semiconductor substrate, a first bonding pad structure, a second bonding pad structure, and an internal bonding wire is provided. The first bonding pad structure is disposed on a surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The second bonding pad structure is disposed on the surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The first bonding pad structure is electrically coupled to the second bonding pad structure via the internal bonding wire. The integrated circuit device having a better electrical performance is provided by eliminating internal resistance drop in power supply trails or ground trails, and improving signal integrity of the integrated circuit device.

Abstract: Embodiments of the present disclosure are directed toward a molded composite enclosure for an integrated circuit (IC) assembly. In one embodiment, an enclosure for an integrated circuit (IC) assembly may include a molded lid structure having a body portion, and a side portion that extends from the body portion and forms a cavity configured to house the IC assembly, wherein the body portion and the side portion share a contiguous interior material comprising a polymer and share a contiguous exterior material comprising a metal, the contiguous interior material having an opening formed in the body portion such that the IC assembly can be thermally coupled with the contiguous exterior material through the opening. Other embodiments may be described and/or claimed.

Abstract: Semiconductor chips are provided. The semiconductor chip includes a first data pad, a first data strobe pad and a second data pad sequentially arrayed from a command address pad in a first direction. In addition, the semiconductor chip includes a third data pad, a second data strobe pad and a fourth data pad sequentially arrayed from the command address pad in a second direction. Data are inputted and outputted through the first and fourth data pads or through the second and third data pads in a predetermined bit organization. Related semiconductor chip packages and semiconductor systems are also provided.

Abstract: The invention relates to a method for bonding stacked layers (19, 20) for making printed circuits, by electromagnetic induction. In particular, a magnetic flux is locally induced at a plurality of conducting spacers (25) provided along a peripheral area (22) of the multilayer stack (18). By this method, it is possible to induce magnetic fluxes with opposite sign in individual areas of the peripheral area, thus achieving the maximum energy efficiency during the bonding process. The invention further comprises an induction head and a bonding apparatus for performing the method.

Abstract: A sensor comprises a substrate (16) and a sensor element (20) anchored to the substrate (16), the substrate (16) and sensor element (20) being of dissimilar materials and having different coefficients of thermal expansion, the sensor element (20) and substrate (16) each having a generally planar face arranged substantially parallel to one another, the sensor further comprising a spacer (26), the spacer (26) being located so as to space at least part of the sensor element (20) from at least part of the substrate (16), wherein the spacer (26) is of considerably smaller area than the area of the smaller of face of the substrate (16) and that of the sensor element (20).

Abstract: A printed circuit board and a method for producing a printed circuit board consisting of at least two printed circuit board regions, wherein the printed circuit board regions each comprise at least one conductive layer and/or at least one conductive component, wherein printed circuit board regions to be connected to one another, in the region of in each case at least one lateral surface directly adjoining one another, are connected to one another by a mechanical coupling. At least one sub-region or connection port of the conductive layer, and/or a conductive element of the component are electrically conductively coupled to each other at the lateral surface.

Abstract: A semiconductor package includes a package substrate including a ground pad; a a conductive spacer and a first semiconductor chip disposed on the package substrate; a second semiconductor chip on the conductive spacer and the first semiconductor chip; a molding unit that covers the package substrate, the first semiconductor chip, the second semiconductor chip, and a first portion of the conductive spacer, and exposes a second portion of the conductive spacer; and an electromagnetic interference (EMI) shield that covers the molding unit.

Abstract: In one embodiment, a ball grid array (BGA) of a packaged semiconductor device and a corresponding landing pad array of a printed circuit board each have a layout defined by an interconnection array having (i) an inner sub-array of locations having connectors arranged in rows and columns separated by a specified pitch and (ii) an outer rectangular ring of locations having connectors arranged in rows and columns separated by the specified pitch. The outer rectangular ring is separated from the inner sub-array by a depopulated rectangular ring having a width of at least twice the specified pitch, wherein the depopulated rectangular ring has no connectors. The outer rectangular ring has empty locations having no connectors. Some of those empty locations define depopulated sets that divide the outer rectangular ring into a number of different contiguous sets of locations having connectors that enable pin escape for connectors of the device's BGA.