Housing Entirely Of Metal Except For Feedthrough Structure Patents (Class 257/699)
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Patent number: 6586833Abstract: Packaged power devices include an electrically conductive flange having a slot therein and an electrically conductive substrate mounted within the slot. A dielectric layer is provided on the electrically conductive substrate and a gate electrode strip line is patterned on the dielectric layer. The gate electrode strip line extends opposite the electrically conductive substrate. A vertical MOSFET is also provided. The vertical MOSFET has a source electrically coupled and mounted to a first portion of the flange located outside the slot and a gate electrode electrically coupled and mounted to a first end of the gate electrode strip line.Type: GrantFiled: November 5, 2001Date of Patent: July 1, 2003Assignee: Silicon Semiconductor CorporationInventor: Bantval Jayant Baliga
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Patent number: 6566742Abstract: An acceleration sensor is disclosed which includes a capacitance-type acceleration detection element mounted on a ceramic base plate. The element comprises a movable electrode mounted between a pair of fixed electrodes. Acceleration of the sensor in a measurement direction causes the movable electrode to move relative to the fixed electrodes and the element has opposite ends in a direction perpendicular to the measurement direction. The acceleration detection element is mounted on the base at a first one of the opposite ends. Accordingly, the mounting surface of the acceleration sensor is parallel to the direction of acceleration to be detected. Thus the acceleration sensor can be surface-mounted on a printed board, and more be easily mounted in an automobile air bag control system or the like.Type: GrantFiled: November 28, 2000Date of Patent: May 20, 2003Assignee: Hitachi, Ltd.Inventors: Masahiro Matsumoto, Seikou Suzuki, Masayuki Miki
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Patent number: 6559529Abstract: A force-fit diode for high circuit application has a cylindrical constant diameter conductive body which has a tapered top and bottom peripheral edge. An axial conductor extends from one end of the housing. The tapered top and bottom peripheral edges allow the housing to be forced into an opening in the bus, with either the housing bottom or the axial lead being the first to enter the openings.Type: GrantFiled: April 10, 2001Date of Patent: May 6, 2003Assignee: International Rectifier CorporationInventors: Aldo Torti, Mario Merlin, Emilio Mattiuzzo
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Patent number: 6555903Abstract: A package structure of a hybrid device in an optical signal transmitter comprises an assembly of a surface emitting laser (SEL), photodiodes, an IC and a passive device, and its application. The package structure further comprises a submount to reduce parasitic capacitance and increase coupling efficiency of the device to the optical fiber, and an electric connect region is formed on the submount to shorten the length of wire and improve the yield. A combination of the SEL and the pair of photodiodes can further applies on a duplexer of single optical fiber.Type: GrantFiled: December 19, 2000Date of Patent: April 29, 2003Assignee: TrueLight CorporationInventors: Yun-Sen Lin, Chang-Cherng Wu, Chao-Fang Li, Meng-Nan Ho
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Patent number: 6528867Abstract: An integrated circuit device comprising a semiconductor connection component attached to a semiconductor die with an electrically conductive adhesive material. The integrated circuit device is structured with a semiconductor connection component having a first portion horizontally offset from a second portion, the first portion of the semiconductor connection component carrying the adhesive material. The semiconductor connection component may be a lead frame element having a lead finger. The semiconductor connection component with the electrically conductive adhesive material attached to the first portion thereof is a terminal such as a bond pad on a surface of a semiconductor die. The electrically conductive adhesive material is precisely applied in a simple manner, little adhesive material is wasted, and a one-step electrical/mechanical connection to bond pads of the die is provided.Type: GrantFiled: August 10, 2000Date of Patent: March 4, 2003Assignee: Micron Technology, Inc.Inventor: Syed Sajid Ahmad
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Patent number: 6498294Abstract: The present invention relates to a package for a high-frequency device, in which the characteristic impedance can be matched while a gap between the casing and each terminal is maintained wide enough to avoid contact. In the package for a high-frequency device, each metallic terminal is hermetically fixed to a conductive casing and is electrically insulated from the conductive casing by glass. Each metallic terminal extends in parallel with a side wall of the conductive casing while it is separated from the side wall. Each metallic terminal is also flanked by a pair of conductive protruding portions that are formed on a side wall of the conductive casing and extend in the longitudinal direction of each metallic terminal. The conductive protruding portions are formed on either side of each metallic terminal and serve to match the characteristic impedance.Type: GrantFiled: April 20, 2000Date of Patent: December 24, 2002Assignee: Fujitsu Quantum Devices LimitedInventors: Ryo Kuwahara, Kouichi Iwaida
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Patent number: 6483184Abstract: A substrate for a semiconductor apparatus, a semiconductor apparatus and a method of manufacturing thereof and an electronic apparatus are provided that achieve excellent productivity and cost reduction. A semiconductor apparatus is formed from a substrate and a semiconductor device wire-bonded thereto. The substrate includes a substrate main body and pluralities of leads formed on a mounting surface of the substrate on which the semiconductor device is mounted. Conduction sections electrically connected to each of the leads define at least a part of external terminals. The leads have portions located under the semiconductor device, with the remaining portions located outside the semiconductor device depending upon the size of the semiconductor device.Type: GrantFiled: February 5, 1999Date of Patent: November 19, 2002Assignee: Seiko Epson CorporationInventor: Akihiro Murata
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Patent number: 6479889Abstract: A conductive mounting board provided in a package has a recessed portion and a projecting portion, and an insulating mounting board is disposed on the recessed portion. The insulating mounting board is disposed on the recessed portion. The insulating mounting board has an insulating board on the surface of which a wiring portion is disposed. A semiconductor laser, constituted by stacked semiconductor layers each being made from a compound semiconductor composed of a group III based nitride, is disposed on the insulating mounting board and the conductive mounting board. An n-side electrode of the semiconductor laser is in contact with the insulating mounting board and a p-side electrode thereof is in contact with the conductive mounting board. Heat generated in the semiconductor laser is radiated via the conductive mounting board, and short-circuit between the n-side electrode and the p-side electrode is prevented by the insulating mounting board.Type: GrantFiled: August 30, 1999Date of Patent: November 12, 2002Assignee: Sony CorporationInventors: Hiroshi Yoshida, Tsuyoshi Tojo, Masafumi Ozawa
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Patent number: 6472724Abstract: In an electronic device structure, a high dam is formed on a circuit board so as to enclose input/output terminals of an electronic component mounted on the circuit board. The input/output terminals are projected from a body of the electronic component and connected to a printed circuit formed on the circuit board. The body is covered with a metal case.Type: GrantFiled: April 17, 2000Date of Patent: October 29, 2002Assignee: NEC CorporationInventors: Hajime Matsuzawa, Koetsu Tamura
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Patent number: 6455929Abstract: An embedded type package of power semiconductor device comprises a semiconductor device and a cup. One side of the semiconductor device is connected to a leader and another side of the semiconductor device is connected to the cup. The cup has guiding bevel and annulus groove on bottom side thereof. The cup further has an embedding part on outer side thereof and having two slantingly planes. The cup further comprises a heatsink connected to the semiconductor device; and a cone-shaped inner wall bordered to the heatsink and having a mold lock.Type: GrantFiled: June 5, 2001Date of Patent: September 24, 2002Assignee: Actron Technology CorporationInventor: C. G. Sheen
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Patent number: 6452261Abstract: Control electrode wirings which are led out from control electrodes over a number of chips built in a flat package and insulating members which are provided in order to insulate the control electrode wirings from main electrode wirings are also given function of positioning of the respective semiconductor chips in the flat package. Further, a one-piece control electrode wiring net is housed in the common electrodes of the package and the electrodes which are led out from the control electrodes of the respective semiconductor chips are connected to the net to simplify the processing of a large number of gate signal wirings.Type: GrantFiled: September 7, 1999Date of Patent: September 17, 2002Assignee: Hitachi, Ltd.Inventors: Hironori Kodama, Masahiro Nagasu, Hirokazu Inoue, Yasuo Osone, Shigeta Ueda, Kazuji Yamada
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Patent number: 6429509Abstract: A semiconductor die and an associated low resistance interconnect located primarily on the bottom surface of such die is disclosed. This arrangement provides a flexible packaging structure permitting easy interconnect with other integrated circuits; in this manner, a number of such circuits can be stacked to create high circuit density multi-chip modules. A process for making the device is further disclosed. To preserve structural integrity of a wafer containing such die during manufacturing, a through-hole via formed as part of the interconnect is filled with an inert material during operations associated with subsequent active device formation on such die.Type: GrantFiled: May 3, 1999Date of Patent: August 6, 2002Assignee: United Microelectronics CorporationInventor: Min-Chih John Hsuan
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Vented semiconductor device package having separate substrate, strengthening ring and cap structures
Patent number: 6410981Abstract: A packaged semiconductor device having high reliability that allows for a large number of pins and that provides good heat removal properties, and that can discharge the high pressure moisture in a gas state from the inside thereof to the exterior. The device includes a strengthening ring arranged around a semiconductor chip that includes a process type electrode and that is mounted on an isolated substrate; a resin to fill spaces between the semiconductor chip and the isolated substrate; and a cap on the semiconductor chip and the strengthening ring, wherein at least one vent is formed perpendicular to the direction of the thickness of the semiconductor chip.Type: GrantFiled: October 22, 1998Date of Patent: June 25, 2002Assignee: NEC CorporationInventor: Tetsuya Tao -
Patent number: 6404048Abstract: A novel package comprising a die and metal housing arrangement is provided that improves conduction of heat away from the die during use. The housing is a heat block and is abutted against the die in a thermally conductive manner. The heat block has a large thermal mass as compared to the die and is substantially rectangular in cross section. A cavity is formed in the heat block for receiving the die. In one embodiment, the cavity is substantially rectangular in cross section and is bound on three sides by a wall and open on the fourth side. In another embodiment, the cavity is substantially rectangular and bound on all four sides by a wall. In both embodiments, the cavity is slightly larger than the perimeter of the die and the walls are arranged to be in close proximity with the die during use. A metal lid is provided for at least partially covering the die and for thermally conductively attaching to the die to even further facilitate heat transfer.Type: GrantFiled: September 3, 1998Date of Patent: June 11, 2002Assignee: Micron Technology, Inc.Inventor: Salman Akram
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Patent number: 6365961Abstract: A high-frequency input/output feedthrough comprises a lower dielectric substrate in which are formed a bottom face ground layer, side ground layers, a line conductor and cofacial ground layers (formed on both sides of the line conductor on one and the same face of the lower dielectric substrate); and an upper dielectric substrate joined to the lower dielectric substrate so that portions of the line conductor and cofacial ground layers are sandwiched between the lower and upper dielectric substrate. In order to suppress return and insertion losses of signal in millimeter wave range due to a difference in transmission mode to improve transmission characteristics, the upper dielectric substrate is made thicker than the lower dielectric substrate. The width of the portion of the line conductor which is sandwiched between the lower dielectric substrate and the upper dielectric substrate is smaller than that of another portion. The cofacial ground layers are projected toward the line conductor.Type: GrantFiled: January 18, 2000Date of Patent: April 2, 2002Assignee: Kyocera CorporationInventor: Satoru Tomie
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Publication number: 20020030266Abstract: A semiconductor device comprising a substrate including a metal portion and a resin portion and having a plurality of through holes formed in the resin portion, conductive members formed within the through holes, a semiconductor chip attached to one surface of the substrate, and a plurality of solder balls attached to the other surface of the substrate. The semiconductor chip and solder balls are electrically connected through the conductive members.Type: ApplicationFiled: September 4, 2001Publication date: March 14, 2002Applicant: Seiko Epson CorporationInventor: Akihiro Murata
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Patent number: 6331730Abstract: A push-in type semiconductor chip has a semiconductor device, a support electrode body bonded to one of the end portions of the semiconductor chip and supported by, and fixed to, a heat spreader at a support fixing portion thereof, a lead electrode body bonded to the other end portion of the semiconductor chip and an insulating/sealing member disposed at the bond portion between the semiconductor chip and the support electrode body and at the bond portion between the semiconductor chip and the lead electrode body. The support electrode body includes a first portion having an outer diameter different from that of the support fixing portion at which the support electrode body is supported and fixed by the heat spreader. By setting a predetermined relationship between the outer diameters of the first portion and the support fixing portion, deformation and breakage of the semiconductor chip during assembly can be prevented.Type: GrantFiled: April 22, 1999Date of Patent: December 18, 2001Assignee: Hitachi, Ltd.Inventors: Takeshi Terasaki, Hideo Miura, Chikara Nakajima, Makoto Kitano
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Patent number: 6310401Abstract: A metallic-ceramic substrate having a ceramic layer and metal layers on both sides of the ceramic layer is provided with a high-impedance layer at the surface of the ceramic layer. The high-impedance layer is located adjacent to the metal layers. Therefore, the electrical field intensity at the edges of the metal layers is limited and an even distribution of the electrical potential at the surface of the ceramic layer is achieved. For example, the high-impedance layer may include a thin CrNi-layer, a doped Si-layer, an a—C:H-layer or a Ti-implantation.Type: GrantFiled: June 29, 2000Date of Patent: October 30, 2001Assignee: Siemens AktiengesellschaftInventors: Michael Stoisiek, Guy Lefranc, Reinhold Bayerer, Rainer Leuschner
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Patent number: 6303974Abstract: In a housing of a semiconductor device there are provided a plurality of semiconductor chips captivated in a preformed sub-assembly and arranged to present contact areas for connection to anode and emitter electrodes of the semiconductor housing. Electrically conductive contact pin arrangements project from electrically insulated channels in the preformed sub-assembly, an inward end of each of the pin arrangements being so arranged, when urged into its channel, as to provide an electrical connection to a part of the surface of a semiconductor chip. There is a sheet of electrically conductive material, resting on a base level of an inner surface of the emitter electrode and electrically isolated therefrom by an electrically insulating insert, as a means for distributing an electrical signal and making simultaneous contact with the opposite ends of the pin arrangements.Type: GrantFiled: December 7, 1998Date of Patent: October 16, 2001Assignee: Westcode Semiconductors LimitedInventors: Robert Charles Irons, Kevin Robert Billett, Michael John Evans
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Publication number: 20010023984Abstract: A semiconductor package includes a substrate panel, a chip, an upper package encapsulant, and a lower package encapsulant. The chip is mounted to the substrate panel and below a hole in the substrate panel. A number of wires interconnect the leads on the chip with the leads on the substrate panel. The upper package encapsulant is formed on the upper side of the substrate panel by filling molten liquid plastic material into an upper mold placed on the upper side of the substrate panel. The lower package encapsulant is formed on the underside of the substrate panel by filling molten liquid plastic material into a lower mold placed on the underside of the substrate panel.Type: ApplicationFiled: June 5, 2001Publication date: September 27, 2001Applicant: ADVANCED SEMICONDUCTOR ENGINEERING INC.Inventors: Jen-Kuang Fang, Chun-Chi Lee
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Patent number: 6271584Abstract: A bearer strip having components arranged in several parallel rows with variable spacing between the rows so as to increase packing density while providing sufficient empty space for introducing free flowing plastic on the bearer strip.Type: GrantFiled: August 27, 1997Date of Patent: August 7, 2001Assignee: Siemens AktiengesellschaftInventors: Stefan Schmausser, Otto Gruber, Siegfried Fischer, Walter Juri, Bernd Barchmann, Jürgen Winterer, Martin Petz, Jürgen Steinbichler, Xaver Schlögel, Otto Voggenreiter
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Patent number: 6262362Abstract: The invention discloses a method for making two sided Multi-Chip Modules (MCMs) that will allow most commercially available integrated circuits to meet the thermal and radiation hazards of the spacecraft environment using integrated package shielding technology. The invention describes the technology and methodology to manufacture MCMs that are radiation-hardened, structurally and thermally stable using 3-dimensional techniques allowing for high density integrated circuit packaging in a radiation hardened package.Type: GrantFiled: July 2, 1998Date of Patent: July 17, 2001Assignee: Maxwell Electronic Components Group, Inc.Inventors: David R. Czjakowski, Neil Eggleston, Janet S. Patterson
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Patent number: 6249046Abstract: A semiconductor device for surface-mounting that allows of easy mounting. It comprises a semiconductor element 16, an insulating film 12, a wiring pattern 20 formed on a first surface of the insulating film 12 and connected to the semiconductor element 16, bumps 14 formed on the reverse side of the wiring pattern 20 and projecting through holes 12a formed in the insulating film 12 to the second surface of the insulating film 12, and a support plate 24 being electrically conductive and adhered so as to cover the wiring pattern 20 on the first surface of the insulating film 12 and acting as a planarity maintaining member. The support plate 24 is connected to a constant potential portion of the wiring pattern 20.Type: GrantFiled: February 18, 1999Date of Patent: June 19, 2001Assignee: Seiko Epson CorporationInventor: Nobuaki Hashimoto
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Patent number: 6242694Abstract: A package for housing a photosemiconductor including a plurality of united-inner/outer-portions type leads each of which has an inner lead portion and an outer lead portion continuously formed into one body; a conductive frame having a side wall and an opening provided on the side wall for introducing the inner lead portions of the plurality of united-inner/outer-portions type leads into an inside of the conductive frame; and a ceramic plate which has a side face for stopping up the opening of the side wall of the conductive frame. The ceramic plate has a plurality of through holes on the side face for inserting the inner lead portions of the plurality of united-inner/outer-portions type leads therethrough. The ceramic plate is joined with the conductive frame so that the side face stops up the opening of the conductive frame.Type: GrantFiled: November 18, 1998Date of Patent: June 5, 2001Assignee: Sumitomo Metal (SMI) Electronics Devices Inc.Inventor: Ichiro Muraki
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Patent number: 6229088Abstract: An electronic enclosure having a cover and a base member reduced in height by providing the necessary height on the decoupling area around and generally in the same vertical space as is occupied by the thickness of glass provided to hermetically seal the enclosure. The glass is formed inside and kept away from the decoupling area by an inner ring fixed to the base member, or by a tool which is removed after the glass has been applied to seal the enclosure.Type: GrantFiled: January 6, 1999Date of Patent: May 8, 2001Assignee: Legacy Technologies, Inc.Inventor: Jack E. Launtz
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Patent number: 6208020Abstract: A resin-molded semiconductor device includes: signal leads; a die pad with a central portion elevated above a peripheral portion thereof; support leads, each including a raised portion higher in level than the other portions; and DB paste for use in die bonding. All of these members are encapsulated within a resin encapsulant. The lower part of each of these signal leads protrudes downward out of the resin encapsulant and functions as an external electrode. Each of the support leads is provided with two bent portions to cushion the deforming force. By forming a half-blanked portion in the die pad, the central portion is elevated above the peripheral portion, thus preventing the semiconductor chip from being hampered by the support leads. Accordingly, the size of the semiconductor chip mounted can be selected from a broader range and the humidity resistance of the device can also be improved.Type: GrantFiled: November 3, 1999Date of Patent: March 27, 2001Assignee: Matsushita Electronics CorporationInventors: Masanori Minamio, Kunikazu Takemura, Yuichiro Yamada, Fumito Ito, Takahiro Matsuo
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Patent number: 6172414Abstract: An interconnected apparatus for producing a low loss, reproducible electrical interconnection between a semiconductor device and a substrate includes a rod and rod receptor. The rod, generally cylindrically shaped, is attached to the semiconductor device and includes an outer circumferential wall which comes into contact with the rod receptor during a bonding process. A lip portion is formed on one end of the rod receptor for interlocking engagement with the rod. The rod receptor is plated on the substrate and includes a generally circularly shaped body which forms a centrally disposed well for receiving the rod. A lip portion is formed on one end or mouth of the rod receptor for interlocking engagement with the rod. When the rod and corresponding receptor are aligned and brought together, the rod deforms and interlocks with its corresponding rod receptor. A thermo-compression bonding process is utilized to bond the rod to the rod receptor, thereby producing a strong interlocking bond.Type: GrantFiled: April 28, 1998Date of Patent: January 9, 2001Assignee: TRW Inc.Inventors: Dean Tran, Eric R. Anderson, Ronald L. Strijek, Edward A. Rezek
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Patent number: 6150715Abstract: A semiconductor device of the present invention comprises a semiconductor pellet, a radiation plate mounted with the semiconductor pellet, a plurality of lead terminals electrically connected with the semiconductor pellet, and a resin member for encapsulating the above items. The resin member has a first surface and a second surface, and the radiation plate has a first portion exposed to the outside from the first surface of the resin member and a second portion exposed to the outside from the second surface of the resin member.Type: GrantFiled: July 28, 1998Date of Patent: November 21, 2000Assignee: NEC CorporationInventors: Seiji Ichikawa, Takeshi Umemoto, Kazunari Sato, Kunihiko Tsubota, Yoshikazu Nishimura, Toshiaki Nishibe, Kazuhiro Tahara, Masato Suga, Toru Kitakoga, Tatsuya Miya, Keita Okahira
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Patent number: 6137169Abstract: A power module or other circuit is formed with transistor assemblies, each having one or more semiconductor slices electrically connected to one another and fixed to a supporting system. The supporting system includes a tubular element suited to allow the flood of a refrigerating and insulating fluid in the inside and which has the semiconductor slices directly welded on its external surface.Type: GrantFiled: February 19, 1998Date of Patent: October 24, 2000Inventor: Adolfo Pace
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Patent number: 6100582Abstract: A circuit substrate having an insulating layer comprising a polyimide resin on a metal foil substrate, wherein the polyimide resin is a polyimide resin obtained by the reaction of(A) aromatic diamines comprising(a) p-phenylene diamine and(b) 2,2'-bis(trifluoromethyl)-4,4'-diaminobiphenyl.(B) 3,4,3',4'-biphenyltetracarboxylic acid dianhydride.The circuit-formed substrate has a desired circuit comprising a conductive layer on the circuit substrate.The polyimide resin has a coefficient of thermal linear expansion close to that of the metal foil, and hence breakage does not occur on the resin layer, the resin layer does not separate, and warping does not occur.Type: GrantFiled: March 6, 1998Date of Patent: August 8, 2000Assignee: Nitto Denko CorporationInventors: Toshihiko Omote, Yasuhito Funada
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Patent number: 6084296Abstract: A method for providing pre-placed, pre-brazed feed throughs in the substrate of a hermetic package corresponding to the terminal leads of the encased circuit COTS components. The substrate may include directly bonded copper (DBC) regions forming circular shapes where the holes for the special connectors of the present invention will be located. These holes will correspond to the leads of the COTS component that will be mounted to it. Holes are laser or mechanically drilled into the substrate inside the circular shapes formed in the DBC. To form the feed through, a bushing, such as a blind copper rivet, is brazed in the hole, with the open end thereof oriented toward the component-side of the substrate. These open ends can accept the leads of the COTS component, like the holes of a conventional PC circuit board.Type: GrantFiled: July 9, 1998Date of Patent: July 4, 2000Assignee: Satcon Technology CorporationInventors: Gary M. Colello, Dennis E. Hartzell
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Patent number: 6078101Abstract: In a high-power microwave hybrid integrated circuit comprising package-free semiconductor devices 5 with contact pads, a dielectric substrate 1 containing holes 3 and a topological pattern on its front side and a shielding metallization 2 on its opposite side, a metallic header 4 with projections 6 adjoining the shielding metallization 2 of the dielectric substrate 1 and passing through the holes 3 thereof, said semiconductor devices 5 being mounted on the projections 6 of the header 4 such that their surfaces with the contact pads flush level with a front side of the dielectric substrate 1, a part of said contact pads being connected to the topological pattern of the metallization and a part thereof being connected to the projections 6 of the header 4, the improvements consisting in that the metallic header 4 is provided with holes 3 where its projections 6 are mounted, said projections 6 being fabricated in the form of inserts rigidly secured in said holes 3 and made of material with a thermal conductivityType: GrantFiled: April 28, 1999Date of Patent: June 20, 2000Assignee: Samsung Electronics Co., Ltd.Inventors: Eduard Volfovich Aizenberg, Vladimir Iljich Bejl, Yurij Petrovich Klyuev
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Patent number: 6075289Abstract: A thermally enhanced semiconductor package includes a sheet metal cap having flexible flanges provided with solder contacts for reliable attachment to a circuit board. The package assembly further includes a semiconductor chip with a contact-bearing front surface facing forwardly, and chip bonding contacts overlying the front face of the chip. The flange bonding contacts are coplanar with the chip bonding contacts, or can be brought into coplanar alignment by flexure of the cap. The package can be surface-mounted to a circuit board by placing the package onto pads of solder paste, and then heating the assembly to melt the solder paste in order to join the bonding contacts on the chip and on the flange to corresponding contacts on the circuit board.Type: GrantFiled: November 4, 1996Date of Patent: June 13, 2000Assignee: Tessera, Inc.Inventor: Thomas H. Distefano
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Patent number: 6060776Abstract: A rectifier diode has a base which is press-fittable into an intended opening of a rectifier arrangement, a pedestal disposed on the base integrally with the base, a semiconductor chip secured to the pedestal, a head wire secured to the chip, the base being formed to connect the diode thermally and electrically to the rectifier arrangement, and a unit for mechanically stabilizing the base and including a bulwark provided on a bottom of the base in a region of the pedestal and surrounding the pedestal, the bulwark being separated from the pedestal by a trench and being integral with the bottom of the base, a pressing region for absorbing forces oriented at right angles to a plane of the semiconductor chip and disposed on a side of the bulwark remote from the trench and between bulwark and a substantially cylindrical wall of the base disposed substantially perpendicular to the bottom of the base, the trench being located between the bulwark and the pedestal and having a radial extent that is approximately twiceType: GrantFiled: June 26, 1998Date of Patent: May 9, 2000Assignee: Robert Bosch GmbHInventors: Richard Spitz, Siegfried Schuler
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Patent number: 6057593Abstract: In a power microwave hybrid integrated circuit, a depth of recesses (2) in a metal base (1) is selected so that a face surface of chips (3) and a metal base (1) are coplanar, a dielectric board (5) has a shield ground metallization (10) on its back side at the places adjoining the metal base (1), the metal base (1) is sealingly joined and electrically connected to the shield grounding metallization (10) of the board (5), and interconnecting holes (7) of the board (5) are filled with an electrically conducting material (9), the spacing between the side surfaces of the chips (3) and the side surfaces of the recesses (2) in the base (1) being of 0.001 to 0.2 mm.Type: GrantFiled: August 2, 1999Date of Patent: May 2, 2000Assignee: Samsung Electronics Co., Ltd.Inventors: Viktor Anatolievich Iovdalsky, Jury Isaevich Moldovanov
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Patent number: 6043560Abstract: A method and apparatus for controlling the thickness of a thermal interface between a processor die and a thermal plate in a microprocessor assembly are provided. The apparatus includes a generally rectangular shaped thermal top cover having a recessed portion of predetermined depth and aperture therein. The thermal top cover fits over the processor die. A thermal interface layer fills the recessed portion of the thermal top cover covering the processor die. The depth of the recessed portion is greater than the thickness of the processor die so that the thickness of the thermal interface layer is controlled. A thermal plate is placed over the thermal top cover in contact with the thermal grease so as to form a thermal path from the processor die to the thermal plate.Type: GrantFiled: December 3, 1997Date of Patent: March 28, 2000Assignee: Intel CorporationInventors: Kevin J. Haley, Niel C. Delaplane, Ravindranath V. Mahajan, Robert Starkston, Charles A. Gealer, Joseph C. Krauskopf
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Patent number: 5990553Abstract: Polyimide layers having special properties are formed on the bottom surface of a metallic body for a metal-based semiconductor circuit substrate with a polyimide layer as an insulator. There are four lamination methods: (a) a method in which a layer of thermoplastic polyimide resin (1) and a layer of non-thermoplastic polyimide resin are laminated on the bottom surface of the metallic body one over another in this order, (b) a method in which a layer of thermoplastic polyimide resin (1), a layer of non-thermoplastic polyimide resin and a layer of thermoplastic polyimide resin (2) are laminated on the bottom surface of a metallic body one over another in this order, (c) a method in which a layer of non-thermoplastic polyimide resin is laminated on the bottom surface of a metallic body and (d) a method in which a layer of thermoplastic polyimide resin (2) is laminated on the bottom surface of a metallic body.Type: GrantFiled: April 6, 1998Date of Patent: November 23, 1999Assignee: Mitsui Chemicals, Inc.Inventors: Moritsugu Morita, Hirofumi Tanaka, Kazuhito Fujita
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Patent number: 5965937Abstract: An electrical cartridge of the present invention includes a spring that pushes an integrated circuit package into a thermal plate. The integrated circuit package and substrate are attached to a substrate such as a printed circuit board. A cover may be attached to an opposite side of the substrate. There is typically a space between the integrated circuit package and the thermal plate that is filled with a thermal grease. The spring is located between the cover and the substrate in a manner which deflects the spring and exerts a force on the substrate. The spring force pushes the substrate and the integrated circuit package into the thermal plate. The spring may be designed to always provide a sufficient force to ensure a minimum space between the integrated circuit package and the thermal plate for assemblies produced in a mass production process.Type: GrantFiled: December 15, 1997Date of Patent: October 12, 1999Assignee: Intel CorporationInventors: Chia-Pin Chiu, Gregory Turturro
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Patent number: 5880403Abstract: The invention discloses a method for making two sided Multi-Chip Modules (MCMs) that will allow most commercially available integrated circuits to meet the thermal and radiation hazards of the spacecraft environment using integrated package shielding technology. The invention describes the technology and methodology to manufacture MCMs that are radiation-hardened, structurally and thermally stable using 3-dimensional techniques allowing for high density integrated circuit packaging in a radiation hardened package.Type: GrantFiled: January 24, 1997Date of Patent: March 9, 1999Assignee: Space Electronics, Inc.Inventors: David Czajkowski, Neil Eggleston, Janet Patterson
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Patent number: 5838551Abstract: Electronic package with an electronic component mounted upon a PCB or ceramic substrate by first level interconnects and housing second level interconnects on the other side of the PCB. The component is protected by an EMI shield which is grounded to a ground plane of the PCB. Especially significant when there are a plurality of components protected by the shield and when at least one of the components is an integrated circuit component (I.C.C.). The package is thus prebuilt with the EMI shield and without a separate package required for each I.C.C., and is robust in construction for shipping. The shield and ground plane provide a Faraday cage which is especially complete when the shield extends around edges of the PCB and onto its other side. The package is ready for connection to a motherboard by use of the second level interconnects and process steps to place EMI shields individually onto mother boards are avoided.Type: GrantFiled: August 1, 1996Date of Patent: November 17, 1998Assignee: Northern Telecom LimitedInventor: Yee-Ning Chan
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Patent number: 5822190Abstract: A card type memory device comprises a semiconductor chip having a nonvolatile semiconductor memory formed with external connection terminals and a metal frame comprising bed sections and external terminal electrode sections with a step section formed between the bed section and the external terminal electrode section, the bed sections of the metal frame being electrically connected to the external terminal electrode sections of the semiconductor chip. At least one surface and outer peripheral surface of the semiconductor chip are resin sealed such that at least electrode surfaces of the external terminal electrode sections of the metal frame are exposed substantially flush with a resin-sealed body surface. By doing so, a semiconductor package is formed. The semiconductor package is buried in a recess in a card type base board such that the electrode surfaces of the external terminal electrode sections of the metal frame in the semiconductor package is buried substantially flush with an external surface.Type: GrantFiled: June 10, 1997Date of Patent: October 13, 1998Assignee: Kabushiki Kaisha ToshibaInventor: Hiroshi Iwasaki
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Patent number: 5668408Abstract: A module technology allows a PGA like package architecture to be used in microwave instruments and other high frequency systems where high isolation, low reflection, and low cost multi-chip modules are needed.Type: GrantFiled: April 12, 1996Date of Patent: September 16, 1997Assignee: Hewlett-Packard CompanyInventor: Dean B. Nicholson
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Patent number: 5635754Abstract: The radiation shielded and packaged integrated circuit semiconductor device includes a lid secured to a base to enclose the integrated circuit die within, wherein the lid and the base are each constructed from a high-Z material to prevent radiation from penetrating therethrough. Another embodiment includes a die attach slug constructed from a high-Z material disposed between the integrated circuit die and a base, in combination with a high-Z material lid to substantially block incident radiation.Type: GrantFiled: January 13, 1995Date of Patent: June 3, 1997Assignee: Space Electronics, Inc.Inventors: David J. Strobel, David R. Czajkowski
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Patent number: 5633531Abstract: A compression glass lead-in arrangement in a metal body, especially in metal housings for semiconductors, in particular integrated circuits. The lead-through arrangements hermetically seal the interior of the housing relative to the environment. A glass bead is fused into a bore in the housing and the connecting conductor of the integrated circuit is passed outwardly through the glass. Alloys of the systems Cu, Al and Mg, during a cooling phase after the fusing-in exhibit a hardening effect which provides that in conjunction with the alloys, it is possible to produce compression glass lead-in arrangements which possess a hermetic sealing integrity even after a high degree of thermal and/or mechanical loading, have a high resistance to fluctuations in temperature and good resistance to corrosion.Type: GrantFiled: June 7, 1995Date of Patent: May 27, 1997Assignees: Diehl GmbH & Co., Electrovac, Fabrikation elektrotechnischer Spezialartikel Gesellschaft M.B.H.Inventors: Wolfgang Hornig, Walter Findl
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Patent number: 5585668Abstract: This invention is for an integrated circuit package which includes two integrated circuit die connected to a common substantially planar lead frame, wherein bond pads on each die face the common lead frame.Type: GrantFiled: February 15, 1996Date of Patent: December 17, 1996Assignee: Staktek CorporationInventor: Carmen D. Burns
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Patent number: 5541448Abstract: An electronic circuit card has a metal case including top and bottom surfaces connected by first and second sidewalls and a rear wall. The case has an interior chamber and an opening at one end. A substrate is positioned in the interior chamber and a connector attached to the substrate and case so as to cover the opening. A metal spring is attached to the substrate in contact with a ground conductor on the substrate. The spring contacts the top and bottom surfaces of the case to support the substrate and to couple the case to the ground conductor. The case provides protection from electrostatic discharge and radio frequency interference and is capable of receiving substrates having different sizes or shapes or different arrangements of mounted electronic components.Type: GrantFiled: October 16, 1991Date of Patent: July 30, 1996Assignee: Texas Instruments Inc.Inventor: Alton D. Carpenter
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Patent number: 5517059Abstract: A method and apparatus for electron or laser beam welding of semiconductor subassemblies to larger terminal members, without exposing semiconductor chips in such subassemblies to detrimental welding "flash".Type: GrantFiled: April 26, 1994Date of Patent: May 14, 1996Assignee: Delco Electronics Corp.Inventors: Charles T. Eytcheson, Donald E. Lake, deceased, Patrick E. Tonies
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Patent number: 5436407Abstract: An improved metal semiconductor package is described. The semiconductor package includes a lead frame with a top side and a bottom side. A semiconductor is positioned on the top side of the lead frame. Bond wires electrically couple the lead frame to the semiconductor die. A metallic base is positioned at the bottom side of the lead frame. A metallic cap is positioned over the top side of the lead frame. The metallic cap includes a central aperture that is aligned with the semiconductor die. An external plastic seal is used to join the metallic base, lead frame, and metallic cap. The external plastic seal may be in the form of a perimeter seal or a body seal.Type: GrantFiled: June 13, 1994Date of Patent: July 25, 1995Assignee: Integrated Packaging Assembly CorporationInventors: Gerald K. Fehr, Victor Batinovich
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Patent number: 5434358Abstract: A ceramic feedthrough for a package for an electronic device provides a plurality of electrical connections through an opening in the package. A method of making the feedthrough and of packaging the electronic device includes electrically conductive paths that are formed from a metal paste applied between green sheets that are joined and cofired to form a ceramic body. Vias extend from an exterior surface of the ceramic body to the paths to complete the electrical connection from outside the package to inside the package. A density of 50 paths per inch or greater may be achieved. The ceramic body may be hermetically sealed into an opening in the package and the body may have a peripheral extension to facilitate attachment of the feedthrough to the package.Type: GrantFiled: December 13, 1993Date of Patent: July 18, 1995Assignee: E-Systems, Inc.Inventors: Timothy J. Glahn, Mark J. Montesano
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Patent number: 5267684Abstract: A reservoir for the introduction of a preform of solid brazing filler metal is formed by a recess in the outer wall of an electronic component package and opens into a package through-hole. A lead-wire and bushing are placed within the through-hole with allowance for a clearance space so as to permit liquefaction and capillary diffusion of the filler metal within the space.Type: GrantFiled: November 15, 1991Date of Patent: December 7, 1993Assignee: Egide S.A.Inventors: Marc Catheline, Jean-Noel Dody, Jean-Pierre Maquaire