For Integrated Circuit Patents (Class 257/713)
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Patent number: 11972998Abstract: A miniaturized and high-power semiconductor package device with its own heat-dissipating ability includes a thermal conductor, a redistribution layer, an electronic device, a molding layer, and a solder ball. The redistribution layer includes a first surface defining an opening, a second surface opposite to the first surface, and a circuit layer. The thermal conductor is disposed in the opening. The electronic device is disposed on the first surface of the redistribution layer above the thermal conductor. The molding layer is formed on the first surface and surrounding the electronic device. The solder balls are disposed on the second surface of the redistribution layer and can form electrical connections to the circuit layer.Type: GrantFiled: November 29, 2021Date of Patent: April 30, 2024Assignee: SHUNSIN TECHNOLOGY (ZHONG SHAN) LIMITEDInventor: Shun-Hsing Liao
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Patent number: 11974414Abstract: A circuit board cooling apparatus is disclosed having a heat spreader device to be thermally coupled with a surface of the circuit board to be cooled. Also, a conforming heat transfer device is disclosed that is thermally and physically coupled with the heat spreader device to conform to a surface contour of the heat spreader device on a first side of the heat transfer device. The cooling apparatus also includes a heat transport device physically attached and thermally coupled with a second side of the heat transfer device.Type: GrantFiled: August 23, 2019Date of Patent: April 30, 2024Assignee: Hewlett Packard Enterprise Development LPInventors: Ernesto Ferrer Medina, Harvey J. Lunsman, Tahir Cader, John Franz
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Patent number: 11973005Abstract: A method includes bonding a first package and a second package over a package component, adhering a first Thermal Interface Material (TIM) and a second TIM over the first package and the second package, respectively, dispensing an adhesive feature on the package component, and placing a heat sink over and contacting the adhesive feature. The heat sink includes a portion over the first TIM and the second TIM. The adhesive feature is then cured.Type: GrantFiled: August 3, 2021Date of Patent: April 30, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Hsun Wang, Ping-Yin Hsieh, Pu Wang, Li-Hui Cheng, Szu-Wei Lu
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Patent number: 11967548Abstract: An assembly includes a chip including an integrated circuit, a casing including an integrated circuit and having an upper portion formed on a side of the chip and lower portion formed on another side of the chip, plural through-wafer vias (TWVs) for electrically connecting the integrated circuit of the chip and the integrated circuit of the casing, a system board configured to be electrically connected to the casing, and upper and lower cards connected to the casing for electrically connecting the casing to the system board.Type: GrantFiled: December 16, 2019Date of Patent: April 23, 2024Assignee: International Business Machines CorporationInventors: Kerry Bernstein, Thomas Brunschwiler, Bruno Michel
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Patent number: 11956930Abstract: A liquid-submersible thermal management system includes a shell, a heat-generating component, a working fluid, and at least one heat-dispersing element. The shell defines an immersion chamber where the heat-generating component is located in the immersion chamber. The working fluid is positioned in the immersion chamber and at least partially surrounds the heat-generating component so the working fluid receives heat from the heat-generating component. The at least one heat-dispersing element is positioned on exterior surface of the shell to conduct heat from the shell into the heat-dispersing element.Type: GrantFiled: December 19, 2022Date of Patent: April 9, 2024Assignee: Microsoft Technology Licensing, LLCInventors: Husam Atallah Alissa, Ioannis Manousakis, Nicholas Andrew Keehn, Eric C. Peterson, Bharath Ramakrishnan, Christian L. Belady, Ricardo Gouvea Bianchini
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Patent number: 11942395Abstract: An apparatus including first and second substrates. The first and second substrates each include a base and at least one peripheral wall extending from the base. One of the at least one peripheral walls of the first or second substrates includes at least one well, and the other of the at least one peripheral walls of the first or the seconds substrate that does not include a well is mechanically anchored to the well. The apparatus includes a stack having a first and second end, and the stack is disposed on the base of the first and/or the second substrates at the first and/or second ends. The stack includes at least one element configured to generate energy. A method of assembling the apparatus by contacting the substrates.Type: GrantFiled: November 24, 2021Date of Patent: March 26, 2024Assignee: Ciena CorporationInventors: Raphael Beaupré-Laflamme, Simon Savard, Lam Nguyen
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Patent number: 11942503Abstract: An image sensor unit is disclosed that includes an array of image sensing pixels, arranged in a plurality of rows and a plurality of columns, wherein each pixel is individually addressable. Each row of pixels is controlled via a row control in communication with the row of pixels in the array via a row addressing line, and capable of selectively addressing one or more of the plurality of rows. Each column of pixels is controlled by a column control in communication with each column of pixels in the array via a column addressing line, and capable of selectively addressing one or more of the plurality of columns. A unit controller is configured to specify selective readout of one or more pixel readout signals by instructing the row and column control to address one or more specific rows and columns of the array.Type: GrantFiled: May 8, 2019Date of Patent: March 26, 2024Assignee: EASTERN BLUE TECHNOLOGIES, INC.Inventors: Jianjun Guo, Yin Qian
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Patent number: 11934048Abstract: An apparatus includes a photonic integrated circuit, which includes at least one splitter configured to split at least one input beam into multiple input beamlets and multiple phase modulators configured to phase-shift at least some of the input beamlets. The apparatus also includes an array of optical amplifiers configured to amplify the phase-shifted input beamlets and generate amplified beamlets. The apparatus further incudes a beam combiner configured to combine the amplified beamlets and generate an output beam. In addition, the apparatus includes a controller configured to control the phase modulators in order to adjust phasing of the phase-shifted input beamlets.Type: GrantFiled: January 29, 2021Date of Patent: March 19, 2024Assignee: Raytheon CompanyInventors: Stephen P. Palese, Avram Bar-Cohen
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Patent number: 11937413Abstract: A power electronics module includes at least one first substrate having on a first side one or more first semiconductor dies, the one or more first semiconductor dies and the at least one first substrate providing a higher power part of the power electronics module, at least one second substrate having on a first side one or more second semiconductor dies, the one or more second semiconductor dies and the at least one second substrate providing a lower power part of the power electronics module, and a common frame at least partially encasing the first and second substrates and being a monobloc part, the higher power part being configured for direct liquid cooling and the lower power part being configured for indirect cooling.Type: GrantFiled: February 18, 2022Date of Patent: March 19, 2024Assignee: Infineon Technologies AGInventors: Tomas Manuel Reiter, Elvis Keli
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Patent number: 11929298Abstract: A molded semiconductor package includes: a semiconductor die embedded in a mold compound; a first heat spreader partly embedded in the mold compound and thermally coupled to a first side of the semiconductor die; and a second heat spreader partly embedded in the mold compound and thermally coupled to a second side of the semiconductor die opposite the first side. The first heat spreader includes at least one heat dissipative structure protruding from a side of the first heat spreader uncovered by the mold compound and facing away from the semiconductor die. The mold compound is configured to channel a fluid over the at least one heat dissipative structure in a direction parallel to the first side of the power semiconductor die. Corresponding methods of production and electronic assemblies are also described.Type: GrantFiled: November 13, 2020Date of Patent: March 12, 2024Assignee: Infineon Technologies AGInventors: Jo Ean Joanna Chye, Edward Fuergut, Ralf Otremba
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Patent number: 11924998Abstract: The disclosed systems and structures are directed to providing a hybrid liquid-cooling system for at least one rack-mounted immersion case containing at least one electronic assembly submerged in dielectric immersion cooling liquid. The hybrid liquid cooling system comprises a closed-loop fluid distribution arrangement configured to circulate channelized fluid, an external cooling module configured to thermally condition the channelized fluid circulated by the closed-loop fluid distribution arrangement, a serpentine convection coil structured to internally convey channelized fluid to operatively cool ambient temperatures of the dielectric immersion cooling liquid, and one or more fluid cooling blocks arranged to be in direct thermal contact with one or more heat-generating electronic processing components of the at least one electronic assembly.Type: GrantFiled: March 22, 2022Date of Patent: March 5, 2024Assignee: OVHInventors: Mohamad Hnayno, Ali Chehade, Henryk Klaba
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Patent number: 11923268Abstract: Techniques and mechanisms for promoting heat conduction in a packaged device using a heat spreader that is fabricated by a build-up process. In an embodiment, 3D printing of a heat spreader successively deposit layers of a thermal conductor material, where said layers variously extend each over a respective one or more IC dies. The heat spreader forms a flat top side, wherein a bottom side of the heat spreader extends over, and conforms at least partially to, different respective heights of various IC dies. In another embodiment, fabrication of a portion of the heat spreader comprises printing pore structures that contribute to a relatively low thermal conductivity of said portion. An average orientation of the oblong pores contributes to different respective thermal conduction properties for various directions of heat flow.Type: GrantFiled: February 4, 2020Date of Patent: March 5, 2024Assignee: Intel CorporationInventors: Jesus Gerardo Reyes Schuldes, Shankar Devasenathipathy, Pramod Malatkar, Aravindha Antoniswamy, Kyle Arrington
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Patent number: 11915992Abstract: A method for forming a package structure is provided, including forming an interconnect structure over a carrier substrate and forming a semiconductor die over a first side of the interconnect structure. A removable film is formed over the semiconductor die. The method includes forming a first stacked die package structure over the first side of the interconnect structure. A top surface of the removable film is higher than a top surface of the first stacked die package structure. The method includes forming a package layer, removing a portion of the package layer to expose a portion of the removable film, removing the removable film to form a recess, forming a lid structure over the semiconductor die and the first stacked die package structure. The lid structure has a main portion and a protruding portion disposed in the recess and extending from the main portion.Type: GrantFiled: February 24, 2022Date of Patent: February 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shin-Puu Jeng, Po-Yao Lin, Feng-Cheng Hsu, Shuo-Mao Chen, Chin-Hua Wang
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Patent number: 11916045Abstract: A semiconductor device, the device including: a first substrate; a first metal layer disposed over the first substrate; a second metal layer disposed over the first metal layer; a first level including a plurality of transistors, the first level disposed over the second metal layer, where the plurality of transistors each include single crystal silicon; a third metal layer disposed over the first level; a fourth metal layer disposed over the third metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 200 nm alignment error; and a via disposed through the first level, where the via has a diameter of less than 450 nm, where the fourth metal layer provides a global power distribution, and where the device includes at least one power supply circuit.Type: GrantFiled: August 21, 2023Date of Patent: February 27, 2024Assignee: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Brian Cronquist
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Patent number: 11915991Abstract: A semiconductor device includes a substrate, a package structure, a first heat spreader, and a second heat spreader. The package structure is disposed on the substrate. The first heat spreader is disposed on the substrate. The first heat spreader surrounds the package structure. The second heat spreader is disposed on the package structure. The second heat spreader is connected to the first heat spreader. A material of the first heat spreader is different from a material of the second heat spreader.Type: GrantFiled: June 29, 2021Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shu-Shen Yeh, Po-Yao Lin, Yu-Sheng Lin, Po-Chen Lai, Shin-Puu Jeng
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Patent number: 11908810Abstract: A hybrid semiconductor device includes an interposer substrate, a semiconductor package mounted on the interposer substrate, a molding member on the package substrate covering at least a portion of the semiconductor chip and exposing an upper surface of the semiconductor chip, and a stiffener disposed on an upper surface of the interposer substrate substantially around the semiconductor package.Type: GrantFiled: September 29, 2021Date of Patent: February 20, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Heungkyu Kwon, Junso Pak, Heeseok Lee
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Patent number: 11910567Abstract: A liquid-submersible thermal management system includes a cylindrical outer shell and an inner shell positioned in an interior volume of the outer shell. The cylindrical outer shell has a longitudinal axis oriented vertically relative to a direction of gravity, and the inner shell defines an immersion chamber. The liquid-submersible thermal management system a spine positioned inside the immersion chamber and oriented at least partially in a direction of the longitudinal axis with a heat-generating component located in the immersion chamber. A working fluid is positioned in the immersion chamber and at least partially surrounding the heat-generating component. The working fluid receives heat from the heat-generating component.Type: GrantFiled: March 13, 2023Date of Patent: February 20, 2024Assignee: Microsoft Technology Licensing, LLCInventors: Husam Atallah Alissa, Ioannis Manousakis, Nicholas Andrew Keehn, Eric C. Peterson, Bharath Ramakrishnan, Christian L. Belady, Ricardo Gouvea Bianchini
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Patent number: 11901258Abstract: A semiconductor structure includes a die embedded in a molding material, the die having die connectors on a first side; a first redistribution structure at the first side of the die, the first redistribution structure being electrically coupled to the die through the die connectors; a second redistribution structure at a second side of the die opposing the first side; and a thermally conductive material in the second redistribution structure, the die being interposed between the thermally conductive material and the first redistribution structure, the thermally conductive material extending through the second redistribution structure, and the thermally conductive material being electrically isolated.Type: GrantFiled: April 12, 2021Date of Patent: February 13, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hao-Jan Pei, Wei-Yu Chen, Chia-Shen Cheng, Chih-Chiang Tsao, Cheng-Ting Chen, Chia-Lun Chang, Chih-Wei Lin, Hsiu-Jen Lin, Ching-Hua Hsieh, Chung-Shi Liu
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Patent number: 11894287Abstract: Provided are a package structure and a method of forming the same. The package structure includes a first die, a second die group, an interposer, an underfill layer, a thermal interface material (TIM), and an adhesive pattern. The first die and the second die group are disposed side by side on the interposer. The underfill layer is disposed between the first die and the second die group. The adhesive pattern at least overlay the underfill layer between the first die and the second die group. The TIM has a bottom surface being in direct contact with the first die, the second die group, and the adhesive pattern. The adhesive pattern separates the underfill layer from the TIM.Type: GrantFiled: March 10, 2023Date of Patent: February 6, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hao Chen, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu, Chih-Chien Pan
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Patent number: 11895769Abstract: A module according to the present disclosure includes a circuit board, an electronic component on one of two principal surfaces of the circuit board, a connection conductor on the principal surface of the circuit board, and sealing resin on the principal surface of the circuit board. The electronic component and the connection conductor are covered with the sealing resin. The connection conductor includes a plate-shaped conductor and terminal sections. The plate-shaped conductor is disposed upright on the principal surface of the circuit board. The terminal sections extend from the plate-shaped conductor and away from the principal surface of the circuit board and are arranged side by side. Tip portions of the terminal sections are exposed at a surface of the sealing resin.Type: GrantFiled: September 21, 2021Date of Patent: February 6, 2024Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Kazuya Okamoto, Takashi Haga, Masayoshi Takagi, Kazushige Sato
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Patent number: 11887839Abstract: An imaging unit comprising an imaging chip and a mounting substrate that has the imaging chip mounted thereon and includes a first metal layer for outputting a signal generated by the imaging chip to the outside. An imaging apparatus comprises an imaging unit that includes an imaging chip and a mounting substrate that has the imaging chip mounted thereon and includes a first metal layer for outputting a signal generated by the imaging chip to the outside.Type: GrantFiled: April 12, 2019Date of Patent: January 30, 2024Assignee: NIKON CORPORATIONInventors: Hirofumi Arima, Ryoichi Suganuma, Takuya Sato, Satoru Suzuki
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Patent number: 11881441Abstract: Stacked die semiconductor packages may include a spacer die disposed between stacked dies in the semiconductor package and the semiconductor package substrate. The spacer die translates thermally induced stresses on the solder connections between the substrate and an underlying member, such as a printed circuit board, from electrical structures communicably or conductively coupling the semiconductor package substrate to the underlying structure to mechanical structures that physically couple the semiconductor package to the underlying structure. The footprint area of the spacer die is greater than the sum of the footprint areas of the individual stacked dies in the semiconductor package and less than or equal to the footprint area of the semiconductor package substrate. The spacer die may have nay physical configuration, thickness, shape, or geometry. The spacer die may have a coefficient of thermal expansion similar to that of the lowermost semiconductor die in the die stack.Type: GrantFiled: September 29, 2017Date of Patent: January 23, 2024Assignee: Intel CorporationInventors: Sireesha Gogineni, Andrew Kim, Yong She, Karissa J. Blue
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Patent number: 11879910Abstract: An integrated circuit device testing system includes a socket configured to receive an integrated circuit device, wherein the socket comprises at least one conductive trace made of a material with a resistivity that is a function of temperature, and wherein the socket is configured such that, when the integrated circuit device is located in the socket, the at least one conductive trace extends along a surface of the integrated circuit device. The integrated circuit device testing system further includes a controller or active circuit configured to determine a temperature at the surface of the integrated circuit device based on a measured resistance of the at least one conductive trace.Type: GrantFiled: September 17, 2020Date of Patent: January 23, 2024Assignee: DELTA DESIGN, INC.Inventor: Jerry Ihor Tustaniwskyj
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Patent number: 11876059Abstract: A semiconductor device having a radiating element and a directing structure is provided. The semiconductor device includes a device package. A semiconductor die is coupled to the radiating element integrated in the device package. The directing structure is affixed to the device package by way of an adhesive. The directing structure is located over the radiating element and configured for propagation of radio frequency (RF) signals.Type: GrantFiled: May 17, 2021Date of Patent: January 16, 2024Assignee: NXP USA, INC.Inventors: Robert Joseph Wenzel, Michael B. Vincent
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Patent number: 11869760Abstract: Power electronics device assemblies, circuit board assemblies, and power electronics assemblies are disclosed. In one embodiment, a power electronics device assembly includes an S-cell including a first metal layer, a first graphite layer bonded to the first metal layer, an electrically insulating layer bonded to the first graphite layer, a second graphite layer bonded to the electrically insulating layer and a second metal layer bonded to the second graphite layer, the second metal layer comprising a surface and a recess provided within the surface. The power electronics device assembly further includes a power electronics device disposed within the recess of the surface.Type: GrantFiled: July 27, 2022Date of Patent: January 9, 2024Assignee: TOYOTA MOTOR ENGINEERING & MANUFACTURING NORTH AMERICA, INC.Inventors: Feng Zhou, Hiroshi Ukegawa
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Patent number: 11868174Abstract: Examples described herein generally relate to clock tree routing in a chip stack. In an example, a multi-chip device includes a chip stack. The chip stack includes chips. The chip stack includes a clock tree. In-chip routing of the clock tree is contained within one logical chip of the chip stack. The chip stack includes leaf nodes disposed in respective chips. Each leaf node of the leaf nodes is electrically connected to the clock tree through a respective leaf-level connection bridge. The respective leaf-level connection bridge extends in an out-of-chip direction through a plurality of the chips.Type: GrantFiled: December 18, 2020Date of Patent: January 9, 2024Assignee: XILINX, INC.Inventor: Brian C. Gaide
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Patent number: 11864323Abstract: A driver board assembly includes a printed circuit board (PCB) substrate, one or more power devices embedded within the PCB substrate, and a plurality of conductive layers arranged within the PCB substrate. The plurality of conductive layers are configured to electrically couple the one or more power devices to a current source and thermally couple the one or more power devices to one or more cooling assemblies mounted to at least one of a first surface of the PCB substrate and a second surface of the PCB substrate opposite the first surface of the PCB substrate.Type: GrantFiled: July 15, 2020Date of Patent: January 2, 2024Assignees: Toyota Motor Engineering & Manufacturing North America, Inc., Toyota Jidosha Kabushiki KaishaInventors: Feng Zhou, Shohei Nagai
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Patent number: 11855021Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a semiconductor substrate, an interconnection structure, through substrate vias, conductive pillars and dummy conductive pillars. The interconnection structure is disposed at a front side of the semiconductor substrate, and comprises a stack of dielectric layers and interconnection elements spreading in the stack of dielectric layers. The through substrate vias separately penetrate through the semiconductor substrate and the stack of dielectric layers. The conductive pillars are disposed at a front side of the interconnection structure facing away from the semiconductor substrate, and respectively in electrical connection with one of the through substrate vias. The dummy conductive pillars are disposed aside the conductive pillars at the front side of the interconnection structure.Type: GrantFiled: July 1, 2021Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Chi Lin, Chen-Hua Yu, Tsang-Jiuh Wu, Wen-Chih Chiou
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Patent number: 11846474Abstract: A cooling array for cooling of an electronic component includes the electronic component, a housing which at least partially enclosing the electronic component, a heat sink support connected to the housing in a fluid-tight manner, and a heat sink which is accommodated in the heat sink support. The heat sink is thermally coupled to the electronic component in order to disperse heat generated by the electronic component.Type: GrantFiled: May 10, 2021Date of Patent: December 19, 2023Assignee: LISA DRAEXLMAIER GMBHInventors: Erwin Lichtenberg, Christian Goestl, Christian Friedrich
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Patent number: 11848320Abstract: According to an aspect, a power module package includes a plurality of power modules including a first power module and a second power module, a plurality of heat sinks including a first heat sink coupled to the first power module and a second heat sink coupled to the second power module, and a module carrier coupled to the plurality of power modules, where the module carrier includes a first region defining a first heat-sink slot and a second region defining a second heat-sink slot. The first heat sink extends at least partially through the first heat-sink slot and the second heat sink extends at least partially through the second heat-sink slot. The power module package includes a housing coupled to the module carrier and a ring member located between the module carrier and the housing.Type: GrantFiled: August 29, 2022Date of Patent: December 19, 2023Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jerome Teysseyre, Inpil Yoo, JooYang Eom
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Patent number: 11830787Abstract: Disclosed herein are structures and assemblies that may be used for thermal management in integrated circuit (IC) packages.Type: GrantFiled: August 6, 2019Date of Patent: November 28, 2023Assignee: Intel CorporationInventors: Feras Eid, Telesphor Kamgaing, Georgios Dogiamis, Aleksandar Aleksov, Johanna M. Swan
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Patent number: 11832419Abstract: Embodiments include semiconductor packages. A semiconductor package includes dies on a package substrate, an integrated heat spreader (IHS) with a lid and sidewalls over the dies and package substrate, and a heatsink and a thermal interface material respectively on the IHS. The semiconductor package includes a vapor chamber defined by a surface of the package substrate and surfaces of the lid and sidewalls, and a wick layer in the vapor chamber. The wick layer is on the dies, package substrate, and IHS, where the vapor chamber has a vapor space defined by surfaces of the wick layer and lid of the IHS. The sidewalls are coupled to the package substrate with a sealant that hermetically seals the vapor chamber with the surfaces of the package substrate and the sidewalls and lid. The wick layer has a uniform or non-uniform thickness, and has porous materials including metals, powders, or graphite.Type: GrantFiled: December 20, 2019Date of Patent: November 28, 2023Assignee: Intel CorporationInventors: Nicholas Neal, Nicholas S. Haehn, Je-Young Chang, Kyle Arrington, Aaron McCann, Edvin Cetegen, Ravindranath V. Mahajan, Robert L. Sankman, Ken P. Hackenberg, Sergio A. Chan Arguedas
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Patent number: 11830810Abstract: A package includes a circuit that includes at least one active area and at least one secondary device area, a support configured to support the circuit, and a die attach material. The circuit being mounted on the support using the die attach material and the die attach material including at least one channel configured to allow gases generated during curing of the die attach material to be released from the die attach material.Type: GrantFiled: October 30, 2020Date of Patent: November 28, 2023Assignee: WOLFSPEED, INC.Inventors: Mitch Flowers, Erwin Cohen, Alexander Komposch, Larry Christopher Wall
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Patent number: 11823971Abstract: The disclosure relates to an electronic system including a plurality of adjacent, elementary power electronics modules and connected to one another by an electrical module connection. Each elementary module including at least one power component integrated on a printed circuit inserted between two electrically conductive heat sinks. The electrical module connection is made by heat sinks at the side and/or central connection surfaces thereof.Type: GrantFiled: November 5, 2019Date of Patent: November 21, 2023Assignee: INSTITUT POLYTECHNIQUE DE GRENOBLEInventor: Yvan Avenas
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Patent number: 11817436Abstract: An apparatus for a common cooling solution for multiple packages of a common height, including: a first die package; a second die package having a same height as the first die package; and a cooling element thermally coupled to the first die package and the second die package by a planar surface of the cooling element.Type: GrantFiled: June 28, 2021Date of Patent: November 14, 2023Inventor: Christopher M. Jaggers
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Patent number: 11810876Abstract: An electronic assembly has a host wafer having a first circuit including passive devices for the purpose of one of tuning or matching networks. Chiplets are placed in the cavities. At least one chiplet has a second circuit including at least one transistor or switch device and passive tuning circuits including at least one of a stabilization network, a gain boosting network, a power delivery network, or a low-noise network. Electrical interconnects between the chiplets and wafer electrically connect the first circuitry to the second circuitry.Type: GrantFiled: March 10, 2023Date of Patent: November 7, 2023Assignee: PseudolithIC, Inc.Inventors: James Buckwalter, Michael Hodge, Justin Kim, Florian Herrault, Daniel Green
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Patent number: 11807381Abstract: A hybrid propulsion system for use with an aircraft includes a gas turbine engine, at least one propulsor, and an electric power system. The electric power system is coupled to the gas turbine engine to generate electrical energy and the propulsor to provide electrical energy to drive the propulsor. The electric power system includes a thermal management system configured to cool a heat load generated by the electric power system.Type: GrantFiled: March 16, 2021Date of Patent: November 7, 2023Assignee: Rolls-Royce CorporationInventors: Krishnamoorthi Sivalingam, Chandana J. Gajanayake, Jeyaraman Kumaravel, Palanisamy Mohan Kumar, Govind Pandey, Yunzhe Zhai, Divya Bharathi Perumal
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Patent number: 11805621Abstract: A memory auxiliary heat transfer structure is correspondingly assembled with at least one memory unit and a water-cooling assembly. The memory auxiliary heat transfer structure includes a main body. The main body has a first end, a second end and a middle section. The middle section has a heated side and a contact side. The heated side is disposed corresponding to at least one chip disposed on the memory unit. The contact side is attached to and assembled with the water-cooling assembly. The memory auxiliary heat transfer structure serves to reduce the friction between the memory unit and the water-cooling assembly and fill the gap so as to reduce the heat resistance.Type: GrantFiled: February 7, 2020Date of Patent: October 31, 2023Assignee: ASIA VITAL COMPONENTS (CHINA) CO., LTD.Inventor: Sung-Wei Lee
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Patent number: 11800632Abstract: According to various embodiments, an electronic device may include a first plate, a second plate facing away from the first plate, and a side member surrounding a space between the first plate and the second plate, a middle plate disposed in the space between the first plate and the second plate in parallel with the second plate, a first Printed Circuit Board (PCB) disposed in a space between the second plate and the middle plate, a first electronic component mounted on the first PCB between the first PCB and the middle plate, a first heat transfer structure disposed between the first electronic component and the middle plate, a second electronic component including a first surface disposed in the space and spaced apart from the first PCB, a second surface facing away from the first surface, and a side face substantially perpendicular to the first surface or the second surface, and a second heat transfer structure.Type: GrantFiled: July 24, 2019Date of Patent: October 24, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yonghwa Kim, Min Park, Dongil Son, Hyunwoo Sim, Jaedeok Lim, Chunghyo Jung, Seungbum Choi
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Patent number: 11791234Abstract: A semiconductor device includes a substrate that has a first surface and a second surface on which a plurality of solder balls are provided, a semiconductor memory on the first surface of the substrate, a controller arranged on the first surface of the substrate, separated from the semiconductor memory along a first direction, and configured to control the semiconductor memory, a graphite sheet extending along the first direction above the controller and the semiconductor memory, and a first sealing material that seals the semiconductor memory, the controller, and the graphite sheet.Type: GrantFiled: March 3, 2021Date of Patent: October 17, 2023Assignee: Kioxia CorporationInventors: Ryo Kamoda, Hideki Takahashi
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Patent number: 11785764Abstract: A method of forming a microelectronic device comprises forming a first microelectronic device structure comprising a first semiconductor structure, a first isolation material over the first semiconductor structure, and first conductive routing structures over the first semiconductor structure and surrounded by the first isolation material. A second microelectronic device structure comprising a second semiconductor structure and a second isolation material over the second semiconductor structure is formed. The second isolation material is bonded to the first isolation material to attach the second microelectronic device structure to the first microelectronic device structure. Memory cells comprising portions of the second semiconductor structure are formed after attaching the second microelectronic device structure to the first microelectronic device structure. Control logic devices including transistors comprising portions of the first semiconductor structure are formed after forming the memory cells.Type: GrantFiled: June 30, 2021Date of Patent: October 10, 2023Assignee: Micron Technology, Inc.Inventors: Fatma Arzum Simsek-Ege, Kunal R. Parekh, Terrence B. McDaniel, Beau D. Barry
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Patent number: 11774180Abstract: A heat pipe including a pipe body. The pipe body has an evaporation portion and a condensation portion. The condensation portion is connected to the evaporation portion. The condensation portion includes a condensation end. The evaporation portion includes an evaporation end. The evaporation end and/or the condensation end are/is in a rectangular shape.Type: GrantFiled: February 17, 2021Date of Patent: October 3, 2023Assignee: VAST GLORY ELECTRONICS & HARDWARE & PLASTIC(HUI ZHOU) LTD.Inventors: Xue Mei Wang, Lei Lei Liu
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Patent number: 11758690Abstract: A heat-dissipation device with detachability against the adhesion of a paste includes a heat-dissipation structure and a detachment device. The heat-dissipation structure installed on a heat-generating component includes a base, and a heat-dissipation element disposed on the base, and a through hole penetrating through the base. The detachment device includes a housing disposed on the base and covering the through hole, wherein the housing includes a gas chamber, and a gas hole connected to the gas chamber, the gas hole being in communication with the through hole. An adjustment element is movably disposed in the gas chamber. A gas in the housing is pushed out through the gas hole by moving the adjustment element downwards, creating a positive gas pressure and thus forcing a separation between the heat-dissipation structure and the heat-generating component on which the structure is installed.Type: GrantFiled: June 18, 2021Date of Patent: September 12, 2023Assignee: Nanning FuLian FuGui Precision Industrial Co., Ltd.Inventor: Chih-Yu Yeh
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Patent number: 11756852Abstract: A semiconductor device including a substrate, a semiconductor package, a plurality of pillars and a lid is provided. The semiconductor package is disposed on the substrate and includes at least one semiconductor die. The plurality of pillars are disposed on the semiconductor package. The lid is disposed on the substrate and covers the semiconductor package and the plurality of pillars. The lid includes an inflow channel and an outflow channel to allow a coolant to flow into and out of a space between the substrate, the semiconductor package, the plurality of pillars and the lid. An inner surface of the lid, which faces and overlaps the plurality of pillars along a stacking direction of the semiconductor package and the lid, is a flat surface.Type: GrantFiled: April 14, 2022Date of Patent: September 12, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Chun-Hui Yu, Jeng-Nan Hung, Kuo-Chung Yee, Po-Fan Lin
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Patent number: 11754343Abstract: Embodiments of the disclosure relate to an electronic assembly including a substrate having a first surface and a second surface opposite to the first surface and one or more electronic devices bonded to the first surface of the substrate. A first heat-storing region is embedded within the substrate and proximate to the second surface. The first heat-storing region comprises a phase change material encapsulated by an encapsulating layer. A melting temperature of the encapsulating layer is higher than a melting temperature of the phase change material and a maximum operating temperature of the one or more electronic devices. A heat transfer layer is embedded within the substrate and thermally connects the first heat-storing region to the one or more electronic devices.Type: GrantFiled: November 5, 2019Date of Patent: September 12, 2023Assignee: Toyota Motor Engineering & Manufacturing North America, Inc.Inventors: Shailesh N. Joshi, Ercan M. Dede
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Patent number: 11749584Abstract: The present disclosure describes heat dissipating structures that can be formed either in functional or non-functional areas of three-dimensional system on integrated chip structures. In some embodiments, the heat dissipating structures maintain an average operating temperature of memory dies or chips below about 90° C. For example, a structure includes a stack with chip layers, where each chip layer includes one or more chips and an edge portion. The structure further includes a thermal interface material disposed on the edge portion of each chip layer, a thermal interface material layer disposed over a top chip layer of the stack, and a heat sink over the thermal interface material layer.Type: GrantFiled: August 16, 2021Date of Patent: September 5, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Hsiang Huang, Chin-Chou Liu, Chin-Her Chien, Fong-yuan Chang, Hui Yu Lee
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Patent number: 11735548Abstract: Electronic assemblies may be fabricated with interconnects of different types present in multiple locations and comprising fused copper nanoparticles. Each interconnect or a portion thereof comprises a bulk copper matrix formed from fusion of copper nanoparticles or a reaction product formed from copper nanoparticles. The interconnects may comprise a copper-based wire bonding assembly, a copper-based flip chip connection, a copper-based hermetic seal assembly, a copper-based connector between an IC substrate and a package substrate, a copper-based component interconnect, a copper-based interconnect comprising via copper for establishing electrical communication between opposite faces of a package substrate, a copper-based interconnect defining a heat channel formed from via copper, and any combination thereof.Type: GrantFiled: August 8, 2019Date of Patent: August 22, 2023Assignee: Kuprion Inc.Inventor: Alfred A. Zinn
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Patent number: 11735434Abstract: A method is provided for producing an insulating circuit substrate with a heat sink including an insulating circuit substrate and a heat sink, the insulating circuit substrate including a circuit layer and a metal layer that are formed on an insulating layer, and the heat sink being bonded to the metal layer side. The method includes: an aluminum bonding layer forming step of forming an aluminum bonding layer formed of aluminum or an aluminum alloy having a solidus temperature of 650° C. or lower on the metal layer; and a heat sink bonding step of laminating a copper bonding material formed of copper or a copper alloy between the aluminum bonding layer and the heat sink and bonding the aluminum bonding layer, the copper bonding material, and the heat sink to each other by solid phase diffusion bonding.Type: GrantFiled: February 28, 2018Date of Patent: August 22, 2023Assignee: MITSUBISHI MATERIALS CORPORATIONInventors: Ryouhei Yumoto, Tomoya Oohiraki, Takeshi Kitahara, Yoshiyuki Nagatomo
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Patent number: 11737237Abstract: A liquid cooling arrangement for peripheral board incorporates cooling plates on one side and resilient cushion on the opposite side and enclosing the peripheral board between the cooling plates and the cushion. The cushion exerts pressure on the backside of the peripheral board to ensure physical contact of the microchips and the cooling plates for good thermal conductance. Cooling hoses are connected to the cooling plates to circulate cooling liquid. An electrically insulating layer may be included between the backside of the peripheral board and the cushion. An extension frame may optionally be added onto the cooling frame to house the cooling houses and increase the variability of deployments.Type: GrantFiled: February 3, 2021Date of Patent: August 22, 2023Assignee: BAIDU USA LLCInventor: Tianyi Gao
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Patent number: 11728237Abstract: The semiconductor device includes a supporting member, a conductive member, and a semiconductor element. The supporting member has a supporting surface facing in a thickness direction. The conductive member has an obverse surface facing the same side as the supporting surface faces in the thickness direction, and a reverse surface opposite to the obverse surface. The conductive member is bonded to the supporting member such that the reverse surface faces the supporting surface. The semiconductor element is bonded to the obverse surface. The semiconductor device further includes a first metal layer and a second metal layer. The first metal layer covers at least a part of the supporting surface. The second metal layer covers the reverse surface. The first metal layer and the second layer are bonded to each other by solid phase diffusion.Type: GrantFiled: October 23, 2019Date of Patent: August 15, 2023Assignee: ROHM CO., LTD.Inventor: Xiaopeng Wu