Abstract: A multi-layer structure of source/drain electrodes and an amorphous silicon layer in a forward staggered thin film transistor. Source/drain electrodes are selectively provided on an insulator. Each of the source/drain electrodes comprises an undoped transparent conductive film on the insulator and an impurity doped transparent conductive film extending over the undoped transparent conductive film. An amorphous silicon active layer extends over the source/drain electrodes and a top surface of the insulator so that the amorphous silicon active layer over the source/drain electrodes has an impurity diffused interface in contact with the impurity doped transparent conductive film to form ohmic contacts between the impurity doped transparent conductive film and the amorphous silicon active layer. The amorphous silicon active layer in contact with the top surface of the insulator between the source/drain electrodes is free of impurities.

Abstract: In a semiconductor substrate of a semiconductor device, a plural impurity layers of the same conductivity type as the substrate are formed. An impurity region of an opposite conductivity type penetrates at least one of the impurity layers to a certain depth from the main surface of the semiconductor substrate. The bottom surface of the impurity region terminates between the impurity layers where the impurity concentration is lower. A contact conductor is led out from the impurity region.

Abstract: A semiconductor light emitting device comprising: a substrate; and a gallium nitride type compound semiconductor layers provided on the substrate, the semiconductor layers including at least an N-type layer and a P-type layer; wherein an N-type side electrode connected to a gallium nitride type compound semiconductor of the N-type layer and a P-type side electrode connected to a gallium nitride type compound semiconductor of the P-type layer are provided, wherein the dopant for the gallium nitride type compound semiconductor layer of the P-type layer is Be.

Abstract: The present invention is directed to a process for forming a self-aligned raised source/drain MOS device comprising a planarized metal layer, preferably tungsten, overlying a source, a drain, and a gate that is provided on both sides with an insulating spacer to electrically isolate it from the source and drain. The planarized tungsten layer comprises a first portion whose lower surface is in contact with a polysilicon layer of the gate. The lower surface of each of the second and third portions of the tungsten layer is in contact with the source and drain, respectively. The second and third portions are insulated from the first portion by the insulating spacers, and the upper surfaces of all the portions comprise a coplanar surface. Planarization of the deposited metal layer thus provides ohmic contact at substantially the same level to the source, drain, and gate.

Abstract: A low temperature annealed Cu silicide or germanide layer on the surface of a single crystalline semiconductor substrate of Si or Ge is used in interconnection metallization for integrated circuits. The Cu silicide or germanide layer is preferably formed by heating Cu deposited on a Si or Ge substrate up to about 200.degree. C. for about 30 minutes. The layer demonstrates superior (near ideal) current/voltage characteristics and can be used as a high temperature (600-800.degree. C.) stable Ohmic/Schottky contact to Si or as a Cu diffusion barrier. Additional embodiments involve a Cu layer on a Ge layer on Si substrate, a Cu layer on a Si.sub.x Ge.sub.1-x layer on a substrate, and the use of an intermediate layer of a refractory metal such as W.

Abstract: The invention relates to a semiconductor device of the type sealed in glass, comprising a semiconductor body having a pn-junction between opposing faces which are connected to slugs of a transition metal, said slugs being connected to copper-containing connection conductors by a bonding layer, the bonding layer comprising, in addition to copper and silver, more than 1 wt. % germanium.

Abstract: A novel transistor with a low resistance ultra shallow tip region and its method of fabrication. The novel transistor of the present invention has a source/drain extension or tip region comprising an ultra shallow region which extends beneath the gate electrode and a raised region.

Abstract: A repairable, chip-to-board interconnect process which addresses cost and testability issues in the multi-chip modules. This process can be carried out using a chip-on-sacrificial-substrate technique, involving laser processing. This process avoids the curing/solvent evolution problems encountered in prior approaches, as well is resolving prior plating problems and the requirements for fillets.For repairable high speed chip-to-board connection, transmission lines can be formed on the sides of the chip from chip bond pads, ending in a gull wing at the bottom of the chip for subsequent solder.

Abstract: An ohmic contact structure for connection of a metal electrode to a highly integrated semiconductor device and a method for making the same. A contact hole is selectively formed in an insulating layer. A contact structure of a hetero-junction of Ge and Si.sub.1-x Ge.sub.x whose bandgap is lower than that of the underlying substrate material is formed between the interface of the metal electrode and the semiconductor substrate. The hetero-junction structure minimizes stress and strain between the metal electrode and the semiconductor substrate. The ohmic contact structure lowers the resistance of electronic lines and increases the reliability of integrated semiconductor devices.

Abstract: In a semiconductor device, an impurity diffused layer serving as an active region is formed in a predetermined region of the surface of a semiconductor substrate of silicon, an underlayer insulating film is formed on the semiconductor substrate for the purpose of protecting and stabilizing the surface of the semiconductor substrate, and an interconnection electrically connected to the impurity diffused layer through a contact hole and formed on an Al-Si-Sn alloy, an Al-Si-Sb alloy or alloys having Ti added to the respective alloys, so that occurrence of an alloy pit and a silicon nodule is prevented. In addition, a completed protective film is formed on the interconnection and the underlayer insulating film and an aperture in a bonding pad region is formed in a predetermined region of the completed protective film, so that the interconnection and the bonding pad are electrically connected to each other.

Abstract: An ohmic contact includes a metal boride layer on a semiconducting diamond layer. The metal boride preferably includes boron and a transition metal and, more preferably, a refractory metal. Heating of the metal boride layer and diamond during fabrication forms a highly boron-doped surface portion of the semiconductor diamond by boron diffusion. Alternately, the highly doped surface portion may be formed by selective ion implantation, annealing to form a graphitized surface portion, and removing the graphitized surface portion by etching to thereby expose the highly doped surface portion. The highly doped surface portion lowers the electrical resistivity of the contact. In addition, an interface region of a carbide may also be readily formed by heating. The carbide interface region enhances mechanical adhesion of the metal boride and also serves to lower the electrical resistance of the contact.

Abstract: A semiconductor circuit includes a signal line for transmitting bidirectional pulse currents and a power line for supplying a DC current, and the signal line and the power line are formed of different metal wiring layers. The power line is formed of a metal having higher melting point, higher electromigration resistance and lower resistivity than those of the signal line. As a result, the reliability of the wiring of the semiconductor device can be improved.

Abstract: Doped silicon-germanium alloy is selectively deposited on a semiconductor substrate, and the semiconductor substrate is then heated to diffuse at least some of the dopant from the silicon-germanium alloy into the semiconductor substrate to form a doped region at the face of the semiconductor substrate. The doped silicon-germanium alloy acts as a diffusion source for the dopant, so that shallow doped, regions may be formed at the face of the semiconductor substrate without ion implantation. A high performance contact to the doped region is also provided by forming a metal layer on the doped silicon-germanium alloy layer and heating to react at least part of the silicon-germanium alloy layer with at least part of the metal layer to form a layer of germanosilicide alloy over the doped regions. The method of the present invention is particularly suitable for forming shallow source and drain regions for a field effect transistor, and self-aligned source and drain contacts therefor.

Abstract: A method and resulting ohmic contact structure between a high work function metal and a wide bandgap semiconductor for which the work function of the metal would ordinarily be insufficient to form an ohmic contact between the metal and the semiconductor. The structure can withstand annealing while retaining ohmic characteristics. The ohmic contact structure comprises a portion of single crystal wide bandgap semiconductor material; a contact formed of a high work function metal on the semiconductor portion; and a layer of doped p-type semiconductor material between the single crystal portion and the metal contact. The doped layer has a sufficient concentration of p-type dopant to provide ohmic behavior between the metal and the semiconductor material.

Abstract: In an ohmic contact electrode for the p-type semiconductor diamond, the electrode is formed of metals or metallic compounds containing boron on a p-type semiconductor diamond, so as to obtain a decreased contact resistance.

Abstract: On the surface of n-type layer of Ga.sub.1-x Al.sub.x As (0.ltoreq.x.ltoreq.1) having n-type layer, Au layer is formed as a first layer, and alloying treatment is performed after Ge layer, Ni layer and Au layer are sequentially formed. The first Au layer, the second Ge layer, the third Ni layer and the fourth Au layer have the following thickness:______________________________________ 1st layer Au 10-100 .ANG. 2nd layer Ge 50-200 .ANG. 3rd layer Ni 50-200 .ANG. 4th layer Au 200-1000 .ANG. ______________________________________Thus, it is possible to form an ohmic electrode, which has low contact resistance and does not develop ball-up phenomenon.