Abstract: A semiconductor device and a method for manufacturing the same are disclosed. A dummy pattern is formed between a fuse pattern and a semiconductor substrate so as to prevent the semiconductor substrate from being damaged, and a buffer pattern is formed between the dummy pattern and the semiconductor substrate, so that a dummy metal pattern primarily absorbs or reflects laser energy transferred to the semiconductor substrate during the blowing of the fuse pattern, and the buffer pattern secondarily reduces stress generated between the dummy pattern and the semiconductor substrate, resulting in the prevention of a defect such as a crack.

Abstract: Structures having a hybrid MEMS RF switch and method of fabricating such structures using existing wiring layers of a device is provided. The method of manufacturing a MEMS switch includes forming a forcing electrode from a lower wiring layer of a device and forming a lower electrode from an upper wiring layer of the device. The method further includes forming a flexible cantilever arm over the forcing electrode and the lower electrode such that upon application of a voltage to the forcing electrode, the flexible cantilever arm will contact the lower electrode to close the MEMS switch.

Abstract: A semiconductor device includes: a semiconductor layer composed of one of GaAs based semiconductor, InP-based semiconductor, and GaN-based semiconductor; a first silicon nitride film that is provided on the semiconductor layer, and of which an end portion is in contact with a surface of the semiconductor layer; a protective film that is composed of one of polyimide and benzocyclobutene, and is provided on the semiconductor layer and the first silicon nitride film, the protective film covering the end portion of the first silicon nitride film; and a first metallic layer that is composed of one of titanium, tantalum and platinum, and is continuously provided from a first portion located between the semiconductor layer and the protective film to a second portion located between the end portion of the first silicon nitride film and the protective film, the first metallic layer being in contact with the surface of the semiconductor layer and a surface of the end portion of the first silicon nitride film.

Abstract: Annular, linear, and point contact structures are described which exhibit a greatly reduced susceptibility to process deviations caused by lithographic and deposition variations than does a conventional circular contact plug. In one embodiment, a standard conductive material such as carbon or titanium nitride is used to form the contact. In an alternative embodiment, a memory material itself is used to form the contact. These contact structures may be made by various processes, including chemical mechanical planarization and facet etching.

Abstract: A semiconductor package includes a semiconductor chip having a first surface, on which an electrode pad is arranged, and a second surface which is the other side of the semiconductor chip, an insulation member formed on the second surface of the semiconductor chip, and comprising a via hole at a position spaced apart from the semiconductor chip, and a conductive filler filling the via hole.

Abstract: A wiring metal contains a polycrystal of copper (Cu) as a primary element and an additional element other than Cu, and concentration of the additional element is, at crystal grain boundaries composing the Cu polycrystal and in vicinities of the crystal grain boundaries, higher than that of the inside of the crystal grains. The additional element is preferably at least one element selected from a group consisting of Ti, Zr, Hf, Cr, Co, Al, Sn, Ni, Mg, and Ag. This Cu wiring is formed by forming a Cu polycrystalline film, forming an additional element layer on this Cu film, and diffusing this additional element from the additional element layer into the Cu film. This copper alloy for wiring is preferred as metal wiring formed for a semiconductor device.

Abstract: A stack package includes a substrate, a lower semiconductor chip stacked on the substrate and electrically connected to the substrate through a lower via, a plurality of upper semiconductor chips stacked on the lower semiconductor chip and electrically connected to the lower via through an upper via, wherein the upper semiconductor chips are larger in size than the lower semiconductor chip, and an edge guide electrically connecting edge vias of the upper semiconductor chips and the substrate.

Abstract: A semiconductor device includes an interlayer film formed over a semiconductor substrate. A groove is formed in the interlayer film. A wiring formed in the groove is a copper alloy including copper and a metal element. An oxide layer of the metal element is formed over the surface of the wiring. The oxide layer is formed in a first region along a grain boundary of a copper crystal and a second region surrounded by the grain boundary, over the surface of the wiring. The oxide layer formed in the first region has a thickness greater than that of the oxide layer formed in the second region.

Abstract: A fabricating method of a semiconductor device is provided. Pillars are formed on a substrate. A first oxide layer is continuously formed on upper surfaces and side walls of the pillars by non-conformal liner atomic layer deposition. The first oxide layer continuously covers the pillars and has at least one first opening. The first oxide layer is partially removed to expose the upper surfaces of the pillars, and a first supporting element is formed on the side wall of each of the pillars. The first supporting element is located at a first height on the side wall of the corresponding pillar and surrounds the periphery of the corresponding pillar. The first supporting elements around two adjacent pillars are connected and the first supporting elements around two opposite pillars do not mutually come into contact and have a second opening therebetween.

Abstract: A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.

Abstract: Provided is a semiconductor device that comprises a metal gate having a low sheet resistance characteristic and a high diffusion barrier characteristic and a method of fabricating the metal gate of the semiconductor device. The semiconductor device includes a metal gate formed on a gate insulating film, wherein the metal gate is formed of a metal nitride that contains Al or Si and includes upper and lower portions where the content of Al or Si is relatively high and a central portion where the content of Al or Si is relatively low.

Abstract: Provided is a method of fabricating a semiconductor device. The method includes providing a substrate. The method includes forming a portion of an interconnect structure over the substrate. The portion of the interconnect structure has an opening. The method includes obtaining a boron-containing gas that is free of a boron-10 isotope. The method includes filling the opening with a conductive material to form a contact. The filling of the opening is carried out using the boron-containing gas. Also provided is a semiconductor device. The semiconductor device includes a substrate. The semiconductor device includes an interconnect structure formed over the substrate. The semiconductor device includes a conductive contact formed in the interconnect structure. The conductive contact has a material composition that includes Tungsten and Boron, wherein the Boron is a 11B-enriched Boron.

Abstract: A semiconductor memory device according to an embodiment includes a cell array block having a plurality of cell arrays stacked therein, each of the cell arrays including a plurality of memory cells and a plurality of selective wirings selecting the plurality of memory cells are stacked, a pillar-shaped first via extending in a stack direction from a first height to a second height and having side surfaces connected to a first wiring, and a pillar-shaped second via extending in the stack direction from the first height to the second height and having side surfaces connected to a second wiring upper than the first wiring, the second wiring being thicker in the stack direction than the first wiring and having a higher resistivity than the first wiring.

Abstract: A semiconductor device includes a substrate, a pattern including a conductive layer and a hard mask layer stacked over the substrate, a capping layer surrounding sidewalls of the pattern, and a stress buffer layer disposed between the hard mask layer and the capping layer. The stress buffer layer is configured to inhibit transfer of stress between the hard mask layer and the capping layer during a thermal process so as to inhibit leaning of the capping layer.

Abstract: In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the substrate; an isolation layer over the second area of the substrate, the isolation layer having a recess; and a conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess.

Abstract: An opening structure is disclosed. The opening structure includes: a semiconductor substrate; at least one dielectric layer disposed on the semiconductor substrate, wherein the dielectric layer has a plurality of openings exposing the semiconductor substrate, and each of the openings has a sidewall; a dielectric thin film covering at least a portion of the sidewall of each of the openings; an etch stop layer disposed between the semiconductor substrate and the dielectric layer and extending partially into the openings to isolate the dielectric thin film from the semiconductor substrate; and a metal layer filled in the openings.

Abstract: According to one embodiment, a semiconductor apparatus includes a substrate, a first semiconductor device, a circuit pattern, and a potential unit. The substrate includes a first insulating layer and a second insulating layer stacked with the first insulating layer. The first semiconductor device is provided on a side of the first insulating layer opposite to the second insulating layer side. The circuit pattern is provided between the first insulating layer and the second insulating layer. The potential unit is provided between the first insulating layer and the second insulating layer. The potential unit is connected to ground or a power source.

Abstract: The present invention discloses a MEMS (Micro-Electro-Mechanical System) integrated chip with cross-area interconnection, comprising: a substrate; a MEMS device area on the substrate; a microelectronic device area on the substrate; a guard ring separating the MEMS device area and the microelectronic device area; and a conductive layer on the surface of the substrate below the guard ring, or a well in the substrate below the guard ring, as a cross-area interconnection electrically connecting the MEMS device area and the microelectronic device area.

Abstract: A metal line of a semiconductor device includes an insulation layer formed on a semiconductor substrate. The insulation layer has a metal line forming region. A diffusion barrier is formed on a surface of the metal line forming region of the insulation layer. The diffusion barrier includes a multi-layered structure that includes an MoB2 layer, an MoxByNz layer and an Mo layer. A metal layer is formed on the diffusion barrier to fill the metal line forming region of the insulation layer.

Abstract: The present disclosure provides methods for forming semiconductor devices with laser-etched vias and apparatus including the same. In one embodiment, a method of fabricating a semiconductor device includes providing a substrate having a frontside and a backside, and providing a layer above the frontside of the substrate, the layer having a different composition from the substrate. The method further includes controlling a laser power and a laser pulse number to laser etch an opening through the layer and at least a portion of the frontside of the substrate, filling the opening with a conductive material to form a via, removing a portion of the backside of the substrate to expose the via, and electrically coupling a first element to a second element with the via. A semiconductor device fabricated by such a method is also disclosed.

Abstract: Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps of different depths are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures.

Abstract: A stacked integrated circuit (IC) may be manufactured with a second tier wafer bonded to a double-sided first tier wafer. The double-sided first tier wafer includes back-end-of-line (BEOL) layers on a front and a back side of the wafer. Extended contacts within the first tier wafer connect the front side and the back side BEOL layers. The extended contact extends through a junction of the first tier wafer. The second tier wafer couples to the front side of the first tier wafer through the extended contacts. Additional contacts couple devices within the first tier wafer to the front side BEOL layers. When double-sided wafers are used in stacked ICs, the height of the stacked ICs may be reduced. The stacked ICs may include wafers of identical functions or wafers of different functions.

Abstract: A composite substrate for a semiconductor chip includes a first covering layer containing a semiconductor material, a second covering layer, and a core layer arranged between the first covering layer and the second covering layer, wherein the core layer has a greater coefficient of thermal expansion than the covering layers.

Abstract: A trenched semiconductor power device includes a trenched gate insulated by a gate insulation layer and surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a semiconductor substrate. The source region surrounding the trenched gate includes a metal of low barrier height to function as a Schottky source. The metal of low barrier height further may include a PtSi or ErSi layer. In a preferred embodiment, the metal of low barrier height further includes an ErSi layer. The metal of low barrier height further may be a metal silicide layer having the low barrier height. A top oxide layer is disposed under a silicon nitride spacer on top of the trenched gate for insulating the trenched gate from the source region. A source contact disposed in a trench opened into the body region for contacting a body-contact dopant region and covering with a conductive metal layer such as a Ti/TiN layer.

Abstract: The present invention provides a metal nitride film that realizes an intended effective work function (for example, a high effective work function) and has EOT exhibiting no change or a reduced change, a semiconductor device using the metal nitride film, and a manufacturing method of the semiconductor device. The metal nitride film according to an embodiment of the present invention contains Ti, Al and N, wherein the metal nitride film has such molar fractions of Ti, Al and N as (N/(Ti+Al+N)) of 0.53 or more, (Ti/(Ti+Al+N)) of 0.32 or less, and (Al/(Ti+Al+N)) of 0.15 or less.

Abstract: A semiconductor device having a redistribution layer, and methods of forming same, are disclosed. After fabrication of semiconductor die on a wafer, a tape assembly is applied onto a surface of the wafer, in contact with the surfaces of each semiconductor die on the wafer. The tape assembly includes a backgrind tape as a base layer, and a film assembly adhered to the backgrind tape. The film assembly in turn includes an adhesive film on which is deposited a thin layer of conductive material. The redistribution layer pattern is traced into the tape assembly, using for example a laser. Thereafter, the unheated portions of the tape assembly may be removed, leaving the heated redistribution layer pattern on each semiconductor die.

Abstract: A new method to form an integrated circuit device is achieved. The method comprises providing a substrate. A sacrificial layer is formed overlying the substrate. The sacrificial layer is patterned to form temporary vertical spacers where conductive bonding locations are planned. A conductive layer is deposited overlying the temporary vertical spacers and the substrate. The conductive layer is patterned to form conductive bonding locations overlying the temporary vertical spacers. The temporary vertical spacers are etched away to create voids underlying the conductive bonding locations.

Abstract: A wiring board of the present invention (1) is arranged so that: pads (30) arranged in a plurality of rows include: first-row pads (30a) connected to first metal wires (10a) among metal wires (10); and second-row pads (30b) connected to second metal wires (10b) among the metal wires (10), the first metal wires (10a) being longer than the second metal wires (10b); each of the first metal wires (10a) is formed so as to be separated from a corresponding one of the second-row pads (30b) by at least an insulating layer, and so as to have a widthwise center in a lower region below the corresponding second-row pad (30b); and each of the first metal wires (10a) has widthwise edges provided, in a plan view, beyond widthwise edges of a corresponding one of the second-row pads (30b) in a region in which the first metal wire (10a) overlaps with the corresponding second-row pad (30b).

Abstract: A semiconductor device provided with a silicon carbide semiconductor substrate, and an ohmic metal layer joined to one surface of the silicon carbide semiconductor substrate in an ohmic contact and composed of a metal material whose silicide formation free energy and carbide formation free energy respectively take negative values. The ohmic metal layer is composed of, for example, a metal material such as molybdenum, titanium, chromium, manganese, zirconium, tantalum, or tungsten.

Abstract: A wiring substrate includes an insulating layer, a wiring layer buried in the insulating layer, and a connection pad connected to the wiring layer via a via conductor provided in the insulating layer and in which at least a part is buried in an outer surface side of the insulating layer, wherein the connection pad includes a first metal layer (a first copper layer) arranged on the outer surface side, an intermediate metal layer (a nickel layer) arranged on a surface of an inner layer side of the first metal layer, and a second metal layer (a second copper layer) arranged on a surface of an inner layer side of the intermediate metal layer, and a hardness of the intermediate metal layer is higher than a hardness of the first metal layer and the second metal layer.

Abstract: A semiconductor apparatus with a penetrating electrode having a high aspect ratio is manufactured with a low-temperature process. A first electrode 3 and a second electrode 6 of a semiconductor substrate 1 that are provided at the front and rear surface sides, respectively, are electrically connected by a conductive object 7 filled in a contact hole 4 and an extended portion 6a of the second electrode 6 extends to the contact hole 4. Even though the contact hole 4 has a high aspect ratio, film formation using the low-temperature process is enabled by using the conductive object 7, instead of forming the second electrode 6 on a bottom portion of the contact hole 4.

Abstract: A semiconductor device includes a semiconductor substrate including an NMOS region and a PMOS region, active regions of the semiconductor substrate defined by a device isolation structure formed in the semiconductor substrate, the active regions including an NMOS active region defined in the NMOS region and a PMOS active region defined in the PMOS region, a gate insulating film disposed over the active regions, and a dual poly gate including an amorphous titanium layer formed over the gate insulating film in the NMOS region and the PMOS region. The dual poly gate includes a stacked structure having a lower gate electrode formed of an impurity doped polysilicon layer, a barrier layer including the amorphous titanium layer, and an upper gate electrode formed of a tungsten layer.

Abstract: A semiconductor device with its package size close to its chip size has a stress absorbing layer, allows a patterned flexible substrate to be omitted, and allows a plurality of components to be fabricated simultaneously. There is: a step of forming electrodes on a wafer; a step of providing a resin later as a stress relieving layer on the wafer, avoiding the electrodes; a step of forming a chromium layer as wiring from electrodes over the resin layer; and step of forming solder balls as external electrodes on the chromium layer over the resin layer; and a step of cutting the wafer into individual semiconductor chips; in the steps of forming the chromium layer and solder balls, metal thin film fabrication technology is used during the wafer process.

Abstract: Embodiments of apparatus and methods for forming dual metal interconnects are described herein. Other embodiments may be described and claimed.

Abstract: In an ohmic layer and methods of forming the ohmic layer, a gate structure including the ohmic layer and a metal wiring having the ohmic layer, the ohmic layer is formed using tungsten silicide that includes tungsten and silicon with an atomic ratio within a range of about 1:5 to about 1:15. The tungsten silicide may be obtained in a chamber using a reaction gas including a tungsten source gas and a silicon source gas by a partial pressure ratio within a range of about 1.0:25.0 to about 1.0:160.0. The reaction gas may have a partial pressure within a range of about 2.05 percent to about 30.0 percent of a total internal pressure of the chamber. When the ohmic layer is employed for a conductive structure, such as a gate structure or a metal wiring, the conductive structure may have a reduced resistance.

Abstract: An alignment mark for defect inspection is disclosed. The alignment mark includes: a semiconductor substrate; a first type well disposed in the semiconductor substrate; a second type doping region disposed in the first type well; a dielectric layer disposed on the semiconductor substrate to cover the first type well and the second type doping region; and a plurality of conductive plugs formed in the dielectric layer for connecting to the second type doping region.

Abstract: Contact elements of sophisticated semiconductor devices may be formed by lithographical patterning, providing a spacer element for defining the final critical width in combination with increasing a width of the contact opening prior to depositing the spacer material. The width may be increased, for instance by ion sputtering, thereby resulting in superior process conditions during the deposition of a contact metal. As a result, the probability of generating contact failures for contact elements having critical dimensions of approximately 50 nm and less may be significantly reduced.

Abstract: A semiconductor device having a redistribution layer, and methods of forming same, are disclosed. After fabrication of semiconductor die on a wafer, a tape assembly is applied onto a surface of the wafer, in contact with the surfaces of each semiconductor die on the wafer. The tape assembly includes a backgrind tape as a base layer, and a film assembly adhered to the backgrind tape. The film assembly in turn includes an adhesive film on which is deposited a thin layer of conductive material. The redistribution layer pattern is traced into the tape assembly, using for example a laser. Thereafter, the unheated portions of the tape assembly may be removed, leaving the heated redistribution layer pattern on each semiconductor die.

Abstract: A method for manufacturing a three-dimensional, electronic system includes: providing a first integrated circuit structure in a first substrate, wherein the first integrated circuit structure has a contact pad at a first main side of the first substrate; providing a second substrate with a main side; forming a vertical contact area in the second substrate; after step (c) forming a semiconductor layer on the main side of the second substrate; forming a semiconductor device of a second integrated circuit structure in the second substrate with the semiconductor layer; removing the substrate material from a side of the second substrate opposite the main side, so that the vertical contact area at the opposite side is electrically exposed; arranging the first and second substrates on top of each other aligning the vertical contact area with the contact pad, so that an electrical connection between the first and second integrated circuit structures is produced via the vertical contact area and the contact pad.

Abstract: Briefly, a memory device comprising a beta phase tungsten seed layer is disclosed.

Abstract: A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO2 gate oxides are provided. Gate oxides formed from alloys such as cobalt-titanium are thermodynamically stable such that the gate oxides formed will have minimal reactions with a silicon substrate or other structures during any later high temperature processing stages. The process shown is performed at lower temperatures than the prior art, which inhibits unwanted species migration and unwanted reactions with the silicon substrate or other structures. Using a thermal evaporation technique to deposit the layer to be oxidized, the underlying substrate surface smoothness is preserved, thus providing improved and more consistent electrical properties in the resulting gate oxide.

Abstract: Provided are semiconductor devices and methods of fabricating the same, and more specifically, semiconductor devices having a W—Ni alloy thin layer that has a low resistance, and methods of fabricating the same. The semiconductor devices include the W—Ni alloy thin layer. The weight of Ni in the W—Ni alloy thin layer may be in a range from approximately 0.01 to approximately 5.0 wt % of the total weight of the W—Ni alloy thin layer.

Abstract: The present invention relates to a semiconductor device and its manufacturing method including the steps of: forming a first semiconductor element layer having a first wiring over a substrate; forming a second semiconductor element layer having a second wiring and fixed to a first structure body having a first sheet-like fiber body, a first organic resin, and a first electrode; preparing a second structure body having a second sheet-like fiber body, a second organic resin which is not cured, and a second electrode; disposing the second structure body between the first and second semiconductor element layers so that the first wiring, the second electrode, and the second wiring are overlapped with each other over the substrate; and curing the second organic resin.

Abstract: Embodiments of apparatus and methods for forming dual metal interconnects are described herein. Other embodiments may be described and claimed.

Abstract: The present invention provides a method of fabricating a semiconductor device, which could advance the commercialization of semiconductor devices with a copper interconnect. In a process of metal interconnect line fabrication, a TiN thin film combined with an Al intermediate layer is used as a diffusion barrier on trench or via walls. For the formation, Al is deposited on the TiN thin film followed by copper filling the trench. Al diffuses to TiN layer and reacts with oxygen or nitrogen, which will stuff grain boundaries efficiently, thereby blocking the diffusion of copper successfully.

Abstract: A method and device of nanostructured titania that is crack free. A method in accordance with the present invention comprises depositing a Ti film on a surface, depositing a masking layer on the Ti film, etching said masking layer to expose a limited region of the Ti film, the limited region being of an area less than a threshold area, oxidizing the exposed limited region of the Th.ucsbi film, and annealing the exposed limited region of the Ti film.

Abstract: A process for forming a local interconnect includes applying a layer of metal over a semiconductor layer. A layer of metal silicide is formed over the layer of metal. The layer of metal silicide is patterned to define the boundaries of the local interconnect. The metal silicide is reacted with the layer of metal to form a composite structure. The composite structure includes the metal silicide, another metal silicide formed as silicon from the metal silicide reacts with the underlying layer of metal and an intermetallic compound of the metal from the layer of metal and metal from the layer of metal silicide. The unreacted layer of metal is removed with the composite structure remaining as the local interconnect.

Abstract: An integrated circuit containing a vertical interconnect that includes a region of interconnect metal continuously surrounding one or more dielectric pillars. The vertical interconnect electrically contacts a top surface of a lower conductive structure. An upper conductive structure contacts a top surface of the vertical interconnect. A process of forming an integrated circuit that includes forming a vertical interconnect that has a region of interconnect metal continuously surrounding one or more dielectric pillars. The vertical interconnect electrically contacts a top surface of a lower conductive structure, and an upper conductive structure contacts a top surface of the vertical interconnect.

Abstract: A multi-layer TiN film with reduced tensile stress and discontinuous grain structure, and a method of fabricating the TiN film are disclosed. The TiN layers are formed by PVD or IMP in a nitrogen plasma. Tensile stress in a center layer of the film is reduced by increasing N2 gas flow to the nitrogen plasma, resulting in a Ti:N stoichiometry between 1:2.1 to 1:2.3. TiN films thicker than 40 nanometers without cracks are attained by the disclosed process.

Abstract: Polishing systems and methods for removing conductive material (e.g., noble metals) from microelectronic substrates are disclosed herein. Several embodiments of the methods include forming an aperture in a substrate material, disposing a conductive material on the substrate material and in the aperture, and disposing a fill material on the conductive material. The fill material at least partially fills the aperture. The substrate material is then polished to remove at least a portion of the conductive material and the fill material external to the aperture during which the fill material substantially prevents the conductive material from smearing into the aperture during polishing the substrate material.