Abstract: Method of forming a solder alloy deposit on a substrate comprising i) provide a substrate including a surface bearing electrical circuitry that includes at least one inner layer contact area, ii) form a solder mask layer on the substrate surface and patterned to expose at least one contact area, iii) contact the entire substrate area including the solder mask layer and the at least one contact area with a solution to provide a metal seed layer on the substrate surface, iv) form a structured resist layer on the metal seed layer, v) electroplate a first solder material layer containing tin onto the conductive layer, vi) electroplate a second solder material layer onto the first solder material layer, vii) remove the structured resist layer and etch away an amount of the metal seed layer sufficient to remove the metal seed layer from the solder mask layer area and reflow the substrate.

Abstract: In one embodiment of the present invention, inert nano-sized particles having dimensions from 1 nm to 1,000 nm are added into a solder ball. The inert nano-sized particles may comprise metal oxides, metal nitrides, metal carbides, metal borides, etc. The inert nano-sized particles may be a single compound, or may be a metallic material having a coating of a different material. In another embodiment of the present invention, a small quantity of at least one elemental metal that forms stable high melting intermetallic compound with tin is added to a solder ball. The added at least one elemental metal forms precipitates of intermetallic compounds with tin, which are dispersed as fine particles in the solder.

Abstract: Methods and apparatus for package on package structures. A structure includes a first integrated circuit package including at least one integrated circuit device mounted on a first substrate, a plurality of package on package connectors extending from a bottom surface and arranged in a pattern of one or more rows proximal to an outer periphery of the first substrate; and a second integrated circuit package including at least another integrated circuit device mounted on a second substrate and a plurality of lands on an upper surface coupled to the plurality of package on package connectors, and a plurality of external connectors extending from a bottom surface of the second substrate; wherein the pattern of the external connectors is staggered from the pattern of the package on package connectors so that the package on package connectors are not in vertical alignment with the external connectors. Methods for forming structures are disclosed.

Abstract: A junction body has a first member and a second member each of which is provided with a joining surface whose main component is copper. A solder member containing, in a tin-base solder material, a three-dimensional web structure whose main component is copper is provided between the first member and the second member. A copper-tin alloy whose average thickness is 2 ?m or more but 20 ?m or less is provided between the joining surfaces and the three-dimensional web structure.

Abstract: An integrated circuit module has a common function known good integrated circuit die with selectable functions. The selectable functions arc selected during packaging of the known good integrated circuit die. The known good integrated circuit die is mounted to a second level substrate. The second level substrate has wiring connections to the input/output pads of the known good integrated circuit die that select desired input functions and output functions. Further, the wiring connections on the second level substrate provide signal paths to transfer signals to the desired input function and signals from the desired output function, and signals to and from the common functions. Also, the wiring connections form connections between the input/output pads and external circuitry. To select the desired input functions and the desired output functions, appropriate logic states are applied to input/output pads connected to a function selector to configure a functional operation of the integrated circuit module.

Abstract: A method for the connection of two wafers in which a contact area is formed between the two wafers by placing the two wafers one on top of the other. The contact area is heated locally and for a limited time. A wafer arrangement comprises two wafers which have been placed one on top of the other and between whose opposite surfaces a contact area is located. The wafers are connected to one another at selected areas of the contact area.

Abstract: A power semiconductor module includes: an interconnect layer including an electrical conductor patterned on a dielectric layer, the electrical conductor including a power coupling portion having a thickness sufficient to carry power currents and a control coupling portion having a thickness thinner than that of the power coupling portion; and a semiconductor power device physically coupled to the interconnect layer and electrically coupled to the power coupling portion of the electrical conductor.

Abstract: A method of processing a semiconductor wafer is provided which comprises treating a metallization layer provided on a backside of the wafer to form a plurality of channels therein, such that at least some of the channels along substantially the length thereof extend through the thickness of the metallization layer to the backside of the wafer, thereby exposing the material of the backside of the wafer. When the semiconductor wafer is separated into dies, each die is provided with a plurality of channels, which extend to an edge of the die. On attaching the die to a die attach flag by solder, the solder does not stick to the exposed material of the backside of the die, and channels are thereby formed in the solder. This allows venting of gases formed in the solder, and decreases void formation in the solder.

Abstract: A method for manufacturing a semiconductor device includes preparing a semiconductor element including electrode pads laid out along the periphery of the semiconductor element in a tetragonal frame-shaped array to form a line of electrode pads along each side of the semiconductor element, preparing a wiring substrate including connection pads corresponding to the electrode pads, applying solder including a bulging central portion on an upper surface of each connection pad, forming pillar-shaped electrode terminals on the electrode pads so that each electrode terminal has an axis separated from a peak of the bulging central portion of the solder on the corresponding connection pad in a longitudinal direction of the corresponding connection pad, and electrically connecting the electrode terminals with the solder to the connection pad.

Abstract: A semiconductor device includes a semiconductor element on which electrode pads are laid out. A wiring substrate includes connecting pads respectively arranged in correspondence with the electrode pads. Pillar-shaped electrode terminals are respectively formed on the electrode pads of the semiconductor element. A solder joint electrically connects a distal portion of each electrode terminal and the corresponding connecting pad on the wiring substrate. Each electrode terminal includes a basal portion, which is connected to the corresponding electrode pad, and a guide, which is formed in the distal portion. The guide has a smaller cross-sectional area than the basal portion as viewed from above. The guide has a circumference and the basal portion has a circumference that is partially flush with the circumference of the guide. The guide is formed to guide solder toward the circumference of the guide.

Abstract: A method includes placing a mold chase over a bottom package, wherein the bottom package has a connector at a top surface of the bottom package. The mold chase includes a cover, and a pin under and connected to the cover. The pin occupies a space extending from a top surface of the connector to the cover. A polymer is filled into a space between the cover of the mold chase and the bottom package. The polymer is then cured. After the step of curing the polymer, the mold chase is removed, and the connector is exposed through an opening in the polymer, wherein the opening is left by the pin of the mold chase.

Abstract: A method comprises connecting a substrate having a plurality of integrated circuit (IC) dies to a package substrate, so that the package substrate extends beyond at least two edges of the substrate, leaving first and second edge portions of the package substrate having exposed contacts. The first and second edge portions meet at a first corner of the package substrate. At least a first upper die package is placed over the substrate, so that first and second edge portions of the first upper die package extend beyond the at least two edges of the substrate. Pads on the first and second edge portions of the first upper die package are connected to the contacts of the first and second edge portions of the package substrate.

Abstract: A microelectronic assembly and method for fabricating the same are described. In an example, a microelectronic assembly includes a microelectronic device having a surface with one or more areas to receive one or more solder balls, the one or more areas having a surface finish comprising Ni. A solder material comprising Cu, such as flux or paste, is applied to the Ni surface finish and one or more solder balls are coupled to the microelectronic device by a reflow process that forms a solder joint between the one or more solder balls, the solder material comprising Cu, and the one or more areas having a surface finish comprising Ni.

Abstract: Disclosed is a sinterable bonding material which is a liquid or a paste containing copper nanoparticles having a particle diameter of 1,000 nm or less, in which the copper nanoparticles have one or more particle diameter peaks of a number-based grain size distribution within a class of particle diameter of 1 to 35 nm and within a class of particle diameter of more than 35 nm and 1,000 nm or less respectively, and in which the copper nanoparticles include individual particles (primary particles) and secondary particles, each of the secondary particles being a fused body of the primary particles. Thus, oxidation resistance and bondability are made compatible in a sinterable bonding material using copper nanoparticles, and ion migration is suppressed in a bonded portion of a semiconductor device, etc. manufactured by using the sinterable bonding material.

Abstract: A stacked integrated circuit (IC) device with at least one IC die having a top semiconductor surface and a bottom surface and at least one through substrate via (TSV) including a tip protruding beyond the bottom surface to a tip length is provided. The tip has an outer dielectric tip liner, and an electrically conductive portion within the outer dielectric tip liner. A compliant layer is applied to the bottom surface of the IC die. The dielectric tip liner is removed from a distal portion of the tip to expose an electrically conductive tip portion. A solder material is deposited on the exposed distal portion of the tip. The solder material is reflowed and coalesced to form a solder bump on the distal portion of the tip.

Abstract: An electrical device includes a semiconductor chip. The semiconductor chip includes a routing line. An insulating layer is arranged over the semiconductor chip. A solder deposit is arranged over the insulating layer. A via extends through an opening of the insulating layer to electrically connect the routing line to the solder deposit. A front edge line portion of the via facing the routing line is substantially straight, has a concave curvature or has a convex curvature of a diameter greater than a maximum lateral dimension of the via.

Abstract: A semiconductor device includes a semiconductor element, a support member bonded to a first surface of the semiconductor element with a first bonding material and a lead electrode bonded to a second surface of the semiconductor element supported on the support member with a second bonding material, and further including a method of producing the semiconductor device. Respective connecting parts of the support member and the lead electrode are Ni-plated and each of the first and the second bonding material is a Sn solder having a Cu6Sn5 content greater than a eutectic content.

Abstract: The present invention provides a conductive composite comprising: suspension matrix, metal nanoparticles suspended within the suspension matrix, wherein the conductive composite has a conductivity greater than 104 S cm?1.

Abstract: An electronic component including a wiring board having a power-source pattern and a signal pattern, a semiconductor element mounted on the wiring board and having a power-source electrode pad and a signal electrode pad, a first connection portion being made of a conductive material and connecting the signal pattern of the wiring board and the signal electrode pad of the semiconductor element, and a second connection portion being made of a conductive material and connecting the power-source pattern of the wiring board and the power-source electrode pad of the semiconductor element. The conductive material of the first connection portion and the conductive material of the second connection portion are selected such that the conductive material of the second connection portion has an electrical resistance which is lower than an electrical resistance of the conductive material of the first connection portion.

Abstract: There is provided a semiconductor device including: a circuit board formed by bonding a first and a second metal plates to both surfaces of an insulating substrate respectively, at least one semiconductor element to be bonded to an external surface of the first metal plate through a first solder, and a radiating base plate to be bonded to an external surface of the second metal plate through a second solder, wherein the first and the second solders are constituted by solder materials of the same type, and a ratio of a sum of thicknesses of the first and the second metal plates to a thickness of the insulating substrate is set in a predetermined range to ensure an endurance to a temperature stress of each of the first and the second solders.

Abstract: A module (20) can include a first substrate (12) comprised of a first material, at least a second substrate (22) comprised of at least a second material, selectively applied solder (14) of a first composition residing between the first substrate and at least the second substrate, and selectively applied solder (16) of at least a second composition residing between the first substrate and at least the second substrate. Preferably, no crack will exist in the module as a result of a reflow process of the solder due to the CTE mismatch between the first and second substrates. The different selectively applied solder compositions can have different melting points and can be solder balls, solder paste, solder preform or any other known form of solder.

Abstract: A semiconductor device includes a substrate and a first sintered silver layer on the substrate. The semiconductor device includes a first semiconductor chip and a first diffusion soldered layer coupling the first semiconductor chip to the first sintered silver layer.

Abstract: Disclosed herein is a substrate with chip mounted thereon, including: a solder pattern having a plan-view shape in which projected parts are projected radially from a central part; and a chip fixed in the state of being aligned to the central part of the solder pattern.

Abstract: A method of manufacturing a ball grid array, BGA, integrated circuit package, comprising forming a double sided printed circuit board, PCB, with blind vias interconnecting electrically the circuits on the opposed surfaces of the PCB, with at least one through-hole to allow fluid or gas to pass through the PCB, and an integrated circuit connected to the printed circuit on one side of the PCB; soldering a lid onto the said one side of the PCB to enclose the integrated circuit, whilst allowing thermally expanding gas or fluid to escape through the or each through-hole, whereby to form a package which is hermetically sealed except for the or each through-hole, and which has a cavity between the integrated circuit and the lid; applying a BGA to the side of the PCB opposed to the said one side, whereby to solder the balls of the BGA to respective portions of the printed circuit and to align one of the balls axially with each through-hole; and soldering the ball or balls into the through-hole, or into each respectiv

Abstract: A flux composition includes an alditol (A) and a polymer (B) which has a repeating structural unit represented by Formula (1): (wherein R1 is a hydrogen atom or a methyl group, and Z is a hydroxyl group, an oxo group, a carboxyl group, a formyl group, an amino group, a nitro group, a mercapto group, a sulfo group, an oxazoline group, an imide group, a group having an amide structure, or a group having any of these groups). The flux composition allows substrates with bumps such as pillar bumps to be electrically connected to each other by reflowing of such bumps without causing any exposure of the bumps from the flux during reflowing, thus resulting in a satisfactory electrically connected structure.

Abstract: A paste for forming an interconnect includes a mixture of binder particles, filler particles and flux material, binder particles having a melting temperature that is lower than that of the filler particles, and the proportion of the binder particles and the filler particles being selected such when heat is applied to melt the binder particles the shape of the paste as deposited is substantially retained thereby allowing for the paste to be used for forming interconnect structures.

Abstract: A chip scale package implements solder bars to form a connection between a chip and a trace, formed in a substrate, such as another chip or PCB. Solder bars are formed by depositing one or more solder layers into the socket, or optionally, depositing a base metal layer into the socket and applying the solder layer to the base metal layer. The geometry of a solder bars may be rectangular, square, or other regular or irregular geometry. Solder bars provide a greater utilization of the connectivity footprint and increase the electrical and thermal flow capacity. Solder bars also provide a robust connection.

Abstract: A circuit board (1) exhibits an average coefficient of thermal expansion (A) of the first insulating layer (21) in the direction along the substrate surface in a temperature range from 25 degrees C. to its glass transition point of equal to or higher than 3 ppm/degrees C. and equal to or lower than 30 ppm/degrees C. Further, an average coefficient of thermal expansion (B) of the second insulating layer (23) in the direction along the substrate surface in a temperature range from 25 degrees C. to its glass transition point is equivalent to an average coefficient of thermal expansion (C) of the third insulating layer (25) in the direction along the substrate surface in a temperature range from 25 degrees C. to its glass transition point. (B) and (C) are larger than (A), and a difference between (A) and (B) and a difference between (A) and (C) are equal to or higher than 5 ppm/degrees C. and equal to or lower than 35 ppm/degrees C.

Abstract: The semiconductor device according to the present invention includes a semiconductor chip, a solid plate to which the semiconductor chip is bonded, and a bonding member made of a BiSn-based material interposed between the semiconductor chip and the solid plate, while the bonding member has a heat conduction path made of Ag for improving heat conductivity between the semiconductor chip and the solid plate.

Abstract: A method of manufacturing a hybrid integrated circuit device of the present invention includes the steps of preparing a lead frame which constituted by units each having a plurality of leads, and fixing a circuit substrate on each unit of the lead frame by fixing pads which are formed on the surface of the circuit substrate to the leads, where a space between a first pad which is formed at an end edge of the circuit substrate and a second pad which is adjacent to the first pad is set narrower than a space between the pads themselves.

Abstract: A power semiconductor device includes a substrate, an element circuit pattern formed on the substrate and made of Cu covered with an electroless Ni—P plating layer, and a power semiconductor element bonded to the element circuit pattern by a solder, wherein the solder is an alloy of Sn, Sb, and Cu, and the weight percent of Cu is in the range of 0.5 to 1%, inclusive.

Abstract: A lead-free paste composition contains an electrically conductive silver powder, one or more glass frits or fluxes, and a lithium compound dispersed in an organic medium. The paste is useful in forming an electrical contact on the front side of a solar cell device having an insulating layer. The lithium compound aids in establishing a low-resistance electrical contact between the front-side metallization and underlying semiconductor substrate during firing.

Abstract: A semiconductor device includes a substrate including a first metal layer, a first semiconductor chip having sidewalls, and a first solder layer contacting the first semiconductor chip and the first metal layer. The first metal layer includes a groove extending around sidewalls of the first semiconductor chip. The groove is at least partly filled with excess solder from the first solder layer.

Abstract: A microelectronic assembly includes a substrate having a first surface and a second surface remote from the first surface. A microelectronic element overlies the first surface and first electrically conductive elements are exposed at one of the first surface and the second surface. Some of the first conductive elements are electrically connected to the microelectronic element. Wire bonds have bases joined to the conductive elements and end surfaces remote from the substrate and the bases, each wire bond defining an edge surface extending between the base and the end surface. An encapsulation layer extends from the first surface and fills spaces between the wire bonds such that the wire bonds are separated by the encapsulation layer. Unencapsulated portions of the wire bonds are defined by at least portions of the end surfaces of the wire bonds that are uncovered by the encapsulation layer.

Abstract: Embodiments of IC manufacture resulting in improved electromigration and gap-fill performance of interconnect conductors are described in this application. Reflow agent materials such as Sn, Al, Mn, Mg, Ag, Au, Zn, Zr, and In may be deposited on an IC substrate, allowing PVD depositing of a Cu layer for gap-fill of interconnect channels in the IC substrate. The Cu layer, along with reflow agent layer, may then be reflowed into the interconnect channels, forming a Cu alloy with improved gap-fill and electromigration performance. Other embodiments are also described.

Abstract: Disclosed in this specification is a lead-free soldering alloy made of gold, tin and indium. The tin is present in a concentration of 17.5% to 20.5%, the indium is present in a concentration of 2.0% to 6.0% and the balance is gold and the alloy has a melting point between 290° C. and 340° C. and preferably between 300° C. and 340° C. The soldering alloy is particularly useful for hermetically sealing semiconductor devices since the melting temperature is sufficiently high to permit post-seal heating and sufficiently low to allow sealing of the semiconductor without causing damage.

Abstract: A semiconductor package is disclosed that includes a semiconductor device; a circuit board; and a connection mechanism including a first conductive terminal provided on the semiconductor device, and a second conductive terminal provided on the circuit board side, the connection mechanism electrically connecting the semiconductor device and the circuit board via the first conductive terminal and the second conductive terminal. At least one of the first conductive terminal and the second conductive terminal of the connection mechanism includes one or more carbon nanotubes each having one end thereof fixed to the surface of the at least one of the first conductive terminal and the second conductive terminal, and extending in a direction away from the surface. The first conductive terminal and the second conductive terminal engage each other through the carbon nanotubes.

Abstract: A power module includes a pair of power devices that are stacked with a plate-shaped output electrode arranged therebetween, and an N-electrode and a P-electrode that are stacked with the pair of power devices arranged therebetween. The output electrode is anisotropic such that the thermal conductivity in a direction orthogonal to the stacking direction is greater than the thermal conductivity in the stacking direction. Also, the output electrode extends in the orthogonal direction from a stacked area where the pair of power devices are stacked. The N-electrode and the P-electrode extend in the orthogonal direction while maintaining an opposing positional relationship.

Abstract: A first Sn absorption layer is formed on a principal surface of a first substrate, the first Sn absorption layer being made of metal absorbing Sn from AuSn alloy and lowering a relative proportion of Sn in the AuSn alloy. A second Sn absorption layer is formed on a principal surface of a second substrate, the second Sn absorption layer being made of metal absorbing Sn from AuSn alloy and lowering a relative proportion of Sn in the AuSn alloy. A solder layer made of AuSn alloy is formed at least on one Sn absorption layer of the first and second Sn absorption layers. The first and second substrates are bonded together by melting the solder layer in a state that the first and second substrates are in contact with each other, with the principal surfaces of the first and second substrates facing each other.

Abstract: A zinc based solder material 55 of the present invention is prepared by providing on the surface of a zinc based material 50, from which an oxide film 501 has been removed or at which an oxide film 501 does not exist, with a coating layer 51 containing primarily a metal whose oxide is more easily reducible than the oxide film 501. In a joined body and a power semiconductor module of the present invention, the zinc based solder material 55 is used in the joining portion, and after joining, the coating layer 51 does not exist.

Abstract: To provide an electronic component, containing: a wiring board containing electrode pads; a component including a plurality of electrodes, the component being mounted on the wiring board; a sealing resin covering the component; and a plurality of terminals configured to connect a wiring provided within the wiring board to an external substrate, wherein the plurality of electrodes and the electrode pads are connected with solder, and wherein a first resin layer and a second resin layer are provided between the solder and the sealing resin in this order from the side of the solder, where the first resin layer has a first Young's modulus and the second resin layer has a second Young's modulus larger than the first Young's modulus.

Abstract: A solder-top enhanced semiconductor device is proposed for packaging. The solder-top device includes a device die with a top metal layer patterned into contact zones and contact enhancement zones. At least one contact zone is electrically connected to at least one contact enhancement zone. Atop each contact enhancement zone is a solder layer for an increased composite thickness thus lowered parasitic impedance. Where the top metal material can not form a uniform good electrical bond with the solder material, the device die further includes an intermediary layer sandwiched between and forming a uniform electrical bond with the top metal layer and the solder layer. A method for making the solder-top device includes: a) Lithographically patterning the top metal layer into the contact zones and the contact enhancement zones. b) Forming a solder layer atop each of the contact enhancement zones using a stencil process for an increased composite thickness.

Abstract: A semiconductor package including connecting members having a controlled content ratio of gold capable of increasing durability and reliability by preventing an intermetallic compound having high brittleness from being formed. The semiconductor package includes a base substrate; a first semiconductor chip disposed on the base substrate; and a first connecting member for electrically connecting the base substrate and the first semiconductor chip, and comprising a first bonding portion that includes gold and has a first content ratio of gold that is controlled to prevent an intermetallic compound of AuSn4, (Cu, Au)Sn4, or (Ni, Au)Sn4 from being formed.

Abstract: An assembly can include a microelectronic element such as, for example, a semiconductor element having circuits and semiconductor devices fabricated therein, and a plurality of electrical connectors, e.g., solder balls attached to contacts of the microelectronic element. The connectors can be surrounded by first, inner regions 200 of compressible dielectric material and second, outer regions of dielectric material. In one embodiment, an underfill can contact a face of the microelectronic element between respective connectors or second regions. The second regions can provide restraining force, such that during volume expansion of the connectors, the first regions can compress against the restraining force of the second regions.

Abstract: A semiconductor device includes: a support base material, and a semiconductor element bonded to the support base material with a binder, the binder including: a porous metal material that contacts the support base material and the semiconductor element, and a solder that is filled in at least one part of pores of the porous metal material.

Abstract: A light emitting diode structure is disclosed that includes a light emitting active portion formed of epitaxial layers and carrier substrate supporting the active portion. A bonding metal system that predominates in nickel and tin joins the active portion to the carrier substrate. At least one titanium adhesion layer is between the active portion and the carrier substrate and a platinum barrier layer is between the nickel-tin bonding system and the titanium adhesion layer. The platinum layer has a thickness sufficient to substantially prevent tin in the nickel tin bonding system from migrating into or through the titanium adhesion layer.

Abstract: A method includes providing a mixture of molten indium and molten aluminum, and agitating the mixture while reducing its temperature until the aluminum changes from liquid phase to solid phase, forming particles distributed within the molten indium. Agitation of the mixture sufficiently to maintain the aluminum substantially suspended in the molten aluminum continues while further reducing the temperature of the mixture until the indium changes from a liquid phase to a solid phase. A metallic composition is formed, including indium and particles of aluminum suspended within the indium, the aluminum particles being substantially free from oxidation. The metallic (solder) composition can be used to form an assembly, including an integrated circuit (IC) device, at least a first thermal component disposed adjacent to the IC device, and a solder TIM interposed between and thermally coupled with each of the IC device and the first thermal component.

Abstract: A solder includes Sn (tin), Bi (bismuth) and Zn (zinc), wherein the solder has a Zn content of 0.01% by weight to 0.1% by weight.

Abstract: An RFID transponder having a semiconductor die with a solderable contact area and an antenna made from a winding wire, wherein the winding wire is soldered to the contact area, and the solderable contact area is made from a nickel based alloy.

Abstract: A microcircuit package having a ductile layer between a copper flange and die attach. The ductile layer absorbs the stress between the flange and semiconductor device mounted on the flange, and can substantially reduce the stress applied to the semiconductor device. In addition, the package provides the combination of copper flange and polymeric dielectric with a TCE close to copper, which results in a low stress structure of improved reliability and conductivity.