Abstract: A chip packaging method includes: providing a wafer, on which multiple bumps are formed; cutting the wafer into multiple chip units, wherein multiple vertical heat conduction elements are formed on the wafer or the chip units; disposing the chip units on a base material; and providing a package material to encapsulate lateral sides and a bottom surface of each of the chip units, to form a chip package unit, wherein the bottom surface of the chip unit faces the base material; wherein, in the chip package unit, the bumps on the chip units abut against the base material, and wherein the vertical heat conduction elements directly connect to the base material, or the base material includes multiple through-holes and the vertical heat conduction elements pass through the multiple through-holes in the base material.

Abstract: In a method of manufacturing a semiconductor package, a plurality of semiconductor chips are encapsulated in a carrier to provide encapsulated semiconductor chips. A first surface of the encapsulated semiconductor chips includes chip pads exposed from a first surface of the carrier. An alignment error of each of the semiconductor chips with respect to the carrier is measured. A redistribution wiring structure may be formed on the first surface of the carrier. Correction values for each layer of the redistribution wiring structure may be reflected while forming the redistribution wiring structure in order to correct the alignment error while forming the redistribution wiring structure. The redistribution wiring structure may have redistribution wirings electrically connected to the chip pads on the first surface of the carrier. Outer connection members may be formed on the redistribution wiring structure and may be configured to be electrically connected to the outermost redistribution wirings.

Abstract: The purification of monoalkyl tin trialkoxides and monoalkyl tin triamides are described using fractional distillation and/or ultrafiltration. The purified compositions are useful as radiation sensitive patterning compositions or precursors thereof. The fractional distillation process has been found to be effective for the removal of metal impurities down to very low levels. The ultrafiltration processes have been found to be effective at removal of fine particulates. Commercially practical processing techniques are described.

Abstract: An electronic device, including an array substrate, a pad portion disposed on the array substrate, and an integrated circuit disposed on the pad portion and comprising a bump portion. The pad portion includes a first sub-pad unit including a first pad having an inclined shape and a second sub-pad unit including a second pad having an inclined shape. The first pad and the second pad are symmetrically arranged with respect to an imaginary line that divides the pad portion. The pad portion is electrically connected with the bump portion.

Abstract: A semiconductor package includes a base comprising a top surface and a bottom surface that is opposite to the top surface; a first semiconductor chip mounted on the top surface of the base in a flip-chip manner; a second semiconductor chip stacked on the first semiconductor chip and electrically coupled to the base by wire bonding; an in-package heat dissipating element comprising a dummy silicon die adhered onto the second semiconductor chip by using a high-thermal conductive die attach film; and a molding compound encapsulating the first semiconductor die, the second semiconductor die, and the in-package heat dissipating element.

Abstract: A semiconductor package includes a chip, a redistribution structure, and first under-ball metallurgies patterns. The chip includes conductive posts exposed at an active surface. The redistribution structure is disposed on the active surface. The redistribution structure includes a first dielectric layer, a topmost metallization layer, and a second dielectric layer. The first dielectric layer includes first openings exposing the conductive posts of the chip. The topmost metallization layer is disposed over the first dielectric layer and is electrically connected to the conductive posts. The topmost metallization layer comprises first contact pads and routing traces connected to the first contact pads. The second dielectric layer is disposed on the topmost metallization layer and includes second openings exposing the first contact pads. The first under-ball metallurgies patterns are disposed on the first contact pads, extending on and contacting sidewalls and top surfaces of the first contact pads.

Abstract: A module includes: a board having a first surface; a first component and a second component mounted on the first surface; and a wire disposed to extend across the first component and having one end and the other end. The one end is connected to the second component. The wire is grounded.

Abstract: A semiconductor structure is provided. The semiconductor structure comprises a substrate, a via, a liner layer, a barrier layer, and a conductor. The via penetrates through the substrate. The liner layer is formed on a sidewall of the via. The barrier layer is formed on the liner layer. The barrier layer comprises a conductive 2D material. The conductor fills a remaining space of the via.

Abstract: In a method of manufacturing a multi-die semiconductor device, a metal leadframe includes a die pad and electrically-conductive leads arranged around the die pad. First and second semiconductor dice are arranged on the die pad. A laser-activatable material is disposed on the dice and leads, and a set of laser-activated lines is patterned, including a first subset coupling selected bonding pads of the dice to selected leads, a second subset coupling selected bonding pads amongst themselves, and a third subset coupling the lines in the second subset to at least one line in the first subset. A first metallic layer is deposited onto the laser-activated lines to provide first, second and third subsets of electrically-conductive lines. A second metallic layer is selectively deposited onto the first and second subsets by electroplating to provide first and second subsets of electrically-conductive tracks. The electrically-conductive lines in the third subset are selectively removed.

Abstract: Solid-state radiation transducer (SSRT) devices and methods of manufacturing and using SSRT devices are disclosed herein. One embodiment of the SSRT device includes a radiation transducer (e.g., a light-emitting diode) and a transmissive support assembly including a transmissive support member, such as a transmissive support member including a converter material. A lead can be positioned at a back side of the transmissive support member. The radiation transducer can be flip-chip mounted to the transmissive support assembly. For example, a solder connection can be present between a contact of the radiation transducer and the lead of the transmissive support assembly.

Abstract: A display device includes a substrate including a display area and a non-display area disposed near the display area, a plurality of pixels disposed in the display area, a plurality of signal lines disposed on the substrate and connected to the pixels, and a pad portion disposed in the non-display area and including a plurality of pads. The signal lines include a first crack detecting line connected to a first test voltage pad and a first pad at a first node, connected to a second pad at a second node, and extending around the non-display area between the first node and the second node, as well as a first data line including a first end connected to a first transistor connected to the first crack detecting line at the second node, and a second end connected to corresponding pixels from among the plurality of pixels.

Abstract: A first side of a tapeless leadframe package is etched to form a ring shaped protrusion and a lead protrusion extending from a base layer. An integrated circuit die is mounted to tapeless leadframe package in flip chip orientation with a front side facing the first side. An electrical and mechanical attachment is made between a bonding pad of the integrated circuit die and the lead protrusion. A mechanical attachment is made between the front side of the integrated circuit die and the ring shaped protrusion. The integrated circuit die and the protrusions from the tapeless leadframe package are encapsulated within an encapsulating block. The second side of the tapeless leadframe package is then etched to remove portions of the base layer and define a lead for a leadframe from the lead protrusion and further define a die support for the leadframe from the ring shaped protrusion.

Abstract: The present disclosure provides a pad structure and a testkey structure and a testing method for a semiconductor device. The pad structure includes: an insulating dielectric layer formed on a substrate; a metal interconnection structure formed in the insulating dielectric layer, the metal interconnection structure comprising a first section and a second section, which are insulated from each other; and a pad formed on the top of the insulating dielectric layer so as to be exposed therefrom at least at its top surface, electrically connected to the first section, and insulated from the second section. With this disclosure, reduced capture of plasma is achievable, mitigating adverse impact of plasma on the semiconductor device.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least a circuit substrate, a semiconductor die and a filling material. The circuit substrate has a first surface, a second surface opposite to the first surface and a cavity concave from the first surface. The circuit substrate includes a dielectric material and a metal floor plate embedded in the dielectric material and located below the cavity. A location of the metal floor plate corresponds to a location of the cavity. The metal floor plate is electrically floating and isolated by the dielectric material. The semiconductor die is disposed in the cavity and electrically connected with the circuit substrate. The filling material is disposed between the semiconductor die and the circuit substrate. The filling material fills the cavity and encapsulates the semiconductor die to attach the semiconductor die and the circuit substrate.

Abstract: The present invention relates to an LED filament lamp (10) comprising a two-dimensional flexible printed circuit board (100), PCB, having a first and a second opposing connection end portions (110, 120). The two-dimensional flexible PCB (100) comprises a plurality of filaments lines (130a-d) extending from the first connection end portion (110) to the second connection end portion (120), wherein each filament line (130a) comprises an array of LEDs (130a1-130aN). The two-dimensional flexible PCB (100) is arranged in a cylinder shape by connecting the first and the second opposing connection end portions (110, 120) such that each (130a) of the plurality of filament lines (130a-d) is connected to another (130b) one of the plurality of filament lines (130a-d) thereby a spiral LED filament (150) is formed by the plurality of filament lines (130a-d).

Abstract: A semiconductor device includes an integrated circuit die having bond pads and a bond wires. The bond wires are connected to respective ones of the bond pads by a ball bond. An area of contact between the ball bond and the bond pad has a predetermined shape that is non-circular and includes at least one axis of symmetry. A ratio of the ball bond length to the ball bond width may be equal to a ratio of the bond pad length to the bond pad width.

Abstract: A semiconductor device, and a method of manufacturing a semiconductor device, includes first stack structures enclosing first channel structures and spaced apart from each other. The first channel structures are spaced apart from each other at a first distance in each of the first stack structures and the first stack structures are spaced apart from each other at a second distance.

Abstract: In some embodiments, a radio-frequency device can be manufactured by a method that includes forming or providing a substrate, fabricating or providing a flip chip die having a front side and a back side, and including an integrated circuit implemented on the front side, and mounting the front side of the flip chip die on the substrate. The method can further include implementing a shielding component over the back side of the flip chip die to provide electromagnetic shielding between a first region within or on the flip chip die and a second region away from the flip chip die.

Abstract: Disclosed is a semiconductor device that has a first layer including conductive material, a bond wire coupled to an upper surface of the first layer, and a second layer including conductive material underneath the first layer. One or more interconnects couple the second layer to the first layer. In an example, the second layer has a plurality of discontinuous sections that includes (i) a connected section coupled to the one or more interconnects and (ii) one or more floating sections that are at least in part surrounded by the connected section, where the one or more floating sections are electrically floating and isolated from the connected section. The semiconductor device also includes an under-pad circuit on a substrate underneath the second layer, the under-pad circuit to transmit signals to one or more components external to the semiconductor device though the first layer.

Abstract: A semiconductor chip including a main electrode and a control electrode is bonded to a substrate. A wiring chip including a first electrode, a second electrode and a wiring is bonded to the substrate. A main electrode member is bonded to the main electrode. A control electrode member is bonded to the second electrode. The control electrode is bonded to the first electrode with a connection member. The semiconductor chip, the substrate, the wiring chip, the main electrode member, the control electrode member and the connection member are putted into a mold and are sealed with sealing material by injecting the sealing material into the mold in a state that distal end surfaces of the main electrode member and the control electrode member are pressed against a buffer material provided between the main electrode member/the control electrode member and the mold. The sealing material is not ground.

Abstract: A display device includes a substrate including a display area and a non-display area disposed near the display area, a plurality of pixels disposed in the display area, a plurality of signal lines disposed on the substrate and connected to the pixels, and a pad portion disposed in the non-display area and including a plurality of pads. The signal lines include a first crack detecting line connected to a first test voltage pad and a first pad at a first node, connected to a second pad at a second node, and extending around the non-display area between the first node and the second node, as well as a first data line including a first end connected to a first transistor connected to the first crack detecting line at the second node, and a second end connected to corresponding pixels from among the plurality of pixels.

Abstract: In a mounting structure in which an electronic component is mounted on a wiring board, a wiring sheet including an adhesive layer interposes between the electronic component and the wiring board and the electronic component is indirectly mounted on the wiring board. The electronic component is directly mounted on the adhesive layer of the wiring sheet and the adhesive layer of the wiring sheet is directly fitted to the wiring board. Conduction between the electronic component and the wiring board is attained by conduction between the electronic component and the wiring sheet and conduction between the wiring sheet and the wiring board.

Abstract: A memory device includes a package substrate and at least one stack of a plurality of semiconductor dies disposed on the package substrate. The plurality of semiconductor dies can be stacked in a shingled configuration. Each semiconductor die includes a plurality of slits disposed in a first direction. An offset direction defining the shingled arrangement is in-line with the first direction. Each semiconductor die can include a die substrate and a plurality of memory planes disposed on the die substrate with each memory plane having a memory cell array. Each slit can divide and separate each memory plane into at least one of logic blocks or sub-logic blocks. The semiconductor die can include a plurality of bond pads linearly aligned in a second direction that is perpendicular to the first direction.

Abstract: A semiconductor package is provided. The semiconductor package includes a chip pad of a semiconductor chip, the chip pad including a connection portion and a test portion in a first surface of the chip pad; a barrier layer covering the chip pad, the barrier layer defining a first opening and a second opening that is separate from the first opening, the first opening exposing the connection portion of the chip pad, and the second opening exposing the test portion of the chip pad; and a redistribution structure.

Abstract: An integrated circuit includes a semiconductor substrate, electronic components integrated in the semiconductor substrate, an electric connection structure overlying the semiconductor substrate, and an conductive region, with elongated shaped, having a first and a second end. The conductive region is formed in the electric connection structure, extends over an entire length of the substrate and is not directly electrically connected to the electronic components. A first and a second synchronization connection element are electrically coupled to the first end and to the second end, respectively, of the conductive region and have each a respective synchronization connection portion facing the coupling face.

Abstract: The conductive wire is bonded to the front electrode of the semiconductor device at the bonding section. The first resin member covers at least one end portion of two end portions of the bonding section, the first surface of the front electrode, and the second surface of the conductive wire. The second resin member covers the bent portion of the first resin member. The first resin member has a higher break elongation and a higher break strength than the second resin member. The second tensile elastic modulus of the second resin member is greater than the first tensile elastic modulus of the first resin member. Thereby, the reliability of the power semiconductor module is improved.

Abstract: A method of manufacturing a display device including the steps of providing a lower substrate having a display area and a pad area, forming a display structure in the display area of the lower substrate, forming pad electrodes in the pad area of the lower substrate to be spaced apart from each other in a first direction parallel to a top surface of the lower substrate, forming an upper substrate on the display structure to face the lower substrate in the display area, forming a conductive film member including a non-cured resin layer and conductive balls arranged in a lattice shape on the pad electrodes, the non-cured resin layer overlapping the pad electrodes, and forming a film package on the non-cured resin layer, the film package including bump electrodes overlapping the pad electrodes.

Abstract: Disclosed a photosensitive assembly, an imaging module, a smart terminal, and a method and a mould for manufacturing the photosensitive assembly.

Abstract: A semiconductor device package and method for manufacturing the same are provided. The semiconductor device package includes a dielectric layer, an electronic component, a first conductive layer, and a conductive element. The dielectric layer has a first surface and a second surface opposite to the first surface. The electronic component is embedded in the dielectric layer. The first conductive layer is embedded in the dielectric layer and adjacent to the first surface of the dielectric layer. The conductive element is disposed on the first surface of the dielectric layer and in contact with the first conductive layer.

Abstract: Electronic device package technology is disclosed. An electronic device package in accordance with the present disclosure can include an electronic component, a redistribution layer, and an interposer electrically coupling the redistribution layer and the electronic component. The interposer can have interconnect interfaces on a top side electrically coupled to the electronic component and interconnect interfaces on a bottom side electrically coupled to the redistribution layer. A density of the interconnect interfaces on the top side can be greater than a density of the interconnect interfaces on the bottom side. Associated systems and methods are also disclosed.

Abstract: The circuit board includes a plurality of bonding pads having a first bonding pad and a second bonding pad configured to supply a ground potential; a first ground wiring connected to the first bonding pad; a second ground wiring connected to the second bonding pad; and a first extension pad connected to the first ground wiring and a second extension pad connected to the second ground wiring, the first extension pad and the and second extension pad being provided in a different area from an area in which the plurality of bonding pads is provided, the first extension pad and the and second extension pad being connectable through a wire.

Abstract: A display panel includes: a display substrate having a display area, and a pad area disposed on at least one side of thereof; and a plurality of pad groups arranged on the pad area in a first direction and including: a first pad group having a plurality of first pads, at least some of the plurality of first pads have a first inclination with respect to a reference line extending in a second direction different from the first direction, and the plurality of first pads being spaced from each other at a first pitch; and a second pad group having a plurality of second pads, at least some of the plurality of second pads having a different second inclination with respect to the reference line, and the plurality of second pads being spaced from each other at a second pitch different from the first pitch.

Abstract: A semiconductor die (“die”) employing repurposed seed layer for forming additional signal paths to a back end-of-line (BEOL) structure of the die, and related integrated circuit (IC) packages and fabrication methods. A seed layer is repurposed that was disposed adjacent the BEOL interconnect structure to couple an under bump metallization (UBM) interconnect without a coupled interconnect bump thus forming an unraised interconnect bump, to a UBM interconnect that has a raised interconnect bump. To couple the unraised interconnect bump to the raised interconnect bump, the seed layer is selectively removed during fabrication to leave a portion of the seed layer repurposed that couples the UBM interconnect that does not have an interconnect bump to the UBM interconnect that has a raised interconnect bump. Additional routing paths can be provided between raised interconnect bumps to the BEOL interconnect structure through coupling of UBM interconnects to an unraised interconnect bump.

Abstract: A chip package structure is provided. The chip package structure includes a first chip structure including a substrate and an interconnect layer over the substrate. The chip package structure includes a second chip structure over the interconnect layer. The chip package structure includes a first conductive bump connected between the interconnect layer and the second chip structure. The chip package structure includes a conductive pillar over the interconnect layer. The chip package structure includes a molding layer over the interconnect layer and surrounding the second chip structure, the first conductive bump, and the conductive pillar. The chip package structure includes a second conductive bump over a first surface of the conductive pillar. The first surface faces away from the first chip structure.

Abstract: A semiconductor device includes a shielding wire formed across a semiconductor die and an auxiliary wire supporting the shielding wire, thereby reducing the size of a package while shielding the electromagnetic interference generated from the semiconductor die. In one embodiment, the semiconductor device includes a substrate having at least one circuit device mounted thereon, a semiconductor die spaced apart from the circuit device and mounted on the substrate, a shielding wire spaced apart from the semiconductor die and formed across the semiconductor die, and an auxiliary wire supporting the shielding wire under the shielding wire and formed to be perpendicular to the shielding wire. In another embodiment, a bump structure is used to support the shielding wire. In a further embodiment, an auxiliary wire includes a bump structure portion and wire portion and both the bump structure portion and the wire portion are used to support the shielding wire.

Abstract: An integrated circuit package includes a support substrate having a front side and a back side and an optical integrated circuit die having a back side mounted to the front side of the support substrate and having a front side with an optical sensing circuit. A glass optical element die has a back side mounted to the front side of the optical integrated circuit die over the optical sensing circuit. The mounting of the glass optical element die is made by a layer of transparent adhesive which extends to the cover the optical sensing circuit and a portion of the front side of the optical integrated circuit die peripherally surrounding the optical sensing circuit. An encapsulation material body encapsulates the glass optical element die and the optical integrated circuit die.

Abstract: The disclosed principles provide for implementing low-cost and fast metallic printing processes into the QFN and other no-leads package assembly flow to selectively print solderable material in areas that would otherwise be susceptible to corrosion and thus pose reliability risks. The problem of copper corrosion and poor BLR performance in no-leads packages because of remaining exposed copper areas after package singulation is solved by employing selective metallic printing processes in the assembly flow to coat all risk-prone areas with solder material. For example, for no-leads packages that are formed using printed leadframes, solder can be deposited through inkjet, screen, stencil, or photonic printing into the grooves which are formed after passivating the packages at the strip level. The singulating occurs through the grooves having solder printed therein, and results in wettable upper and sidewall surfaces of the outer ends of the leadframe for each package.

Abstract: The present invention discloses a circuit substrate including an insulation layer; a metal layer disposed on a first surface of the insulation layer; and a first solder pad and a second solder pad disposed on a second surface of the insulation layer opposite the metal layer. Shortest distances between soldering dots on the metal layer and a projected area of the first solder pad on the metal layer are shorter than a distance threshold, the shortest distance being a minimum value of vertical distances between each of the soldering dots on the metal layer and a side edge of the projected area of the first solder pad on the metal layer. The soldering dots on the metal layer correspond one-to-one to soldering dots on a corresponding die; and the side edge is adjacent to a projected area of the second solder pad on the metal layer.

Abstract: A semiconductor device includes a first terminal, a second terminal, and a plurality of third terminals on a substrate. Memory chips are stacked on the substrate in an offset manner. Each memory chip has first pads, second pads, and third pads thereon. A first bonding wire is electrically connected to the first terminal and physically connected to a first pad of each memory chip. A second bonding wire is electrically connected to the second terminal and physically connected to a second pad of each memory chip. A third bonding wire electrically connects one third terminal to a third pad on each memory chip. A fourth bonding wire is connected to the first bonding wire at a first pad on a first memory chip of the stack and another first pad on the first memory chip. The fourth bonding wire straddles over the second bonding wire and the third bonding wire.

Abstract: A chip package structure is provided. The chip package structure includes a first chip, a second chip, and a third chip. The chip package structure includes a first molding layer surrounding the first chip and the second chip. The first molding layer is a single layer structure. A first boundary surface between the passivation layer and the second molding layer extends toward the first chip. The chip package structure includes a second molding layer surrounding the third chip and the first molding layer. A first bottom surface of the first molding layer and a second bottom surface of the second molding layer are substantially coplanar.

Abstract: A method for contacting and packaging a semiconductor chip of a power electronic component. The power electronic component has a first contact face produced in a first step via a multi-material printing process and a semiconductor chip, which is placed in a second step onto the first contact face. A ceramic insulation layer, which surrounds the semiconductor chip along its circumference and extends over the first contact face not covered by the semiconductor chip, is printed in a third step onto the first contact face. A second contact face is printed in a fourth step onto the ceramic insulation layer and the semiconductor chip. In a fifth step, the power electronic component is sintered by means of heat treatment.

Abstract: A printed board includes a first wiring layer including a first terminal, a second wiring layer including a second terminal facing to the first terminal, a dielectric layer interposed between the first wiring layer and the second wiring layer and having an end face, and a plurality of through-hole vias configured to electrically connect the first terminal and the second terminal. The plurality of through-hole vias includes a first through-hole via which is closest to an end-face edge of the first terminal, and a second through-hole via which is closest to an inner edge of the second terminal. The end-face edge being closer to the end face than the inner edge. A distance between the first through-hole via and the end-face edge is equal to or smaller than one eighth of a signal wavelength of a high speed signal transmitted through the first terminal.

Abstract: A semiconductor device has a substrate and a first electrical component disposed over a first surface of the substrate. An RF antenna interposer is disposed over the substrate with the first electrical component connected to a first antenna disposed on a surface of the antenna interposer. An area of the antenna interposer is substantially the same as an area of the substrate. The first antenna disposed on the surface of the antenna interposer has a plurality of islands of conductive material. Alternatively, the first antenna disposed on the surface of the antenna interposer has a spiral shape of conductive material. A second antenna can be disposed on the surface of the antenna interposer connected to a second electrical component disposed over the substrate. A second electrical component can be disposed over a second surface of the substrate opposite the first surface of the substrate.

Abstract: A semiconductor package and a fabrication method of the semiconductor package are disclosed. First and second redistribution layer patterns are formed on a semiconductor substrate including a chip region and a scribe lane region to provide a bonding pad portion and an edge pad portion, respectively. A polymer pattern is formed to reveal the bonding pad portion and a portion of the edge pad portion. A dicing line is set on the scribe lane region. A stealth dicing process is performed along the dicing line to separate a semiconductor chip including the bonding pad portion from the semiconductor substrate. The semiconductor chip is disposed on a package substrate. A bonding wire is formed to connect the bonding pad portion to the package substrate. The bonding wire is supported by an edge of the polymer pattern to be spaced apart from the revealed portion of the edge pad portion.

Abstract: A nonvolatile memory device of an embodiment includes: a first wiring line extending in a first direction; a second wiring line extending in a second direction intersecting the first direction; a memory cell disposed between the first layer and the second layer, and has first and second terminals, the memory cell including a variable resistance element; a first drive circuit capable of supplying a first potential and a second potential lower than the first potential; a second drive circuit supplying a third potential having a different polarity from a polarity of the first potential; a third drive circuit capable of supplying the second potential and a fourth potential higher than the second potential; a fourth drive circuit supplying a fifth potential having a different polarity from a polarity of the first potential; and a control circuit electrically connected to the first to fourth drive circuits.

Abstract: An electronic package is provided, in which an electronic component with a conductive layer on an outer surface thereof is embedded in an encapsulant, where at least one electrode pad is disposed on an active surface of the electronic component, and at least one wire electrically connected to the electrode pad is arranged inside the electronic component, so that the conductive layer is electrically connected to the wire, such that the electrode pad, the wire and the conductive layer are used as a power transmission structure which serves as a current path to reduce DC resistance and improve an impedance issue associated with the supply of power.

Abstract: A semiconductor device includes: a substrate; a circuit element disposed on a first surface side of the substrate; a first transmission line disposed on the first surface side; a first terminal disposed on the first surface side; a first dielectric disposed in a part of the first transmission line; a second terminal disposed on a side of the first dielectric opposite to the first transmission line; a second transmission line disposed on the first surface side and has one end coupled to the circuit element; a third terminal disposed on the first surface side and coupled to the other end of the second transmission line; a second dielectric disposed in a part of the second transmission line; a fourth terminal disposed on a side of the second dielectric opposite to the second transmission line; and a conductor disposed on a second surface side of the substrate.

Abstract: A method for fabricating a substrate structure for packaging includes providing a core substrate, a plurality of conductive pads at a first surface of the core substrate, and a metal layer at a second surface of the core substrate opposite to the first surface; forming a conductive structure, for pasting the substrate structure onto an external component, on each of the plurality of conductive pads; forming a molding compound on the first surface of the core substrate and to encapsulate the conductive structure; and forming a plurality of packaging pads by patterning the metal layer at the second surface of the core substrate.

Abstract: In one example, a semiconductor device includes a substrate having leads that include lead terminals, lead steps, and lead offsets extending between the lead steps so that at least some lead steps reside on different planes. A first electronic component is coupled to a first lead step side and includes a first electronic component first side, and a first electronic component second side opposite to the first electronic component first side. A second electronic component is coupled to a second lead step side, and includes a second electronic component first side, and a second electronic component second side opposite to the second electronic component first side. An encapsulant encapsulates the first electronic component, the second electronic component, and portions of the substrate. The lead terminals are exposed from a first side of the encapsulant. Other examples and related methods are also disclosed herein.

Abstract: Embodiments may relate to a radio frequency (RF) multi-chip module that includes a first RF die and a second RF die. The first and second RF dies may be coupled with a package substrate at an inactive side of the respective dies. A bridge may be coupled with an active side of the first and second RF dies die such that the first and second RF dies are communicatively coupled through the bridge, and such that the first and second RF dies are at least partially between the package substrate and the bridge. Other embodiments may be described or claimed.