Abstract: A semiconductor device includes a header, a semiconductor chip fixed to the header constituting a MOSFET, and a sealing body of insulating resin which covers the semiconductor chip, the header and the like, and further includes a drain lead contiguously formed with the header and projects from one side surface of the sealing body, and a source lead and a gate lead which project in parallel from one side surface of the sealing body, and wires which are positioned in the inside of the sealing body and connect electrodes on an upper surface of the semiconductor chip and the source lead and the gate lead, with a gate electrode pad arranged at a position from the gate lead and the source lead farther than a source electrode pad.

Abstract: A light emitting diode (10) includes an LED chip (14) and an encapsulant (16) enclosing the LED chip. The LED chip has a light emitting surface (141), and the encapsulant has a light output surface (161) over the light emitting surface. The light output surface defines a plurality of annular, concentric grooves (163). Each groove is cooperatively enclosed by a first groove wall (165) and a second groove wall (166). The first groove wall is a portion of a circumferential side surface of a cone, and a conical tip of the cone is located on the light emitting surface of the LED chip.

Abstract: The present application relates to a reinforcing structure (1, 2) for reinforcing a stack of layers (100) in a semiconductor component, wherein at least one reinforcing element (110, 118) having at least one integrated anchor-like part (110a, 110b), is provided. The basic idea is to reinforce bond pad structures by providing a better mechanical connection between the layers below an advanced underbump metallization (BUMA, UBM) by providing reinforcing elements under the UBM and/or BUMA layer.

Abstract: The die bonding resin paste of the invention comprises a polyurethaneimide resin represented by the following general formula (I), a thermosetting resin, a filler and a printing solvent. [wherein R1 represents a divalent organic group containing an aromatic ring or aliphatic ring, R2 represents a divalent organic group with a molecular weight of 100-10,000, R3 represents a tetravalent organic group containing 4 or more carbon atoms, and n and m each independently represent an integer of 1-100.

Abstract: A process for structuring at least one layer as well as an electrical component with structures from the layer are described. The invention states a process to generate at least one structured layer (10A), wherein a mask structure (20) with a first (20A) and second structure (20B) is generated on a layer (10) which is present on a substrate (5). Through this mask structure (20), the first layer (20A) is transferred onto the layer (10) using isotropic structuring processes, and the second structure (20B) is transferred onto the layer (10) using anisotropic structuring processes. The process as per the invention permits the generation of two structures (20A, 20B) in at least a single layer while using a single mask structure.

Abstract: The detachment of a semiconductor chip (1) from a foil (4) and picking the semiconductor chip (1) from the foil (4) takes place with the support of a chip ejector (6), that has a ramp (16), the surface (17) of which is formed concave and ends at a stripping edge (18) projecting from the surface (9) of the chip ejector (6), and a support area (13) with grooves (12) arranged next to the stripping edge (18). Vacuum can be applied to the grooves (12). The detachment and picking of the semiconductor chip (1) from the foil (4) takes place in that the wafer table (5) is shifted relative to the chip ejector (6) in order to pull the foil (4) over the stripping edge (18) protruding from the surface (9) of the chip ejector (6), whereby the semiconductor chip (1) temporarily detaches itself at least partially from the foil (4) and lands on the foil (4) above the support area (13), and in that the chip gripper (7) picks the semiconductor chip (1) presented on the support area (13).

Abstract: A method for selectively altering a predetermined portion of an object or an external member in contact with the predetermined portion of the object is disclosed. The method includes selectively electrically addressing the predetermined portion, thereby locally resistive heating the predetermined portion, and exposing the object, including the predetermined portion, to the external member.

Abstract: A land grid array module is provided that includes a land grid array interface. The interface includes a substrate having a mating face. A contact pad is provided on the mating face of the substrate. The contact pad has an exposed surface with a depression that is configured to restrain transverse movement of a mating contact tip when the mating contact tip is loaded against the contact pad. The substrate layer may include a via having a diameter such that the depression is formed in the contact pad when the contact pad is plated over the via. The depression may also be stamped in the exposed surface of the contact pad. Alternatively, the depression may be surrounded by a raised conductive perimeter that is configured to retain the mating contact tip.

Abstract: Semiconductor process technology and devices are provided, including a method for forming a high quality group III nitride layer on a silicon substrate and to a device obtainable therefrom. According to the method, a pre-dosing step is applied to a silicon substrate, wherein the substrate is exposed to at least 0.01 ?mol/cm2 of one or more organometallic compounds containing Al, in a flow of less than 5 ?mol/min. The preferred embodiments are equally related to the semiconductor structure obtained by the method, and to a device comprising said structure.

Abstract: An integrated circuit in one embodiment includes asymmetric cores and an asymmetric core control circuit. At least one of the asymmetric cores is a different implementation of substantially the same function or subset of functionality as another core. The asymmetric core control circuit determines a performance parameter of an integrated circuit. The performance parameter may be the workload, the operating frequency, power consumption, quality of service, operating temperature or the like of the integrated circuit or a given portion of the integrated circuit. If the performance parameter is within a first range, the asymmetric core control circuit utilizes a first core to perform a function of the integrated circuit and idles a second core that is a different implementation of substantially the same function. If the performance parameter is within a second range, the core control circuit utilizes the second core to perform the function and idles the first core.

Abstract: A plurality of conductive pads (2) are formed on a mounting surface of a mounting board. Conductive pads (11) are formed on a principal surface of a semiconductor chip (10) at positions corresponding to the conductive pads of the mounting board, when the principal surface faces toward the mounting board. A plurality of conductive nanotubes (12) extend from the conductive pads of one of the mounting board and the semiconductor chip. A press mechanism (3) presses the semiconductor chip against the mounting board and restricts a position of the semiconductor chip on the mounting surface to mount the semiconductor chip on the mounting board, in a state that tips of the conductive nanotubes are in contact with the corresponding conductive pads not formed with the conductive nanotubes.

Abstract: Single spacer processes for multiplying pitch by a factor greater than two are provided. In one embodiment, n, where n?2, tiers of stacked mandrels are formed over a substrate, each of the n tiers comprising a plurality of mandrels substantially parallel to one another. Mandrels at tier n are over and parallel to mandrels at tier n?1, and the distance between adjoining mandrels at tier n is greater than the distance between adjoining mandrels at tier n?1. Spacers are simultaneously formed on sidewalls of the mandrels. Exposed portions of the mandrels are etched away and a pattern of lines defined by the spacers is transferred to the substrate.

Abstract: A chip structure according to the present invention is provided. A plurality of pedestals extends from the back surface of the chip structure. Each of the pedestals is located at a position away from the edge of the back surface for a non-zero distance so that the pedestals of an upper chip structure will not damage the bonding pads positioned on the edge of the active surface of a lower chip structure when the upper chip structure is stacked on the active surface of the lower chip structure with the pedestals.

Abstract: Apparatus and methods for performing quantum computations are disclosed. Such apparatus and methods may include identifying a first quantum state of a lattice having a system of quasi-particles disposed thereon, moving the quasi-particles within the lattice, identifying a second quantum state of the lattice after the quasi-particles have been moved, and determining a computational result based on the second quantum state of the lattice.

Abstract: One-dimensional nanostructures having uniform diameters of less than approximately 200 nm. These inventive nanostructures, which we refer to as “nanowires”, include single-crystalline homostructures as well as heterostructures of at least two single-crystalline materials having different chemical compositions. Because single-crystalline materials are used to form the heterostructure, the resultant heterostructure will be single-crystalline as well. The nanowire heterostructures are generally based on a semiconducting wire wherein the doping and composition are controlled in either the longitudinal or radial directions, or in both directions, to yield a wire that comprises different materials. Examples of resulting nanowire heterostructures include a longitudinal heterostructure nanowire (LOHN) and a coaxial heterostructure nanowire (COHN).

Abstract: Apparatus and methods for performing quantum computations are disclosed. Such apparatus and methods may include identifying a first quantum state of a lattice having a system of quasi-particles disposed thereon, moving the quasi-particles within the lattice according to at least one predefined rule, identifying a second quantum state of the lattice after the quasi-particles have been moved, and determining a computational result based on the second quantum state of the lattice. Various platforms can be used to physically implement such a quantum computer. Platforms include an optical lattice, a Josephson junction array, a quantum dot, and a crystal structure. Each platform comprises an appropriate array of associated sites that can be used to approximate a desired Kagome geometry. A charge controller is desirably electrically coupled to the platform so that the array may be manipulated as desired.

Abstract: In a method of forming an electrically conductive lamination pattern, an insulating film is formed on a surface of a chromium-containing bottom layer, before an aluminum-containing top layer is formed over the insulating film, so that the insulating film separates the aluminum-containing top layer from the chromium-containing bottom layer. A first selective wet etching process is carried out for selectively etching the aluminum-containing top layer with a first etchant. A second selective wet etching process is carried out for selectively etching the chromium-containing bottom layer with a second etchant in the presence the insulating film which suppresses a hetero-metal-contact-potential-difference between the chromium-containing bottom layer and the aluminum-containing top layer during the second selective wet etching process.

Abstract: A method of producing a substrate that has a transfer crystalline layer transferred from a donor wafer onto a support. The transfer layer can include one or more foreign species to modify its properties. In the preferred embodiment an atomic species is implanted into a zone of the donor wafer that is substantially free of foreign species to form an embrittlement or weakened zone below a bonding face thereof, with the weakened zone and the bonding face delimiting a transfer layer to be transferred. The donor wafer is preferably then bonded at the level of its bonding face to a support. Stresses are then preferably applied to produce a cleavage in the region of the weakened zone to obtain a substrate that includes the support and the transfer layer. Foreign species are preferably diffused into the thickness of the transfer layer prior to implanbumtation or after cleavage to modify the properties of the transfer layer, preferably its electrical or optical properties.

Abstract: Apparatus and methods for performing quantum computations are disclosed. Such quantum computational systems may include quantum computers, quantum cryptography systems, quantum information processing systems, quantum storage media, and special purpose quantum simulators.

Abstract: Apparatus and methods for performing quantum computations are disclosed. Such apparatus and methods may include identifying a first quantum state of a lattice having a system of quasi-particles disposed thereon, moving the quasi-particles within the lattice according to at least one predefined rule, identifying a second quantum state of the lattice after the quasi-particles have been moved, and determining a computational result based on the second quantum state of the lattice. A topological quantum computer encodes information in the configurations of different braids. The computer physically weaves braids in the 2D+1 space-time of the lattice, and uses this braiding to carry out calculations. A pair of quasi-particles, such as non-abelian anyons, can be moved around each other in a braid-like path. The quasi-particles can be moved as a result of a magnetic or optical field being applied to them, for example.

Abstract: A semiconductor integrated circuit (IC) chip includes an IC chip body and a nano-structure-surface passivation film. The IC chip body has at least one surface. The nano-structure-surface passivation film is formed on the at least one surface. The nano-structure-surface passivation film including nano-particles and a carrier resin protects the IC chip body from encountering any external interference. The IC chip body further has a plurality of fingerprint sensing members for sensing a whole fingerprint or a partial fingerprint.

Abstract: Processes for producing copy protection for an integrated circuit are provided. To avoid unauthorized copying of an integrated circuit, an effective and reliable copy protection are provided. The process includes the steps of providing a substrate that has semiconductor structures on at least a first side of the substrate, providing a material for coating the substrate, and coating the substrate with a copy-protect layer. In one embodiment, the copy-protect layer is produced by applying a silicate glass by evaporation coating. Thus, an etching process that dissolves the copy-protect layer also attacks the substrate so that the semiconductor structures are at least partially destroyed.

Abstract: A tamper-resistant packaging approach protects non-volatile memory. According to an example embodiment of the present invention, an array of magnetic memory elements (130-132) in an integrated circuit (100) are protected from magnetic flux(122) by a package (106) including a magnet (120). Flux from the magnet is directed away from the magnetic memory elements by the package. When tampered with, such as by removal of a portion of the package for accessing the magnetic memory elements, the package allows the flux to reach some or all of the magnetic memory elements, which causes a change in a logic state thereof. With this approach, the magnetic memory elements are protected from tampering.

Abstract: Apparatus and methods for performing quantum computations are disclosed. Such apparatus and methods may include identifying a first quantum state of a lattice having a system of quasi-particles disposed thereon, moving the quasi-particles within the lattice according to at least one predefined rule, identifying a second quantum state of the lattice after the quasi-particles have been moved, and determining a computational result based on the second quantum state of the lattice.

Abstract: An electronic component includes a base insulative layer having a first surface and a second surface; an electronic device having a first surface and a second surface, and the electronic device being secured to the base insulative layer; an adhesive layer disposed between the first surface of the electronic device and the second surface of the base insulative layer; and a removable layer disposed between the first surface of the electronic device and the second surface of the base insulative layer. The base insulative layer secures to the electronic device through the removable layer. The removable layer is capable of releasing the base insulative layer from the electronic device. The removal may be done without damage to a predetermined part of the electronic component.

Abstract: The present disclosure relates to compositions and methods for the treatment of a disease, e.g., cancer or pathogenic infection, using a bioconjugated nanoparticle comprising a biocompatible quantum dot conjugated to a targeting moiety. The targeting moiety allows for the nanopaticle to bind to a cancer cell or pathogenic organism. The quantum dot, upon excitation by soft x-rays, emits electromagnetic radiation at a frequency of ultraviolet light, thereby allowing for the disruption of the DNA found in the cancer cell or pathogenic organism.

Abstract: An electronic component includes a base insulative layer having a first surface and a second surface; an electronic device having a first surface and a second surface, and the electronic device being secured to the base insulative layer; an adhesive layer disposed between the first surface of the electronic device and the second surface of the base insulative layer; and a removable layer disposed between the first surface of the electronic device and the second surface of the base insulative layer. The base insulative layer secures to the electronic device through the removable layer. The removable layer releases the base insulative layer from the electronic device at a sufficiently low temperature.

Abstract: A semiconductor chip comprises a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern. The pad-rearrangement pattern includes a bond pad disposed over at least a part of the cell region. Thus, with the embodiments of the present invention, the overall chip size can thereby be substantially reduced and an MCP can be fabricated without the problems mentioned above.

Abstract: Apparatus and methods for performing quantum computations are disclosed. Such apparatus and methods may include identifying a first quantum state of a lattice having a system of quasi-particles disposed thereon, moving the quasi-particles within the lattice according to at least one predefined rule, identifying a second quantum state of the lattice after the quasi-particles have been moved, and determining a computational result based on the second quantum state of the lattice.

Abstract: The ion beam irradiation apparatus has a vacuum chamber 10, an ion source 2, a substrate driving mechanism 30, rotation shafts 14, arms 12, and a motor. The ion source 2 is disposed inside the vacuum chamber 10, and emits an ion beam 4 which is larger in width than a substrate 6, to the substrate 6. The substrate driving mechanism 30 reciprocally drives the substrate 6 in the vacuum chamber 10. The center axes 14a of the rotation shafts 14 are located in a place separated from the ion source 2 toward the substrate, and substantially parallel to the surface of the substrate. The arms 12 are disposed inside the vacuum chamber 10, and support the ion source 2 through the rotation shafts 14. The motor is disposed outside the vacuum chamber 10, and reciprocally rotates the rotation shaft 14.

Abstract: A micromechanical component includes a cap wafer made up of at least a first silicon substrate and a thin glass substrate, and having a functional wafer made up of at least a second silicon substrate, at least one electrical contact surface being disposed on the functional wafer. the cap wafer is joined at the glass substrate to the functional wafer by anodic bonding. the electrical contact surface is disposed on a side of the functional wafer facing the cap wafer, and the cap wafer has at least one recess, such that an access is provided to the electrical contact surface. A method for encapsulating a micromechanical component having a cap wafer, by anodically bonding the cap wafer to a functional wafer.

Abstract: A semiconductor device has a heterostructure including a first layer of semiconductor oxide material. A second layer of semiconductor oxide material is formed on the first layer of semiconductor oxide material such that a two dimensional electron gas builds up at an interface between the first and second materials. A passivation layer on the outer surface stabilizes the structure. The device also has a source contact and a drain contact.

Abstract: A hybrid electronic circuit package (102, FIG. 1) includes non-insertable conductive features (110) and insertable conductive features (112) at a surface of the package. A hybrid receptacle (120), such as a socket, for example, includes non-insertable contacts (124) and insertable contacts (126), which are positioned in a complementary manner with the non-insertable and insertable features of the package. A vertical securement device (132, 134, 136) applies a vertical compressive force to the package (102) to compress the non-insertable features (110) against the non-insertable contacts (124). Further, a normal force securement device can be used to provide a sustained normal force to compress the insertable features and contacts together. In one embodiment, the non-insertable features are land grid array lands and the insertable features are low insertion force features.

Abstract: Techniques are disclosed to monitor the time of operation of a solid state lighting system, e.g. for warranty purposes. Examples are disclosed that measure time of system connection to power and/or time of light output from the solid state emitter(s) of the system. A service under the warranty is provided if operation time does not exceed the warranty eligibility criteria, e.g. maximum limit(s). The service provided under the warranty may be pro-rated based on the time of operation.

Abstract: The invention relates to a multilayer composite body having an electronic function, in particular an electronic subassembly comprising a plurality of organic electronic components. The invention provides, for the first time, a possibility for a structure of an entire subassembly such as an RFID tag, the entire tag with all of the components being able to be implemented in one production process.

Abstract: A wafer structure with mirror shot is provided. A wafer structure according to the present invention comprises a first mirror shot area to which a mirror shot is applied, wherein the position of a first die is searched for based on the first mirror shot area. The wafer structure further comprises a second mirror shot area to which the mirror shot is applied. The second mirror shot area is located diagonally with respect to the first mirror shot area.

Abstract: An electromechanical switching device employs a first nanoscale pillar shuttling charge between opposed charged electrodes. Motion of the first pillar is coupled to a second set of pillars providing controlled charge transfer between a second isolated set of electrodes. Standard logic elements may be constructed using this switching device.

Abstract: A microelectronic switch having a substrate layer, an electrically conductive switching layer formed on the substrate layer, an electrically conductive cavity layer formed on the switching layer, an electrically conductive cap layer formed on the cavity layer, the cap layer forming a first electrode and a second electrode that are physically and electrically separated one from another, and which both at least partially overlie the switching layer, and a cavity disposed between the switching layer and the second electrode, where the switching is layer is flexible to make electrical contact with the second electrode by flexing through the cavity upon selective application of an electrical bias.

Abstract: The present invention provides an apparatus comprising a device and a mechanism for heat transfer comprising a hydrofluoroether heat-transfer fluid wherein the heat transfer fluid is represented by the following structure: Rf—O—Rh—O—Rf? wherein O is oxygen; Rf and Rf? are, independently, a fluoroaliphatic group, wherein each Rf and Rf? contain 1 hydrogen atom; Rh is independently a linear, branched or cyclic alkylene group having from 2 to about 8 carbon atoms and at least 4 hydrogen atoms, and wherein the hydrofluoroether compound is free of —O—CH2—O—. Another embodiment of the present invention is a method therefor.

Abstract: An electronic device, such as a thin film transistor, containing a semiconductor of Formula/Structure (I) wherein each R? is independently at least one of hydrogen, and a suitable hydrocarbon; Ar is an aryl, inclusive of heteroaryl substituents; and M represents at least one thiophene based conjugated segment.

Abstract: This is a method for creating Bose-Einstein condensates using low-cost technology at room temperature. The method includes a convenient way for separating the condensate into parts that remain entangled and storing the parts in reliable and stable containers that are suitable for easy transportation. The containers have a convenient method to monitor changes in the state of the condensate.

Abstract: Complementary metal oxide semiconductor (CMOS) static random access memory (SRAM) cells include at least a first inverter formed in a fin-shaped pattern of stacked semiconductor regions of opposite conductivity type. In some of these embodiments, the first inverter includes a first conductivity type (e.g., P-type or N-type) MOS load transistor electrically coupled in series with a second conductivity type (e.g., N-type of P-type) MOS driver transistor. The first inverter is arranged so that active regions of the first conductivity type MOS load transistor and the second conductivity type driver transistor are vertically stacked relative to each other within a first portion of a vertical dual-conductivity semiconductor fin structure. This fin structure is surrounded on at least three sides by a wraparound gate electrode, which is configured to modulate conductivity of both the active regions in response to a gate signal.

Abstract: The present invention relates to a method for producing a structure serving as an etching mask on the surface of a substrate. In this case, a first method involves forming a first partial structure on the surface of the substrate, which has structure elements that are arranged regularly and are spaced apart essentially identically. A second method involves forming spacers on the surface of the substrate, which adjoin sidewalls of the structure elements of the first partial structure, cutouts being provided between the spacers. A third method step involves introducing filling material into the cutouts between the spacers, a surface of the spacers being uncovered. A fourth method step involves removing the spacers in order to form a second partial structure having the filling material and having structure elements that are arranged regularly and are spaced apart essentially identically. The structure to be produced is composed of the first partial structure and the second partial structure.

Abstract: A striped tape carrier for TAB includes a plurality of mounting parts. In the respective mounting parts, wiring patterns to bond electrodes of electronic components are formed. Each of exposure regions includes a predetermined number of mounting parts. On both sides of each of the exposure regions, alignment marks and identification marks are formed. The alignment marks are used for alignment during the exposure. The identification marks are used for specifying positions of the respective exposure regions on the tape carrier.

Abstract: The present invention relates to a heat-resistant dicing tape or sheet, which includes a substrate having a glass transition temperature of 70° C. or higher; and at least one pressure-sensitive adhesive layer disposed on at least one side of the substrate, the pressure-sensitive adhesive layer having a degree of weight loss upon heating of less than 2% when the pressure-sensitive adhesive layer is heated from room temperature to 200° C. at a rate of temperature increase of 2° C./min, in which the pressure-sensitive adhesive layer has an adhesive force (peel rate: 300 mm/min; peel angle: 180°) of 0.5 N/20 mm or lower when the heat-resistant dicing tape or sheet is applied to a silicon mirror wafer, is subsequently heated at 200° C. for 30 seconds, and is then cooled to 23° C.

Abstract: The present invention provides a method of manufacturing a bonded wafer. When bonding the top wafer through an insulating film exceeding about 1,000 Angstroms in thickness to the base wafer, a top wafer and a base wafer in which the total number of particles having a size of equal to or greater than about 0.20 micrometers present on the two surfaces being bonded is equal to or less than about 0.014 particles/cm2 are bonded; and when bonding the top wafer through an insulating film having a thickness of equal to or less than about 1,000 Angstroms to the base wafer, or with no insulating film present between the top wafer and the base wafer, a top wafer and a base wafer are bonded wherein the total number of particles having a size of equal to or greater than about 0.20 micrometers present on the two surfaces being bonded is equal to or less than about 0.007 particles/cm2.

Abstract: A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the dielectric material layer and solder materials, and the first and second copper layers are patterned to form a plurality of conductive traces each of which has a terminal coated with a metal layer. A chip is mounted on the conductive traces and electrically connected to the terminals by bonding wires, with the dielectric material layer and solder materials being exposed to the outside. This package structure can flexibly arrange the conductive traces and effectively shorten the bonding wires, thereby improve trace routability and quality of electrical connection for the semiconductor package.

Abstract: Elongated solder masses are formed by contacting the molten solder with the walls of holes in a dielectric layer overlying the front face of a chip element such as a wafer. The elongated solder masses have a relatively large aspect ratio, or ratio of height to maximum diameter, and thus provide a high reliability connection with a relatively small diameter compatible with closely spaced contacts on the chip.

Abstract: A semiconductor device includes a first insulation layer including a first conductor pattern, a second insulation layer formed on the first insulation layer and including a second conductor pattern, and a third conductor pattern formed on the second insulation layer, wherein there is formed a first alignment mark part in the first insulation layer by a part of the first conductor pattern, the third conductor pattern is formed with a second alignment mark part corresponding to the first alignment mark part, the first and second alignment marks forming a mark pair for detecting alignment of the first conductor pattern and the third conductor pattern, the second conductor pattern being formed in the second insulation layer so as to avoid the first alignment mark part.

Abstract: The electronic device includes a plurality of layout regions each including a plurality of patterns defined by a buried structure buried in a substrate. For each of the layout regions, in each of the layout regions, the minimum space between the patterns, and a maximum area percentage allowed for the patterns in the layout region are defined based on a size of the layout region. In larger one of the layout regions, the minimum space between the patterns in the region is set larger.