Abstract: A MOSFET capable of achieving decrease in the number of steps in a manufacturing process and improvement in integration includes an SiC wafer composed of silicon carbide and a source contact electrode arranged in contact with the SiC wafer and containing titanium, aluminum, silicon, and carbon as well as a remaining inevitable impurity. The SiC wafer includes an n+ source region having an n conductivity type and a p+ region having a p conductivity type. Both of the n+ source region and the p+ region are in contact with the source contact electrode. The source contact electrode contains aluminum and titanium in a region including an interface with the SiC wafer.

Abstract: A semiconductor device having the present high withstand voltage power device IGBT has at a back surface a p collector layer with boron injected in an amount of approximately 3×1013/cm2 with an energy of approximately 50 KeV to a depth of approximately 0.5 ?m, and an n+ buffer layer with phosphorus injected in an amount of approximately 3×1012/cm2 with an energy of 120 KeV to a depth of approximately 20 ?m. To control lifetime, a semiconductor substrate is exposed to protons at the back surface. Optimally, it is exposed to protons at a dose of approximately 1×1011/cm2 to a depth of approximately 32 ?m as measured from the back surface. Thus snapback phenomenon can be eliminated and an improved low saturation voltage (Vce (sat))-offset voltage (Eoff) tradeoff can be achieved.

Abstract: A trench IGBT is disclosed. One embodiment includes an embedded structure arranged above a collector region and selected from a group consisting of a porous semiconductor region, a cavity, and a semiconductor region including additional scattering centers for holes, the embedded structure being arranged below the body contact region such that the embedded structure and the body contact region overlap in a horizontal projection.

Abstract: A semiconductor device includes first semiconductor zones of a first conductivity type having a first dopant species of the first conductivity type and a second dopant species of a second conductivity type different from the first conductivity type. The semiconductor device also includes second semiconductor zones of the second conductivity type including the second dopant species. The first and second semiconductor zones are alternately arranged in contact with each other along a lateral direction extending in parallel to a surface of a semiconductor body. One of the first and second semiconductor zones constitute drift zones and a diffusion coefficient of the second dopant species is at least twice as large as the diffusion coefficient of the first dopant species. A concentration profile of the first dopant species along a vertical direction perpendicular to the surface of the semiconductor body includes at least two maxima.

Abstract: A method of forming an IC includes forming a first and a second gate portion using a poly mask. The first portion includes a first active poly gate having a line width W1 over an end of a first active area framed by a first active area edge and a first adjacent active field poly feature having a line width 0.8W1 to 1.3W1 in a first field region. The first field poly feature has a horizontal portion and a first extension portion along a gate width direction extending over the first active area edge having a first minimum spacing (S1). The second gate portion includes a second active poly gate over an end of a second active area framed by a second active area edge electrically connected to a second field poly feature in a second field region having a horizontal portion and a second extension portion along a gate width direction extending over the second active area edge having a second minimum spacing (S2). A dummy field poly feature is between the second active poly gate and the second field poly feature.

Abstract: Aimed at providing a highly reliable semiconductor device appropriately increased in stress at the channel region so as to improve carrier injection rate, thereby dramatically improved in transistor characteristics, and made adaptable also to recent narrower channel width, and a method of manufacturing the same, and a method of manufacturing the same, a first sidewall composed of a stress film having expandability is formed on the side faces of a gate electrode, a second sidewall composed of a film having smaller stress is formed on the first sidewall, and a semiconductor, which is a SiC layer for example, is formed as being positioned apart from the first sidewall while placing the second sidewall in between.

Abstract: A semiconductor device includes a first MIS transistor, and a second MIS transistor having a threshold voltage higher than that of the first MIS transistor. The first MIS transistor includes a first gate insulating film made of a high-k insulating film formed on a first channel region, and a first gate electrode having a first conductive portion provided on and contacting the first gate insulating film and a second conductive portion. The second MIS transistor includes a second gate insulating film made of the high-k insulating film formed on a second channel region, and a second gate electrode having a third conductive portion provided on and contacting the second gate insulating film and a fourth conductive portion. The third conductive portion has a film thickness smaller than that of the first conductive portion, and is made of the same composition material as that of the first conductive portion.

Abstract: In a vertical power semiconductor device having the super junction structure both in a device section and a terminal section, an n-type impurity layer is formed on the outer peripheral surface in the super junction structure. This allows an electric field on the outer peripheral surface of the super junction structure region to be reduced. Accordingly, a reliable vertical power semiconductor device of a high withstand voltage can be provided.

Abstract: A bipolar semiconductor device with a hole current redistributing structure and an n-channel IGBT are provided. The n-channel IGBT has a p-doped body region with a first hole mobility and a sub region which is completely embedded within the body region and has a second hole mobility which is lower than the first hole mobility. Further, a method for forming a bipolar semiconductor device is provided.

Abstract: A semiconductor device having the present high withstand voltage power device IGBT has at a back surface a p collector layer with boron injected in an amount of approximately 3×1013/cm2 with an energy of approximately 50 KeV to a depth of approximately 0.5 ?m, and an n+ buffer layer with phosphorus injected in an amount of approximately 3×1012/cm2 with an energy of 120 KeV to a depth of approximately 20 ?m. To control lifetime, a semiconductor substrate is exposed to protons at the back surface. Optimally, it is exposed to protons at a dose of approximately 1×1011/cm2 to a depth of approximately 32 ?m as measured from the back surface. Thus snapback phenomenon can be eliminated and an improved low saturation voltage (Vce (sat))-offset voltage (Eoff) tradeoff can be achieved.

Abstract: A method of producing a semiconducting device is provided that in one embodiment includes providing a semiconducting device including a gate structure atop a substrate, the gate structure including a dual gate conductor including an upper gate conductor and a lower gate conductor, wherein at least the lower gate conductor includes a silicon containing material; removing the upper gate conductor selective to the lower gate conductor; depositing a metal on at least the lower gate conductor; and producing a silicide from the metal and the lower gate conductor. In another embodiment, the inventive method includes a metal as the lower gate conductor.

Abstract: A semiconductor integrated circuit device which is improved in wiring efficiency and area efficiency. Metal layers having respective portions protruding out from an N-type diffusion layer and a P-type diffusion layer in plan view toward respective sides of the diffusion layers opposed to each other are formed over the N-type diffusion layer and the P-type diffusion layer, respectively, and contact portions are formed over the upper surfaces of the protruding portions of the metal layers such that they extend parallel to a power supply line and a ground voltage line. This produces empty spaces over the regions of the upper surfaces of the metal layers, which makes it possible to arrange a large number of conductive traces, and enhance wiring efficiency and space efficiency.

Abstract: A method and system of fractional biasing of semiconductors. A small negative voltage is applied to the back of a semiconductor wafer or device. An operating voltage is applied to the semiconductor. Operating characteristics of the semiconductor are enhanced by application of a fractional bias.

Abstract: A semiconductor device which is suitable for miniaturization, capable of improving variations in characteristics of a transistor and enhancing the current driving capability comprises a semiconductor substrate, an isolation protruding from the semiconductor substrate and having a width above the semiconductor substrate narrower than a width in the semiconductor substrate, a semiconductor layer formed on the semiconductor substrate portion between the isolations, and a MOSFET formed on the semiconductor layer.

Abstract: A trench power semiconductor device including a recessed termination structure.

Abstract: An integrated circuit device including a plurality of MOSFETs of similar type and geometry is formed on a substrate with an ohmic contact, and an adjustable voltage source on the die utilizing clearable fuses is coupled between the ohmic contact and the sources of the MOSFETs. After die processing, a post-processing test is performed to measure an operating characteristic of the die such as leakage current or switching speed, and an external voltage source is applied and adjusted to control the operating characteristic. The on-die fuses are then cleared to adjust the on-die voltage source to match the externally applied voltage. The operating characteristic may be determined by including a test circuit on the die to exhibit the operating characteristic such as a ring oscillator frequency. This approach to controlling manufacturing-induced device performance variations is well suited to efficient manufacture of small feature-size circuits such as DRAMs.

Abstract: A static memory device includes at least one memory cell with two cross-coupled CMOS inverters to be connected to first and second voltages. The substrate of the NMOS transistor of a first CMOS inverter is electrically insulated from the substrate of the NMOS transistor of the second CMOS inverter. The two substrates can be biased with the first voltage. A clear flash controller flash clears the cells for temporarily bring the bias of the substrate of the NMOS transistor of the first CMOS inverter to the second voltage.

Abstract: A power MOS transistor formed of an array of source cells and drain cells on an IC chip substrate has a plurality of substrate contact cells, each formed external to the source cells, having respective substrate potential-setting electrodes to which an externally supplied substrate bias voltage can be applied, enabling the substrate potential to be set independently of the source potential of the transistor. It thereby becomes possible to modify the threshold voltage of the transistor or maintain a constant potential difference between the substrate potential and that of a gate input signal. Since the requirement for a substrate contact region within each source cell is eliminated, and the number of substrate contact cells can be fewer than that of the source cells, the chip area occupied by the transistor can be reduced by comparison with a prior art configuration providing such a substrate potential control capability.

Abstract: The present invention provides a threshold voltage stabilizer for use with a MOS transistor having a body effect associated therewith. In one embodiment, the threshold voltage stabilizer, includes a body well located in a substrate, a source located in the body well, and a stabilization region positioned below the body well. The threshold voltage stabilizer is configured to provide a stabilization voltage to the stabilization region to increase a depletion region within the body well and thereby restrict the body effect to stabilize a threshold voltage of the MOS transistor.

Abstract: A semiconductor module includes a supporting substrate having a connecting section on a first major surface thereof. A first semiconductor chip includes a first MIS transistor a source of which is formed on the bottom thereof. A second semiconductor chip includes a second MIS transistor a drain of which is formed on the bottom thereof. The first and second semiconductor chips are on the supporting substrate such that the source of the first MIS transistor and the drain of the second MIS transistor are connected to the connecting section and connected each other through the connecting section. An IC chip is provided on the first major surface and connected to gates of the first and second MIS transistors. An insulative envelope covers the supporting substrate, first and second semiconductor chips and IC chip. Partly exposed connecting terminals are electrically connected to the connecting section and first and second semiconductor chips.

Abstract: A semiconductor integrated circuit device has a MISFET and a body biasing circuit. The MISFET has a source electrode and a drain electrode of a first conductivity type and a gate electrode, and the MISFET is formed in a well of a second conductivity type. The body biasing circuit generates a voltage in the well by passing a prescribed current in a forward direction into a diode which is formed from the well and the source electrode of the MISFET.

Abstract: A method and apparatus for providing a weak inversion mode metal-oxide-semiconductor (MOS) decoupling capacitor is described. In one embodiment, an enhancement-mode p-channel MOS (PMOS) transistor is constructed with a gate material whose work function differs from that commonly used. In one exemplary embodiment, platinum silicate (PtSi) is used. In alternate embodiments, the threshold voltage of the PMOS transistor may be changed by modifying the dopant levels of the substrate. In either embodiment the flat band magnitude of the transistor is shifted by the change in materials used to construct the transistor. When such a transistor is connected with the gate lead connected to the positive supply voltage and the other leads connected to the negative (ground) supply voltage, an improved decoupling capacitor results.

Abstract: A nonvolatile reprogrammable switch for use in a PLD or FPGA has a nonvolatile memory cell connected to the gate of an MOS transistor, which is in a well, with the terminals of the MOS transistor connected to the source of the signal and to the circuit. The nonvolatile memory cell is of a split gate type having a first region and a second region, with a channel therebetween. The cell has a floating gate positioned over a first portion of the channel, which is adjacent to the first region and a control gate positioned over a second portion of the channel, which is adjacent to the second region. The second region is connected to the gate of the MOS transistor. The cell is programmed by injecting electrons from the channel onto the floating gate by hot electron injection mechanism. The cell is erased by Fowler-Nordheim tunneling of the electrons from the floating gate to the control gate. As a result, no high voltage is ever applied to the second region during program or erase.

Abstract: In a semiconductor device in which the gate electrode of a MISFET formed on a semiconductor substrate is electrically connected to a well region under the channel of the MISFET, the MISFET is formed in an island-shaped element region formed on the semiconductor substrate, and electrical connection between the gate electrode of the MISFET and the well region in the semiconductor substrate is done on the side surface of the island-shaped element region.

Abstract: A voltage applying section (32) is connected to a silicon substrate (1). Emission of radiation to a semiconductor device causes a large number of holes to accumulate within a BOX layer (2) in the vicinity of the interface with respect to a silicon layer (3). The amount of accumulation of holes increases with a lapse of time. A voltage applying section (32) applies a negative voltage which decreases with the lapse of time to the silicon substrate (1) in order to cancel out a positive electric field resulting from the accumulated holes. The voltage applying section (32) includes a time counter (30) for detecting the lapse of time and a voltage generating section (31) connected to the silicon substrate (1) for generating a negative voltage (V1) which decreases in proportion to the lapse of time based on the result of detection (time T) carried out by the time counter (30). Consequently, a semiconductor device capable of suppressing occurrence of total dose effects is obtained.

Abstract: A semiconductor device includes an insulating film provided on a semiconductor substrate and a semiconductor layer provided on the insulating film. An element separating insulating film separates element area. A first gate insulating film is provided on the semiconductor layer in the element area. A gate electrode is provided on the first gate insulating film. Source/drain diffusion layers are formed in the semiconductor layer sandwiching a channel area under the gate electrode therebetween. A potential applying section inducing a leak current which controls the potential of the semiconductor layer comprises a second gate insulating film provided on the semiconductor layer in the element area and a conductive film provided on the second gate insulating film and connected to the gate electrode. The potential applying section is configured so that a leak current through the second gate insulating film is larger than a leak current through the first gate insulating film.

Abstract: In a semiconductor device in which the gate electrode of a MISFET formed on a semiconductor substrate is electrically connected to a well region under the channel of the MISFET, the MISFET is formed in an island-shaped element region formed on the semiconductor substrate, and electrical connection between the gate electrode of the MISFET and the well region in the semiconductor substrate is done on the side surface of the island-shaped element region.

Abstract: A silicon substrate comprises a silicon-on-insulator (SOI) portion which includes an insulating silicon dioxide layer beneath a device layer. SOI circuit structures, including SOI field effect transistors, are formed in the device layer. The substrate also comprises a bulk portion. Bulk semiconductor circuit structures are formed in wells in the bulk portion. The bulk circuit structures may be coupled to the SOI circuit structures.

Abstract: A MOSFET die and a Schottky diode die are mounted on a common lead frame pad and their drain and cathode, respectively, are connected together at the pad. The pad has a plurality of pins extending from one side thereof. The lead frame has insulated pins on its opposite side which are connected to the FET source, the FET gate and the Schottky diode anode respectively by wire bonds. The lead frame and die are molded in an insulated housing and the lead frame pins are bent downwardly to define a surface-mount package.

Abstract: A water flow timer including a main body, a water stopping membrane, a control rod, a bottom cover, a control member, a rotating member, a timing member, and a rotary cap. The timer is mechanically operated in such a way that the rotary cap is turned to actuate the control member to force the control rod to slide, thereby resulting in a gap between the water stopping membrane and a bottom opening of an inner chamber of the main body. The inner and the outer chamber of the main body are thus in communication with each other. As the rotary cap is turned, the torsion spring of the timing member is compressed to provide the rotary cap with a recovery force. The recovery of the rotary cap is delayed by an intermittent gear, so as to control the timing of the water flow.

Abstract: A method of forming a silicon on insulator (SOI) body contact at a pair of field effect transistors (FETs), a sense amplifier including a balanced pair of such FETs and a RAM including the sense amplifiers. A pair of gates are formed on a SOI silicon surface layer. A dielectric bridge is formed between a pair of gates when sidewall spacers are formed along the gates. Source/drain (S/D) conduction regions are formed in the SOI surface layer adjacent the sidewalls at the pair of gates. The dielectric bridge blocks selectively formation of S/D conduction regions. A passivating layer is formed over the pair of gates and the dielectric bridge. Contacts are opened partially through the passivation layer. Then, a body contact is opened through the bridge to SOI surface layer and a body contact diffusion is formed. Contact openings are completed through the passivation layer at the S/D diffusions. Tungsten studs are formed in the contact openings.

Abstract: A lateral conduction MOS structure characterized by reduced source resistance and reduced pitch. The structure includes a semiconductor substrate having an epitaxial semiconductor layer thereon, the substrate and epitaxial layer being of the same conductivity type. The structure further includes a source layer and a drain layer, each layer being of a second conductivity type, and a channel layer disposed between the source layer and the drain layer. The channel layer has an oxide layer and a gate disposed thereon. At least one of a wet anisotropic and a reactive ion etching step is performed to define a trench having a maximum width of about from 4-6 microns and a depth that extends well into the substrate. An electrically conductive via is then formed by deposition of metal into the trench to thereby establish a low resistance path between the source and the substrate ground.

Abstract: A MOSFET die and a Schottky diode die are mounted on a common lead frame pad and their drain and cathode, respectively, are connected together at the pad. The pad has a plurality of pins extending from one side thereof. The lead frame has insulated pins on its opposite side which are connected to the FET source, the FET gate and the Schottky diode anode respectively by wire bonds. The lead frame and die are molded in an insulated housing and the lead frame pins are bent downwardly to define a surface-mount package.

Abstract: A body contact to a SOI device is created by providing a deeper buried oxide region for providing connection to the FET body.

Abstract: A semiconductor circuit device having a triple-well structure wherein a predetermined potential level is supplied to a top well without a contact region formed in the top well is disclosed. In an N-type ion implantation step for forming an N-type well region (1) in a P-type semiconductor substrate (5), a mask of a predetermined configuration is used so that ions are not implanted into a region of a portion which is to serve as a bottom portion (1B) of the well region (1). Then, the N-type well region (1) is formed which is shaped such that a portion (6) having P-type properties remains partially in the bottom portion (1B). The P-type portion (6) establishes electrical connection between a P-type well region (2) and the semiconductor substrate (5) to permit the potential applied to a contact region (4) to be supplied to the well region (2) therethrough. The portion (6) may include a plurality of portions (6) which allow uniform potential supply.

Abstract: An output circuit for an integrated circuit, includes a first transistor and a second transistor connected in series between a first external voltage and a second external voltage external to the integrated circuit, respectively through first and second electrical connecting paths. The first transistor is for carrying an output line of the integrated circuit to the first external voltage, while the second transistor is for carrying the external line of the integrated circuit to the second external voltage. The second transistor is formed inside a first well of a first conductivity type contained inside a second well of a second conductivity type formed in a substrate of the first conductivity type. The second well of the second conductivity type is connected to the first external voltage through a third electrical connecting path distinct from the first electrical connecting path.

Abstract: A MOSFET die and a Schottky diode die are mounted on a common lead frame pad and their drain and cathode, respectively, are connected together at the pad. The pad has a plurality of pins extending from one side thereof. The lead frame has insulated pins on its opposite side which are connected to the FET source, the FET gate and the Schottky diode anode respectively by wire bonds. The lead frame and die are molded in an insulated housing and the lead frame pins are bent downwardly to define a surface-mount package.

Abstract: In an integrated semiconductor device formed on an SOI substrate, first and second switches are switched at a predetermined cycle in a standby mode period to apply a boosted potential Vpp and a negative potential Vbb to the source of a p channel MOS transistor and an n channel MOS transistor, respectively, of a row of inverters. The charge stored in the body region of the MOS transistor is discharged to prevent reduction of the body potential of the MOS transistor and increase of the body potential of the MOS transistor to lower subthreshold leakage current. The layout area is reduced comparable to the case where the body potential is fixed by a contact region.

Abstract: A semiconductor device capable of solving a problem of a conventional semiconductor device in that a high density integration cannot be expected because each cell, which includes a pair of N and P wells disposed adjacently, requires a countermeasure against latchup individually. The high density integration prevents an effective countermeasure against latchup. The present semiconductor device arranges two cells, which are adjacent in the direction of an alignment of the N wells and P wells, in opposite directions so that two P wells (or two N wells) of the two adjacent cells are disposed successively, and includes an isolation layer extending across the two adjacent cells to enclose the two successively disposed P wells, thereby isolating the two P wells collectively from the substrate.

Abstract: Integrated circuit memory devices include a semiconductor substrate of first conductivity type (e.g., P-type), a first well region of second conductivity type (e.g., N-type) in the substrate and first and second nonoverlapping sub-well regions of first conductivity type in the first well region. To improve the electrical characteristics of circuits within the memory device, a first semiconductor device is provided in the first sub-well region (which is biased at a back-bias potential (Vbb)) and a second semiconductor device is provided in the second sub-well region (which is biased at a ground or negative supply potential (Vss)). The first semiconductor device is preferably selected from the group consisting of memory cell access transistors, equalization circuits and isolation gates. The second semiconductor device is also preferably selected from the group consisting of column select circuits and sense amplifiers.

Abstract: Disclosed is a semiconductor device having a silicon on insulator structure capable of achieving a high integration, and a manufacturing method of the same. The semiconductor device includes a semiconductor substrate having a silicon on insulator structure, in which a insulating layer and a semiconductor layer are formed on a semiconductor wafer in sequence. A gate insulating film and a gate are formed on the semiconductor layer. A first impurity diffusion region and a second impurity diffusion region are formed in the semiconductor layer at both sides of the gate. A intermediate insulating layer having a first contact hole for exposing a predetermined portion of the first impurity diffusion region and a second contact hole for exposing a predetermined portion of the second impurity diffusion region and a predetermined portion of the wafer, is formed on an overall surface of the substrate.

Abstract: A fully depleted SOI device includes a semiconductor substrate and a conductive well of a first conductivity type formed in a principal surface of the semiconductor substrate. An insulating layer is formed along the principal surface of the semiconductor substrate and extends across the conductive well. A transistor is formed on the insulating layer such that the insulating layer is interposed between the transistor and the semiconductor substrate, with the transistor including source and drain regions of the first conductivity type formed on the insulating layer, a channel region of a second conductivity type formed on the insulating layer and aligned over the conductive well, and a gate electrode aligned over the channel region. A metal contact is connected to the conductive well for applying a reverse bias potential to the transistor.

Abstract: The present invention provides an integrated circuit chip having one or more circuit elements that perform a desired circuit function with the circuit elements being encompassed by a molding compound that forms a package for the chip. The molding compound has a capacitance associated with it. The integrated circuit chip includes a second integrated circuit element within the molding compound in which the second integrated circuit element monitors the molding compound to detect a change in capacitance in the molding compound resulting from a removal of a portion or all of the molding compound. In response to a detection of a change in capacitance, the second integrated circuit element alters the desired circuit function provided by the other integrated circuit elements.

Abstract: An improved body contact structure for a semiconductor device which is capable of forming a contact portion by using less surface area, obtaining a constant contact surface ratio between a source region and a body contact diffusion layer even when a contact is misaligned, and preventing the activation of a parasitic device, whereby it is possible to enable a stable operation of the device. The body contact structure for a semiconductor device includes a conductive substrate, first and second parallel conductive source regions, a bar-shaped conductive body contact diffusion layer formed in an extended source region and split by the extended source region into multiple portions, and cubic-shaped contact wiring metal layers formed so that each body contact diffusion layer portion is connected with a neighboring body contact diffusion layer portion and the extended source region formed between the neighboring body contact diffusion layer portions.

Abstract: A semiconductor device includes a PMOS transistor and an NMOS transistor. In a standby state, a potential of Vcc level is applied to the substrate of the PMOS transistor and a potential of Vss level is applied to the substrate of the NMOS transistor. Therefore, the voltage between the source and substrate of the P and NMOS transistors becomes 0 V. In an active state, potentials that render the voltage between the source and substrate lower than the built-in potential are applied to respective substrates of the P and NMOS transistors. Therefore, the threshold voltage of the transistor is lowered in an active state than in a standby state, and almost no leakage current flows between the source and substrate.

Abstract: A least one one-time programmable nonvolatile (NV) memory element uses a field-effect transistor (FET) as a selectively programmed element. A short duration applied drain voltage exceeding the FET's drain-to-source breakdown voltage results in a drain source resistance which is substantially unaffected by the voltages typically applied at the gate terminal. Since the programmed resistance is less than 200 ohms and a high programming voltage is not required, the present invention compares favorably with antifuse nonvolatile memory techniques. The nonvolatile memory element is implemented without adding complexity to a very large scale integrated (VLSI) circuit process.

Abstract: An RF switch comprises a switching FET having gate and back gate terminals, an input port for receiving an RF signal, and an output port for providing substantially the RF signal during an ON state of the FET. Switching circuitry connects the back gate terminal of the FET to the input port during the ON state to reduce insertion loss during the ON state, and connects the back gate terminal to a point of reference potential during an OFF state of the FET to increase isolation during the OFF state. Preferably, the switching FET is a depletion mode silicon MOSFET capable of operating with low supply voltages. The switching circuitry preferably comprises a second FET for electrically connecting the back gate terminal and the input terminal (e.g., source) of the switching FET during the ON state, and a third FET for electrically connecting the back gate terminal of the switching FET to the point of reference potential during the OFF state.

Abstract: A MOSFET die and a Schottky diode die are mounted on a common lead frame pad and their drain and cathode, respectively, are connected together at the pad. The pad has a plurality of pins extending from one side thereof. The lead frame has insulated pins on its opposite side which are connected to the FET source, the FET gate and the Schottky diode anode respectively by wire bonds. The lead frame and die are molded in an insulated housing and the lead frame pins are bent downwardly to define a surface-mount package.

Abstract: In an SOI-type semiconductor device, a power supply voltage is applied to back gates of P-channel MOS transistors in a standby mode, and a voltage lower than the power supply voltage is applied to the back gates of the P-channel MOS transistors in an active mode. A ground voltage is applied to back gates of N-channel MOS transistors in the standby mode, and a voltage higher than the ground voltage is applied to the back gates of the N-channel MOS transistors in an active mode.

Abstract: An AC power controller includes at least two semiconductor regions reverse-connected in series. Each semiconductor region has an electron donor (source), an electron sink (drain) and an electron flow control electrode (gate) with characteristic curves such as those exhibited by FETs. Each semiconductor region also has an internal body diode. The gate-source voltage of a respective semiconductor region in the forward direction is set to be large enough to establish a desired limiting of the drain-source current. Yet, the gate-source voltage of the semiconductor region in the inverse mode is set to be large enough for the body diode to remain de-energized.