Abstract: Embodiments of the present invention provide an array substrate, a manufacturing method thereof and a display device. The manufacturing method of an array substrate, comprising: forming a gate electrode on a base substrate by a first patterning process, and then depositing a gate insulating layer on the base substrate on which the gate electrode is formed; forming source and drain electrodes on the base substrate obtained after the above step, by a second patterning process; forming an active layer formed of a graphene layer, and a protective layer disposed on the active layer, on the base substrate obtained after the above steps, by a third patterning process; and forming a planarizing layer on the base substrate, obtained after the above steps, by a fourth patterning process, in which the planarizing layer is provided with a through hole through which the source or drain electrode is exposed.

Abstract: A method of detecting the circular uniformity of semiconductor circular contact holes. Several detection circuit structures are disposed on the semiconductor wafer: N-type active regions and P-type active regions; silicon dioxide layers separate the N-type active regions from the P-type active regions; the N-type active regions are formed in the P well and the P-type active regions are formed in the N well; polysilicon gates bridge the N-type active regions and the P-type active regions; gate oxide layers insulate the P-type regions and the N-type regions from the polysilicon gates, so that the P-type regions and the N-type regions are independent; the N-type active regions connect with circular contact holes while the P-type active regions and the polysilicon gates connect with oval contact holes; a electron beam scanner detects the circular uniformity of the contact holes. This invention advantageously reflects effectively and comprehensively the circular uniformity of the contact holes.

Abstract: There is disclosed a photo-detector array including a plurality of sub-arrays of photo-detectors, the photo-detectors of each sub-array being formed on a substrate with an active area of each photo-detector being formed on a surface of the substrate, there further being formed for each photo-detector a conductive via through the substrate from an upper surface thereof to a lower surface thereof to connect the active area of each photo-detector to the lower surface of the substrate, wherein a plurality of said sub-arrays of photo-detectors are placed adjacent to each other in a matrix to form the photo-detector array. An imaging system comprising: a radiation detector including such a photo detector array, a radiation source facing the radiation detector, and means for controlling the radiation detector and the radiation source is also disclosed. A method for making such an array is also disclosed.

Abstract: A light-emitting element array with the improvement of the light-emitting efficiency and the improvement of the uneven amount of light is provided. A light-emitting element array comprises a light-emitting portion array consisting of a plurality of light-emitting portions linearly arranged in a main scanning direction, and a micro-lens formed on each of the light-emitting portions, wherein the micro-lens has a shape of the length of a sub-scanning direction different from the length of the main scanning direction, and the length of the sub-scanning direction is longer than the length of the main scanning direction, and is 3.5 times or less of the length of the main scanning direction.

Abstract: Image sensing devices and methods for fabricating the same are provided. An exemplary image sensing device includes a first substrate having a first side and a second side opposing each other. A plurality of image sensing elements is formed in the first substrate at the first side. A conductive via is formed through the first substrate, having a first surface exposed by the first substrate at the first side and a second surface exposed by the first substrate at the second side. A conductive pad overlies the conductive via at the first side and is electrically connecting the image sensing elements. A conductive layer overlies the conductive via at the second side and electrically connects with the conductive pad. A conductive bump is formed over a portion of the conductive layer. A second substrate is bonded with the first substrate at the first side.

Abstract: A thin film transistor display includes a driving circuit and an active matrix. The driving circuit comprises a first thin film transistor structure. The first thin film transistor structure includes a first gate, source and drain regions, a first LDD region, a second LDD region and a first channel region between the first and the second LDD regions. The first gate region is disposed over the first channel region, and partially or completely overlies the first and the second LDD regions. The active matrix is controlled by the driving circuit and comprises a second thin film transistor structure. The second thin film transistor structure includes a second gate, source and drain regions, a third LDD region, a fourth LDD region and a second channel region between the third and the fourth LDD regions. The second gate region is disposed over the second channel region and substantially overlaps with neither of the first and the second LDD regions.

Abstract: In an active matrix type light emitting device, a top surface exit type light emitting device in which an anode formed at an upper portion of an organic compound layer becomes a light exit electrode is provided. In a light emitting element made of a cathode, an organic compound layer and an anode, a protection film is formed in an interface between the anode that is a light exit electrode and the organic compound layer. The protection film formed on the organic compound layer has transmittance in the range of 70 to 100%, and when the anode is deposited by use of the sputtering method, a sputtering damage to the organic compound layer can be inhibited from being inflicted.

Abstract: A new test structure to locate bridging defects in a conductive layer of an integrated circuit device is achieved. The test structure comprises a line comprising a conductive layer overlying a substrate. The line is coupled to ground. A plurality of rectangles comprises the conductive layer. The rectangles are not connected to the line or to other rectangles. Near edges of the rectangles and of the line are parallel. The rectangles are floating. The test structure is used with a passive voltage contrast test in a scanning electron microscope. A test structure and method to measure critical dimensions is disclosed.

Abstract: In an EUV reflection mask which is set up for region-by-region exposure of a radiation-sensitive layer lying on a semiconductor wafer by means of radiation in the spectral region of extreme ultraviolet radiation, which radiation is reflected at the mask, patterns are written directly into a multilayer layer, lying on a substrate, by means of a focused laser beam or by ion implantation, the reflectivity of which patterns is reduced by more than 90% compared with the reflectivity of the regions that are not written to, and which patterns form the radiation-absorbing regions of the mask. This avoids the shadowing of the exposure radiation that is incident at a small angle, said shadowing occurring with the use of the EUV reflection masks that have been customary heretofore.

Abstract: A method of manufacturing an optical element including the steps of: forming a through hole in a semiconductor element which has an optical section and an electrode electrically connected to the optical section; and forming a conductive layer extending from a first surface of the semiconductor element on which the optical section is formed, through an inner wall surface of the through hole, to a second surface opposite to the first surface.

Abstract: A semiconductor device for picking up an image includes a lens-mounting unit provided with a lens for picking up an image; a semiconductor chip having a light-receiving element formed on a circuit-forming surface thereof, the light-receiving element converting light from the lens into an image signal; a flexible substrate provided between the lens-mounting unit and the semiconductor chip so as to supply the image signal to an external circuit; and a shading plate blocking light transmitting through the flexible substrate toward the semiconductor chip so as to substantially remove an influence of the light on the light-receiving element.

Abstract: The present invention aims to economically implement an ultra-compact semiconductor device having an identification number according to the efficient utilization of an electron-beam writing method.

Abstract: A semiconductor integrated circuit device is subjected to a non-contact and non-destructive analysis using a laser beam after fabrication process, and impurity regions are previously formed in an area assigned to wiring strips regardless of the circuit components, wherein the impurity regions are selectively coupled with the wiring strips for supplying optical beam induced current to a target circuit component so as to analyze the switching action of the target circuit component.

Abstract: A semiconductor memory device having a trench-type capacitor configuration is provided. The device comprises an element isolation insulating film formed on the surface of the substrate in the vicinity of the trenches. The insulating film includes a thickness-reducing region to which the inclined end portion of the capacitor electrode is connected.

Abstract: A memory cell array (50) of a DRAM has a so-called divided bit line structure including two regions (50a and 50) divided from each other. One bit line (24) of a bit line pair is connected to a predetermined memory cell in a first memory cell array block (50a) and is kept in unloaded state in a second memory cell array block (50b). The other bit line (25) of a bit line pair is kept in unloaded state in the first memory cell array block (50a) and is connected to a predetermined memory cell in a first memory cell array block (50b). In these structures, the load state is kept same in both bit lines of the bit line pair. In the memory cell array, four memory cells are disposed in a cross-relationship, and are connected to the bit line (24) through a contact portion (17) used in common by the four memory cells. The word lines (20a and 20b) are formed to obliquely cross the bit lines and to extend perpendicularly to each other. Capacitors (3) in the memory cells have portions extended over the word lines.