Charge Transfer Device Using Both Electron And Hole Signal Carriers Patents (Class 257/912)
  • Patent number: 9703010
    Abstract: Methods and articles are provide for: a substrate having first and second opposing surfaces; an intermediate layer substantially covering the first surface of the substrate, the intermediate layer being between about 1-5 microns in thickness and having a hardness of at least 15 GPa; a first outer layer substantially covering the intermediate layer; and a second outer layer substantially covering the first outer layer, and having a hardness of at least 15 GPa.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: July 11, 2017
    Assignee: Corning Incorporated
    Inventors: Charles Andrew Paulson, Darwin Gene Enicks, Jean-Francois Oudard, James Joseph Price, Jue Wang
  • Patent number: 8865482
    Abstract: A method of detecting the circular uniformity of semiconductor circular contact holes. Several detection circuit structures are disposed on the semiconductor wafer: N-type active regions and P-type active regions; silicon dioxide layers separate the N-type active regions from the P-type active regions; the N-type active regions are formed in the P well and the P-type active regions are formed in the N well; polysilicon gates bridge the N-type active regions and the P-type active regions; gate oxide layers insulate the P-type regions and the N-type regions from the polysilicon gates, so that the P-type regions and the N-type regions are independent; the N-type active regions connect with circular contact holes while the P-type active regions and the polysilicon gates connect with oval contact holes; a electron beam scanner detects the circular uniformity of the contact holes. This invention advantageously reflects effectively and comprehensively the circular uniformity of the contact holes.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: October 21, 2014
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventors: Kai Wang, HungLin Chen, Yin Long, Qiliang Ni, MingShen Kuo
  • Patent number: 7709367
    Abstract: A method for fabricating a storage node contact in a semiconductor device includes forming a landing plug over a substrate, forming a first insulation layer over the landing plug, forming a bit line pattern over the first insulation layer, forming a second insulation layer over the bit line pattern, forming a mask pattern for forming a storage node contact over the second insulation layer, etching the second and first insulation layers until the landing plug is exposed to form a storage node contact hole including a portion having a rounded profile, filling a conductive material in the storage node contact hole to form a contact plug, and forming a storage node over the contact plug.
    Type: Grant
    Filed: June 12, 2007
    Date of Patent: May 4, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hae-Jung Lee, Ik-Soo Choi, Chang-Youn Hwang, Mi-Hyune You
  • Patent number: 7557390
    Abstract: A solid image capturing element comprising a plurality of vertical shift registers arranged to each correspond to a column of a plurality of light receiving pixels in a matrix arrangement, a horizontal shift register provided on an output side of the plurality of vertical shift registers, and an output section provided on an output side of the horizontal shift register. In this solid image capturing element, a reverse conductive semiconductor region is formed over one major surface of one conductive semiconductor substrate, the plurality of light receiving pixels, the plurality of vertical shift registers, the horizontal shift register, and the output section are formed in the semiconductor region, and a portion of the semiconductor region where the output section is formed has a higher dopant concentration than the portion of the semiconductor region where the horizontal shift register is formed.
    Type: Grant
    Filed: October 17, 2003
    Date of Patent: July 7, 2009
    Assignee: Sanyo Electric co., Ltd.
    Inventors: Yoshihiro Okada, Yuzo Otsuru
  • Patent number: 6815719
    Abstract: A field effect transistor includes an n+ high-density impurity injection area, a p+ high-density impurity injection area, an i-impurity non-injection area, and a gate electrode. The gate electrode is free from completely lapping over the i-impurity non-injection area, but laps over substantially half the i-impurity non-injection area adjacent to the n+ high-density impurity injection area so as to avoid channel carrier capture levels due to crystal defects/grain boundaries and an effect of potential barriers due to the channel carrier capture levels.
    Type: Grant
    Filed: September 19, 2001
    Date of Patent: November 9, 2004
    Assignee: Hitachi, Ltd.
    Inventor: Hajime Akimoto
  • Patent number: 6566694
    Abstract: A heterojunction bipolar transferred electron tetrode has an anode region providing a first terminal, an active region in which Gunn-Hilsum oscillations are generated, a base region providing a second terminal, a cathode region providing a third terminal, and a fourth terminal which is operable independently of the three terminals. The fourth terminal can take the form of a second cathode-type structure, a second base region or a Schottky gate electrode. The cathode region and fourth terminal are in proximity enough to each other such that one of the cathode region and the fourth terminal is usable as an input terminal and that the other of the cathode region and the fourth terminal is usable as a terminal to which an electrical signal for disturbing an electric field profile or a current density in the active region is applied.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: May 20, 2003
    Assignee: Sharp Kabushiki Kaisha
    Inventor: John Kevin Twynam
  • Patent number: 6437378
    Abstract: A charge coupled device includes an integrated circuit substrate and a transfer circuit, in the integrated circuit substrate, that transfers charge signals in the charge coupled device to provide transferred charge signals. An amplifier, in the integrated circuit substrate and electrically coupled to the transfer circuit, amplifies the transferred charge signals to generate amplified charge signals. Related methods are also discussed.
    Type: Grant
    Filed: September 20, 1999
    Date of Patent: August 20, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sang-Sik Park
  • Patent number: 6417531
    Abstract: A charge transfer device has a charge transfer region under charge transfer electrodes for stepwise conveying charge packets through potential wells to a floating diffusion region, and the charge transfer region has a boundary sub-region contracting toward the floating diffusion region, wherein the final potential well is created at a certain portion in said boundary sub-region close to the floating diffusion region so that each charge packet travels over a short distance, thereby enhancing a charge transfer efficiency.
    Type: Grant
    Filed: October 27, 1999
    Date of Patent: July 9, 2002
    Assignee: NEC Corporation
    Inventor: Yasutaka Nakashiba
  • Publication number: 20020017661
    Abstract: To transfer signal charges at high speed with small noise, there is provided a charge transfer apparatus including a semiconductor substrate of one conductivity type, a charge transfer region of a conductivity type opposite to that of the semiconductor substrate that is formed in the semiconductor substrate and joined to the semiconductor substrate to form a diode, a signal charge input portion which inputs a signal charge to the charge transfer region, a signal charge output portion which accumulates the signal charge transferred from the charge transfer region, and a plurality of independent potential supply terminals which supply a potential gradient to the semiconductor substrate, wherein the signal charge in the charge transfer region is transferred by the potential gradient formed by the plurality of potential supply terminals.
    Type: Application
    Filed: June 7, 2001
    Publication date: February 14, 2002
    Inventor: Mahito Shinohara
  • Patent number: 5892292
    Abstract: A getterer structure for dielectrically isolated wafer structures such as bonded wafers. The getterer is a layer of polysilicon along the sidewalls of semiconductor regions isolated from each other by trenches. The polysilicon may be doped. The polysilicon is oxidized and polysilicon deposited to fill voids in the trenches.
    Type: Grant
    Filed: March 29, 1996
    Date of Patent: April 6, 1999
    Assignee: Lucent Technologies Inc.
    Inventor: William Graham Easter
  • Patent number: 5627388
    Abstract: A CCD-solid state image sensor includes a sensing area for generating signal charges in response to incident light, a storage area for storing the signal charges from the sensing area, an HCCD (Horizontal Charge Coupled Device) for extracting the signal charges stored in the storage area, a high sensitivity signal charge detection and amplification circuit for detecting and amplifying signal charges of electrons from the HCCD, and a low sensitivity signal charge detection and amplification circuit for detecting and amplifying signal charges of holes from the HCCD.
    Type: Grant
    Filed: February 14, 1996
    Date of Patent: May 6, 1997
    Assignee: LG Semicon Co., Ltd.
    Inventor: Uya Shinji
  • Patent number: 5479035
    Abstract: An ionic liquid-channel charge-coupled device that separates ions in a liquid sample according to ion mobility characteristics includes a channel having an inner wall that has a matrix liquid disposed within. An insulating material surrounds the channel, and an introduction element introduces a liquid sample into the channel. The sample is preferably a liquid solution that has at least one ionic specie present in the solution. The device further includes a gating element that establishes at least one charge packet in the channel in response to an externally applied input signal, and a transport element that induces the charge packet to migrate through the channel. The gate element can be a plurality of spaced-apart, electrically conductive, gate structures that are alternately disposable between a high voltage state and a low voltage state. The transport element further includes an application element that applies a variable voltage to the gating element.
    Type: Grant
    Filed: December 9, 1994
    Date of Patent: December 26, 1995
    Assignee: Massachusetts Institute of Technology
    Inventors: Michael W. Geis, Stephanie A. Gajar, Nancy Geis
  • Patent number: 5374834
    Abstract: An ionic liquid-channel charge-coupled device that separates ions in a liquid sample according to ion mobility characteristics includes a channel having an inner wall that has a matrix liquid disposed within. An insulating material surrounds the channel, and an introduction element introduces a liquid sample into the channel. The sample is preferably a liquid solution that has at least one ionic specie present in the solution. The device further includes a gating element that establishes at least one charge packet in the channel in response to an externally applied input sisal, and a transport element that induces the charge packet to migrate through the channel. The gate element can be a plurality of spaced-apart, electrically conductive, gate structures that are alternately disposable between a high voltage state and a low voltage state. The transport element further includes an application element that applies a variable voltage to the gating element.
    Type: Grant
    Filed: October 12, 1993
    Date of Patent: December 20, 1994
    Assignee: Massachusetts Institute of Technology
    Inventors: Michael W. Geis, Stephanie A. Gajar, Nancy Geis
  • Patent number: 5338968
    Abstract: A method is provided for forming isolated regions of oxide of an integrated circuit, and an integrated circuit formed according to the same. A pad oxide layer is formed over the integrated circuit. A nitrogen doped polysilicon layer is formed over the pad oxide layer. A thick nitride layer is then formed over the nitrogen doped polysilicon layer. An opening is formed in the nitride layer and the nitrogen doped polysilicon layer exposing a portion of the pad oxide layer. The nitrogen doped polysilicon layer is annealed encapsulating the polysilicon layer in silicon nitride. A field oxide region is then formed in the opening.
    Type: Grant
    Filed: September 4, 1992
    Date of Patent: August 16, 1994
    Assignee: SGS-Thomson
    Inventors: Robert Hodges, Frank Bryant
  • Patent number: 5309004
    Abstract: A novel heterostructure acoustic charge transport (HACT) device is disclosed which displays both electron and hole transport. The device includes a transducer fabricated on a substrate structure that launches surface acoustic waves. An optional reflector is formed in the substrate structure at an end portion adjacent to the transducer for reflecting the surface acoustic waves. Also included is an electrode configured with the transport channel at an end thereof distal to the transducer for generating electrical signal equivalents of the propagating electrode charge. The device makes use of both the conduction band quantum well to transport electrons and the valance band quantum well to transport holes. In this manner the sampling, processing and detection frequencies of the device can be doubled.
    Type: Grant
    Filed: October 8, 1991
    Date of Patent: May 3, 1994
    Assignee: United Technologies Corporation
    Inventor: Thomas W. Grudkowski