Polysilicon Containing Oxygen, Nitrogen, Or Carbon (e.g., Sipos) Patents (Class 257/914)
  • Electrical erasable and programmable read-only memory and manufacturing method therefor
    Patent number: 5252847
    Abstract: A method for manufacturing an EEPROM comprises the step of using raw gas containing an organic compound having a molecular weight of more than 44, such as ethyl acetate and tetrahydrofuran when a first polysilicon layer serving as a select gate electrode and a second polysilicon layer serving as a floating gate electrode are deposited by a CVD process. The above described step allows a voltage at the time of tunneling electrons to be decreased.
    Type: Grant
    Filed: September 8, 1988
    Date of Patent: October 12, 1993
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Eiichi Arima, Akira Nishimoto, Shinichi Jintate, Kazuo Sudo, Kazutoshi Oku
  • Semiconductor device of MOS structure having p-type gate electrode
    Patent number: 5189504
    Abstract: A semiconductor device of a MOS structure having a p-type gate electrode has a gate electrode including at least two layers consisting of a boron-doped polysilicon layer and a polysilicon layer doped with boron and an inert material. This inert material is nitrogen or carbon.
    Type: Grant
    Filed: January 30, 1992
    Date of Patent: February 23, 1993
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Satoshi Nakayama, Tetsushi Sakai