Abstract: An integrated circuit is disclosed having through silicon vias spaced apart one from another and conductors, each coupled to one or more of the through silicon vias, the conductors in aggregate in use forming a segmented conductive plane maintained at a same potential and forming an electromagnetic shield.

Abstract: A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.

Abstract: Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include one or more parasitic isolation devices and/or buried layer structures disclosed in the present application. The introduction of design and/or process steps to accommodate these novel structures is compatible with conventional CMOS fabrication processes, and can therefore be accomplished at relatively low cost and with relative simplicity.

Abstract: A total ionizing dose suppression architecture for a transistor and a transistor circuit uses an “end cap” metal structure that is connected to the lowest potential voltage to overcome the tendency of negative charge buildup during exposure to ionizing radiation. The suppression architecture uses the field established by coupling the metal structure to the lowest potential voltage to steer the charge away from the critical field (inter-device) and keeps non-local charge from migrating to the “birds-beak” region of the transistor, preventing further charge buildup. The “end cap” structure seals off the “birds-beak” region and isolates the critical area. The critical area charge is source starved of an outside charge. Outside charge migrating close to the induced field is repelled away from the critical region. The architecture is further extended to suppress leakage current between adjacent wells biased to differential potentials.

Abstract: The present invention relates to radiation hardening by design (RHBD), which employs layout and circuit techniques to mitigate the damaging effects of ionizing radiation. Reverse body biasing (RBB) of N-type metal-oxide-semiconductor (NMOS) transistors may be used to counteract the effects of trapped positive charges in isolation oxides due to ionizing radiation. In a traditional MOS integrated circuit, input/output (I/O) circuitry may be powered using an I/O power supply voltage, and core circuitry may be powered using a core power supply voltage, which is between the I/O power supply voltage and ground. However, in one embodiment of the present invention, the core circuitry is powered using a voltage difference between the core power supply voltage and the I/O power supply voltage. The bodies of NMOS transistors in the core circuitry are coupled to ground; therefore, a voltage difference between the core power supply voltage and ground provides RBB.

Abstract: A total ionizing dose suppression architecture for a transistor and a transistor circuit uses an “end cap” metal structure that is connected to the lowest potential voltage to overcome the tendency of negative charge buildup during exposure to ionizing radiation. The suppression architecture uses the field established by coupling the metal structure to the lowest potential voltage to steer the charge away from the critical field (inter-device) and keeps non-local charge from migrating to the “birds-beak” region of the transistor, preventing further charge buildup. The “end cap” structure seals off the “birds-beak” region and isolates the critical area. The critical area charge is source starved of an outside charge. Outside charge migrating close to the induced field is repelled away from the critical region. The architecture is further extended to suppress leakage current between adjacent wells biased to differential potentials.

Abstract: There is provided a multi-layered structure forming method comprising: (A) forming a first insulating material layer containing a first photo-curing material on a substrate; (B) semi-hardening the first insulating material layer by radiating light having a first wavelength to the first insulating material layer; (C) forming a conductive material layer on the semi-hardened first insulating material layer by ejecting droplets of a conductive material to the semi-hardened first insulating material layer from a nozzle of a liquid droplet ejecting apparatus; (D) forming a second insulating material layer containing a second photo-curing material so as to cover the semi-hardened first insulating material layer and the conductive material layer; and (E) forming a first insulating layer, a conductive layer positioned on the first insulating material, and a second insulating layer covering the first insulating layer and the conductive layer by simultaneously heating the first insulating material layer, the conductive

Abstract: A method of forming bipolar junction devices, including forming a mask to expose the total surface of the emitter region and adjoining portions of the surface of the base region. A first dielectric layer is formed over the exposed surfaces. A field plate layer is formed on the first dielectric layer juxtaposed on at least the total surface of the emitter region and adjoining portions of the surface of the base region. A portion of the field plate layer is removed to expose a first portion of the emitter surface. A second dielectric layer is formed over the field plate layer and the exposed portion of the emitter. A portion of the second dielectric layer is removed to expose the first portion of the emitter surface and adjoining portions of the field plate layer. A common contact is made to the exposed first portion of the emitter surface and the adjoining portions of the field plate layer. In another embodiment, the field plate and emitter contact are formed simultaneously.

Abstract: A method and apparatus for increasing the immunity of new generation microprocessors from electrostatic discharge events involve shielding the microprocessors at the die level. A gasket of a lossy material is provided on the substrate upon which the microprocessor is mounted. The gasket surrounds the microprocessor to protect it from electrostatic discharge pulses. A heat spreader is arranged in heat conducting relation with the microprocessor and atop at least a portion of the gasket adjacent the die. The material is a static dissipative material having a volume resistivity of greater than 102 ohm cm and a shielding effectiveness to protect the microprocessor from at least 4 kV of electrostatic discharge pulse at the computer system level in which the microprocessor is to be used.

Abstract: Structures and methods for providing magnetic shielding for integrated circuits are disclosed. The shielding comprises a foil or sheet of magnetically permeable material applied to an outer surface of a molded (e.g., epoxy) integrated circuit package. The foil can be held in place by adhesive or by mechanical means. The thickness of the shielding can be tailored to a customer's specific needs, and can be applied after all high temperature processing, such that a degaussed shield can be provided despite use of strong magnetic fields during high temperature processing, which fields are employed to maintain pinned magnetic layers within the integrated circuit.

Abstract: In integrated circuit that yields the advantages of contemporary processing technologies and yet is irreparably damaged by ionizing radiation. An integrated circuit is designed and fabricated with contemporary processing technologies in well-known fashion, except that certain devices, called “safeguard” devices, are added to the integrated circuit. The safeguard devices are fabricated so that they, and not the other devices on the integrated circuit, are susceptible to ionizing radiation. Furthermore, the safeguard devices are coupled to the utile devices on the integrated circuit in such a manner than when the integrated circuit is bombarded with ionizing radiation the safeguard devices short and destroy the functionality of the utile devices, and, therefore, the functionality of the integrated circuit.

Abstract: A method of manufacturing a high-gain, high-frequency device, such as a phased-array antenna, which uses such a switch having movable parts as a micromachine switch. The high-frequency device comprises a dielectric substrate on which are formed a plurality of waveguides for carrying high-frequency signals, a phase control layer, and dielectric spacers arranged between the phase control layer and another layer to provide space in which a switch formed in the phase control layer is enclosed.

Abstract: A Rad Hard MOSFET has a plurality of closely spaced base strips which have respective source to form invertible surface channels with the opposite sides of each of the stripes. A non-DMOS late gate oxide and overlying conductive polysilicon gate are formed after the source and base regions have been diffused. The base strips are spaced by about 0.6 microns, and the polysilicon gate stripes are about 3.2 microns wide. An enhancement region is implanted through spaced narrow window early in the process and are located in the JFET common conduction region which is later formed by and between the spaced base stripes. The device is a high voltage (greater than 25 volts) device with very low gate capacitance and very low on resistance. An early and deep (1.6 micron) P channel implant and diffusion are formed before the main channel is formed to produce a graded body diode junction.

Abstract: A Static Random Access Memory (SRAM) device includes at least a transfer transistor, a driving transistor and a load resistor which are commonly connected to a node. A well has a first conductive type, and is placed on a substrate. A first impurity region has a second conductive type opposite to the first conductive type, and is placed in the well. A second impurity region has the first conductive type and has higher impurity concentration than the well, and is placed at a lower portion of the first impurity region. The node is composed of at least the first impurity region and the second impurity region.

Abstract: An N-channel radiation-hardened transistor has source and drain regions that are fully enclosed by an intrinsically radiation-hardened thin gate-oxide, which substantially reduces radiation-induced intra-device and inter-device leakage currents. The width of the polysilicon gate directly between the source and drain can be the minimum feature size allowed by the design rules of a given process. The width of the polysilicon surrounding the device is chosen by design rules from the minimum allowed to some wider value to allows the polysilicon overlap to be sufficient to self-align the source and drain without compromising the doping under the field region. The polysilicon should be sufficiently wide so that it completely overlaps any transitional oxide such as LOCOS or trench oxide. The gate capacitance of the N-channel transistor can be tuned to balance SEU hardness and switching performance.

Abstract: A low-cost EMI shield that fits around an integrated circuit package to absorb electromagnetic energy and dissipate it as heat. The shield is not ohmically conductive so it may contact electrically active conductors without affecting the operation of the circuit. EMI is prevented from being radiated by and around an integrated circuit package by a perimeter of material that is lossy to high-frequency electromagnetic currents. This perimeter is fitted around an integrated circuit package such that the gap between a heat sink or other top conductor and the printed circuit board is completely closed by the lossy material. This provides not only a line-of-sight obstruction to RF currents, but also provides a lossy return path to close the circuit loop for currents on the skin of the heat sink. Since the material is lossy, rather than purely conductive, it can be used with a less than perfect ground attachment.

Abstract: A radiation hardened memory device includes active gate isolation structures placed in series with conventional oxide isolation regions between the active regions of a memory cell array. The active gate isolation structure includes a gate oxide and polycrystalline silicon gate layer electrically coupled to a voltage potential resulting in an active gate isolation structure that prevents a conductive channel extending from adjacent active regions from forming. The gate oxide of the active gate isolation structures is relatively thin compared to the conventional oxide isolation regions and thus, will be less susceptible to any adverse influence from trapped charges caused by radiation exposure.

Abstract: An apparatus for and method of eliminating single event upsets (or SEU) in combinational logic are used to prevent error propagation as a result of cosmic particle strikes to the combinational logic. The apparatus preferably includes a combinational logic block electrically coupled to a delay element, a latch and an output buffer. In operation, a signal from the combinational logic is electrically coupled to a first input of the latch. In addition, the signal is routed through the delay element to produce a delayed signal. The delayed signal is routed to a second input of the latch. The latch used in the apparatus for preventing SEU preferably includes latch outputs and a feature that the latch outputs will not change state unless both latch inputs are correct. For example, the latch outputs may not change state unless both latch inputs have the same logical state. When a cosmic particle strikes the combinational logic, a transient disturbance with a predetermined length may appear in the signal.

Abstract: A CMOS logic circuit comprises a logic gate having an input node (e.g., a storage node) coupled to a positive supply potential through a p-type field-effect transistor (PFET), with one or more n-type field-effect transistors (NFETs) being coupled between the storage node and a negative supply potential. Since the response of the circuit to a high-energy particle strike is dominated by the N+ diffusion associated with the NFETs when the state of the storage node is high, i.e., a logical "1", the gate has a switching point that is set closer to the negative supply potential than to the positive supply potential.

Abstract: The invention provides a method for producing wiring and contacts in an integrated circuit including the steps of forming insulated gate components on a semiconductor substrate; applying a photo-reducible dielectric layer to cover the substrate; etching holes and forming contacts; photo-reducing the dielectric to increase its conductivity; covering the resulting structure with an interconnect layer; etching the interconnect layer to define wiring in electrical contact with the contacts; and oxidizing the dielectric to reduce its conductivity.

Abstract: First and second semiconductor devices are separated by a field oxide on a semiconductor substrate, and a field plate is positioned over the field oxide. A leakage detector detects a field leakage current between the first and second semiconductor devices. A field plate generator tunes a potential of said field plate according to a magnitude of the field current detected by the leakage current detector. In this manner, field leakage is optimized, and total dose effects may be monitored for signs of device failure.

Abstract: An integrated circuit and method of use provides conductive vias between conductor layers so that current flows in such a manner that current crowding is reduced in at least one underlying layer. In particular, the current flows from an overlying conductor (306) down to an underlying conductor (303) by a first set of vias (307), and a portion flows through the underlying conductor towards the destination (e.g., a bondpad). Another portion of the current flows downward to a still lower conductor by means of a second set of vias (310, 311). The second set of vias is located further away from the destination than the first set of vias. Current crowding in the underlying conductor is thereby reduced. An integrated circuit utilizing the inventive technique typically has transistors formed in the semiconductor substrate, wherein at least one of the electrodes (e.g.

Abstract: A package for shielding a circuit containing magnetically sensitive materials from external magnetic fields. A shield attached to a base of the package is connected by vias to a first conductive plane. A shield attached to a lid of the package is connected by vias to a second conductive plane. The first shield and the second shield are electrically interconnected. Conductive leads extend from the package and are connected internally to the circuit.

Abstract: A new and improved process by which plastic material forming the plastic body package of an integrated circuit is selectively removed and replaced with a radiation shield having a specific formulation that is customized for a given radiation environment dependent upon the space application in which the integrated circuit is to be used.

Abstract: A semiconductor device has a well region formed in the surface of a substrate, and has functional portions such as MOSFET and bipolar transistor formed in the well region. The carrier concentration profile of the well region assumes the shape of a valley in the direction of depth thereof, and a minimum point thereof has a concentration of smaller than 5.times.10.sup.15 cm.sup.-3 and is located at a position within 1.6 .mu.m from the surface of the substrate. Preferably, the minimum point should have a concentration of greater than 5.times.10.sup.14 cm.sup.-3 but smaller than 5.times.10.sup.15 cm.sup.-3, and more preferably a concentration of greater than 1.times.10.sup.15 cm.sup.-3 but smaller than 5.times.10.sup.15 cm.sup.-3.

Abstract: A method is provided for forming a radiation hard dielectric region of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A field oxide region, a gate oxide layer and an interlevel dielectric layer are formed over the integrated circuit. Silicon ions are implanted separately into the field oxide region, gate oxide layer and interlevel dielectric layer to a sufficient dosage of less than or equal to approximately 1.times.10.sup.14 /cm.sup.2 to form electron traps to capture radiation induced electrons. This method allows for selective enhancement of radiation hardness of a portion of a circuit, thus providing an on-chip "dosimeter" which can be used to compensate the circuit for the loss of performance due to ionizing radiation.

Abstract: Reduced soft errors in charge-sensitive circuit elements such as volatile memory cells 200 occur by using boron-11 to the exclusion of boron-10 or essentially free of boron-10 in borosilicate glass 230, 240 deposited on the substrate 206 directly over the arrays of memory cells. Boron-10 exhibits a high likelihood of fission to release a 1.47 MeV alpha particle upon capture of a naturally occurring cosmic ray neutron. This capture occurs frequently in boron-10 because of its high neutron capture cross-section. Boron-11 does not fission.

Abstract: An electro-optic integrated circuit including an addressable array of light emitting devices, a column decoder and a plurality of address lines formed on the substrate. There are address lines each including an external connection pad. The decoder includes a switching circuit connected to each column for activating the column and a plurality of sets of diodes connected to the address lines and the switching circuits so that each set of diodes has a unique code produced by a combination of diodes in that set .and the address lines to which the diodes in that set are connected.

Abstract: A laser control circuit in which the laser is driven by a voltage controlled, current driver. At the beginning of each scan, an outer loop senses the laser power, and compares it at an outer loop summing junction to a predetermined value to generate a correction, and then applies that correction to the current driver through an inner summing junction. Within each scan, an inner loop detects the voltage across the laser and applies it as a correction voltage to the inner loop summing junction. The result is that at the beginning of each scan the laser power is set, and during the scan the voltage across the laser is held constant.

Abstract: A pre-molded plastic package has encapsulation material removed so that an upper cavity is formed above the die and its associated wirebonds and a lower cavity is formed below the die attach pad and lead frame. Advantageously, the encapsulating material is removed without damaging the die, its associated wirebonds or the lead frame. An upper shield is then mounted on the top side over the still encapsulated die and wirebonds. Encapsulating material, such as epoxy, is then placed about the upper shield and cured. A lower shield is then mounted on the bottom side the die attach pad and lead frame. Encapsulating material is also placed over the lower shield and cured. Advantageously, the invention provides a process alternative whereby the shields can be installed at a very low per unit cost and in only minutes per unit without the need for custom tooling.

Abstract: A silicon layer formed atop a sapphire substrate is selectively recrystallized such that the original degraded quality of the crystallinity of an N-well region where a P-channel device is to be formed is enhanced, so that leakage in the P-channel device is reduced, while the high ultraviolet reflectance number of a P-well region where an N-channel device resides remains unaffected. The process according to the present invention involves implanting silicon into only that portion of the silicon layer where an N-conductivity well region for a P-channel device is to be formed. An N-conductivity type impurity is introduced into the silicon-implanted portion of the silicon layer, to form the N-conductivity well region. The structure is then annealed at a relatively low temperature for several minutes, which is sufficient to activate the phosphorus and to cause local recrystallization of the N-well region of the silicon layer, without essentially causing a redistribution of the phosphorus.

Abstract: An arrangement for protecting an integrated circuit device (11) against latch up during a nuclear event comprising a capacitance (15) and a switch (17) connected in parallel across the power supply lines (13) of the device. When the power supply lines are connected to a power supply (19) the capacitance stores energy sufficient to supply necessary operating currents to the device during its normal operation. The switch is arranged so that, under a transient gamma pulse incident thereon during a nuclear event, its impedance is set to a low value at such a rate that the energy stored by the capacitance is discharged through the switch and the voltage applied to the device via the power supply lines is pulled down to such a level and at such a rate as to prevent transient gamma pulse induced latch-up in the device.

Abstract: A complementary insulated gate field effect transistor comprises a semiconductor body having an effectively planar surface, the semiconductor body containing complementary conductivity type wells in which complementary transistors are formed. A field insulator layer is selectively formed on the surface of the body, the field insulator layer being hardened against radiation. That portion of the planar surface of the body on which the field insulator layer is formed is not lower than respective surface portions on which first and second gate insulator layers of the complementary conductivity type transistors are formed. In addition to respective gates, and source and drain region pairs, the complementary transistors have insulative spacers which abut sidewalls of the first and second gates and the field insulator layer and extend over portions of the source and drain regions.

Abstract: A radiation hardened NMOS transistor structure suited for application to radiation hardened CMOS devices, and the method for manufacturing it is disclosed. The new transistor structure is characterized by "P" doped guard bands running along and immediately underlying the two bird's beak regions perpendicular to the gate. The transistor and the CMOS structure incorporating it exhibit speed and size comparable to those of conventional non-rad-hard CMOS structure, relatively simple manufacturing, and excellent total-dose radiation hardness.

Abstract: A semiconductor body (100) has a first device region (20) of one conductivity type forming with a second device region (13) of the opposite conductivity type provided adjacent one major surface (11) of the semiconductor body (100) a first pn junction (40) which is reverse-biassed in at least one mode of operation. A floating further region (50) of the opposite conductivity type is provided within the first device region (20) remote from the major surfaces (11 and 12) of the semiconductor body (100) and spaced from the second device region (13) so that, in the one mode, the depletion region of the first pn junction (40) reaches the floating further region (50) before the first pn junction (40) breaks down.

Abstract: The present invention provides a unique circuit and layout methods for improving upon series redundant circuits. A substitution device, comprising a pair of series connected N or P FETs for respective single FETs, can be further hardened or enhanced against cosmic rays, particles, etc. by spacing the P FETs a predetermined distance apart so that an ion or other particle cannot strike or affect both channels simultaneously, thus avoiding upset. When these devices are placed in cells (i.e., ASIC) in logic or the like circuits, the predetermined spacing is related to cell height. Also, alignment of the gates of the substitution device on a common axis minimizes the window of a satellite through which a particle could effectively strike the common gate axis possibly to upset both gates.

Abstract: A method and apparatus for contructing diamond semiconductor structures made of polycrystalline diamond thin films is disclosed. The use of a polycrystalline diamond deposition on a substrate material provides an advantage that any substrate material may be used and the ability to use polycrystalline diamond as a material is brought about through the use of an undoped diamond layer acting as an insulating layer which is formed on a boron-doped layer. Because of the structure, ion implantation can be employed to reduce the ohmic contact resistance. The ion implantation also provides that the entire structure can be made using a deep implant to form a channel layer which allows the insulating gate structure to be formed as an integral part of the device. The buried channel can be doped through the use of several implantation steps through the insulating undoped layer.