Abstract: A non-volatile memory device may include a first wordline on a substrate, an insulating layer on the first wordline, and a second wordline on the insulating layer so that the insulating layer is between the first and second wordlines. A bit pillar may extend adjacent the first wordline, the insulating layer, and the second wordline in a direction perpendicular with respect to a surface of the substrate, and the bit pillar may be electrically conductive. In addition, a first memory cell may include a first resistance changeable element electrically coupled between the first wordline and the bit pillar, and a second memory cell may include a second resistance changeable element electrically coupled between the second wordline and the bit pillar. Related methods and systems are also discussed.

Abstract: An improved Fast Recovery Diode comprises a main PN junction defining a central conduction region for conducting high current in a forward direction and a peripheral field spreading region surrounding the central conduction region for blocking high voltage in the reverse direction. The main PN junction has an avalanche voltage equal to or lower than an avalanche voltage of the peripheral field spreading region so substantially the entire said main PN junction participates in avalanche conduction. This rugged FRED structure can also be formed in MOSFETS, IGBTS and the like.

Abstract: A semiconductor device has a well region having a first conductivity type and formed in an upper portion of a semiconductor substrate, a gate insulating film and a gate electrode formed successively on the well region of the semiconductor substrate, a threshold voltage control layer for controlling a threshold voltage formed in the portion of the well region which is located below the gate electrode and in which an impurity of the first conductivity type has a concentration peak at a position shallower than in the well region, an extension region having a second conductivity type and formed in the well region to be located between each of the respective portions of the well region which are located below the both end portions in the gate-length direction of the gate electrode and the threshold voltage control layer, and source and drain regions each having the second conductivity type and formed outside the extension layer in connected relation thereto.

Abstract: The present invention provides a solid-state image pickup apparatus which is able to easily discharge signal charges in a signal accumulating section and which is free from reduction in the dynamic range of the element, thermal noise in a dark state, an image-lag and so forth even if the pixel size of the MOS solid-state image pickup apparatus is reduced, the voltage of a reading gate is lowered and the concentration in the well is raised. The solid-state image pickup apparatus according to the present invention incorporates a p-type silicon substrate having a surface on which a p+ diffusion layer for constituting a photoelectric conversion region and a drain of a reading MOS field effect transistor are formed. A signal accumulating section formed by an n-type diffusion layer is formed below the p+ diffusion layer. A gate electrode of the MOS field effect transistor is, on the surface of the substrate, formed between the p+ diffusion layer and the drain.

Abstract: Apart from a semiconductor substrate and a photosensitive region in the semiconductor substrate, which comprises a space charge zone region for generating a diffusion current portion and a diffusion region for generating a diffusion current portion, a photodiode includes an insulation means in the semiconductor substrate for at least partially confining the diffusion region against an adjacent surrounding region of the semiconductor substrate.

Abstract: A semiconductor package including passive elements and a method of manufacturing provide reduced package size, improved performance and higher process yield by mounting the passive elements beneath the semiconductor die on the substrate. The semiconductor die may be mounted above the passive elements by mechanically bonding the semiconductor die to the passive elements, mounting the passive elements within a recess in the substrate or mounting the semiconductor using an adhesive retaining wall on the substrate that protrudes above and extends around the passive elements. The recess may include an aperture through the substrate to vent the package to the outside environment or may comprise an aperture through the substrate and larger than the semiconductor die, permitting the encapsulation to entirely fill the aperture, covering the die and the passive elements to secure them mechanically within the package.

Abstract: A high voltage electrical device (20), having a substrate layer (22), base layer (24) and top layer (26), provides high voltage properties in excess of 1000V. Slicing a wafer (28) from an ingot (30) created in by monocrystalline growth forms the substrate layer (22), and this high quality crystal is used as the high resistivity layer in the device (20). The base layer (24) is a highly doped, low resistivity, epitaxial layer deposited on the lower surface (32) of the substrate layer (22) at a fast rate greater than approximately 2 microns/minute. The top layer (26) is a diffusion layer diffused into an upper surface (34) of the substrate layer (22). To control stress in the wafer (28), the epitaxial base is doped with germanium.

Abstract: A semiconductor diode includes a first semiconductor layer including a dopant having a first conductivity type. A second semiconductor layer is adjacent the first semiconductor layer and includes a dopant having the first conductivity type and having a dopant concentration less than a dopant concentration of the first semiconductor layer. Adjacent the second semiconductor layer is a third semiconductor layer including a dopant having the first conductivity type and having a dopant concentration greater than the dopant concentration of the second semiconductor layer. A fourth semiconductor layer is adjacent the third semiconductor layer and includes a dopant of a second conductivity type. Respective contacts are connected to the first and fourth semiconductor layers.

Abstract: The reliability, electromigration resistance, adhesion, and electrical contact resistance of planarized, in-laid metallization patterns, e.g., of copper, are enhanced by a process comprising selectively depositing on the planarized, upper surfaces of the metallization features at least one thin layer comprising at least one passivant element for the metal of the features, reacting the at least one passivant element to chemically reduce any deleterious oxide layer present at the upper surfaces of the metallization features, and diffusing the at least one passivant element for a distance below the upper surface to form a passivated top interface. The passivated top interfaces advantageously exhibit reduced electromigration and improved adhesion to overlying metallization with lower ohmic contact resistance. Planarization, as by CMP, may be performed subsequent to reaction/diffusion to remove any elevated, reacted and/or unreacted portions of the at least one thin layer.

Abstract: The invention relates to a semiconductor device including a preferably discrete bipolar transistor with a collector region, a base region, and an emitter region which are provided with connection conductors. A known means of preventing a saturation of the transistor is that the latter is provided with a Schottky clamping diode. The latter is formed in that case in that the connection conductor of the base region is also put into contact with the collector region. In a device according to the invention, the second connection conductor is exclusively connected to the base region, and a partial region of that portion of the base region which lies outside the emitter region, as seen in projection, lying below the second connection conductor is given a smaller flux of dopant atoms. The bipolar transistor in a device according to the invention is provided with a pn clamping diode which is formed between the partial region and the collector region.

Abstract: A thin-film laminate type conductor is provided which includes a first conductor that is a metal thin film formed of Al or Al alloy, and a second conductor that is a transparent conductive thin film formed of a metal oxide. The first and second conductors are formed in respective patterns on a transparent substrate, such that at least a part of the second conductor is laminated on at least a part of the first conductor. The transparent conductive thin film is composed of an amorphous film. In another embodiment, the first conductor is composed of laminated metal thin films one of which is formed of Al or Al alloy, and the other of which is formed of a high-melting-point metal. The Al or Al-alloy film is sandwiched between the substrate and the high-melting-point metal film.

Abstract: A high voltage MOSFET with low on-resistance and a method of lowering the on-resistance for a specific device breakdown voltage of a high voltage MOSFET. The MOSFET includes a blocking layer of a first conductivity type having vertical sections of a second conductivity type or the blocking layer may include alternating vertical sections of a first and second conductivity type.

Abstract: A semiconductor device structure and method are presented for increasing a breakdown voltage of a junction between a substrate of first conductivity type and a device region. The structure includes a region of second conductivity type in the substrate completely buried in the substrate below and separated from the device region. The region of second conductivity type is located a predetermined distance away from the device region. The distance is sufficient to permit a depletion region to form between the region of second conductivity type and the device region, when a first voltage is applied between the device region and the substrate. The distance also is determined to produce a radius of curvature of the depletion region, when a second voltage that is larger than the first voltage is applied between the device region and the substrate, that is larger than a radius of curvature of the depletion region about the device region that would be formed if the region of second conductivity type were not present.

Abstract: To ensure bulk breakdown when the mesa diode with a positive bevel angle is reverse biased, the diffused region is formed with thinner edge portions. This eliminates corner or edge effects which create conditions of high electric field, resulting in decreased breakdown voltage and clamping voltage levels. The edges of the surface of epitaxial region are covered with a narrow oxide layer prior to diffusion. The middle portion of the surface remains uncovered. Diffusing through the oxide results in a diffused region which is thinner along the edges of the device than in the interior region below the exposed surface portion. The oxide thickness controls the depth of the edge diffusion.

Abstract: A semiconductor integrated circuit comprising a MOSFET having a metal wiring layer formed via an insulating film above and along the gate electrode of the MOSFET. The MOSFET is structured such that its channel length is small or channel width is large, and an input signal is applied from at least both end sides of the gate electrode thereof. Since the metal wiring layer for the input signal is formed on the gate electrode of the MOSFET, high-speed operation is possible without increasing the layout area. FIG. 1.

Abstract: A high voltage semiconductor structure (10) includes a semiconductor substrate (11) of a first conductivity type. The structure (10) also includes a first region (12) providing a main rectifying junction, a second region (13, 17, 21) of a second conductivity type formed in the semiconductor substrate and surrounding the first region ( 12 ) and a third region (14, 18, 22) of the second conductivity type. The third region (14, 18, 22) has reduced conductivity and greater junction depth compared to the second region (13, 17, 21). The third region (14, 18, 22) surrounds and is in contact with the second region (13, 17, 21) to form field rings which improve (increase) breakdown voltage of the high voltage semiconductor structure (10).

Abstract: A bipolar junction transistor (BJT) which exhibits a suppressed Kirk Effect comprises a lightly-doped n-type collector region formed above a more heavily-doped n+ layer. Directly above the collector is a p-type base which has an extrinsic region disposed laterally about an intrinsic region. An n+ emitter is positioned directly above the intrinsic base region. The BJT also includes a localized n+ region disposed directly beneath the intrinsic base region which significantly increases the current handling capabilities of the transistor.

Abstract: An insulating substrate has thin film transistors, and scanning and data wires for supplying signals to the transistors. Each of the wires has a two-layered structure comprising a lower metal film and an upper metal film. Oxide films serving as etching stopper films and having a width smaller than each of the lower and upper metal films are interposed between the lower and upper metal films over the entire length thereof.

Abstract: A semiconductor device is provided wherein a first diode having a pn junction and a second diode having a combination of a Schottky barrier and a pn junction in a current-passing direction are provided side by side in a direction perpendicular to the current-passing direction. When a forward current with a current density J.sub.F is passed into the second diode, the relation ##EQU1## is established in a forward voltage V.sub.F range of 0.1 (V) to 0.3 (V), where k represents the Boltzmann constant (.apprxeq.1.38.times.10.sup.-23 J/K), T represents the absolute temperature, and q represents the quantity of electron charges (.apprxeq.1.6.times.10.sup.-19 C).

Abstract: A P.sup.+ layer (3) and an N.sup.+ layer (1) are provided on the top and bottom surfaces of an N.sup.- layer (21), respectively. An electrode (7) is formed on the P.sup.+ layer (3), while an electrode (8) is formed on the bottom surface of the N.sup.+ layer (1). In a direction from the electrode (7) to the electrode (8), the area of the cross section of the N.sup.- layer (21) is decreased, which cross section is perpendicular to the direction. An N.sup.-- layer (22) is formed complementarily to the N.sup.- layer (21) which is decreased in cross-sectional area. When a potential applied to the electrode (8) is higher than a potential applied to the electrode (7), a depletion layer extends from a PN junction formed by the P.sup.+ layer (3) and the N.sup.- layer (21). Since the impurity concentration of the N.sup.- layer ( 21) is lower than that of the P.sup.+ layer (3), the depletion layer extends substantially to the N.sup.- layer (21). The depletion layer extending to the N.sup.