Abstract: A method of fabricating an inductor (70) in a silicon substrate (10), wherein an Argon implantation step (84) is performed after the resist layer (82) has been deposited and the polysilicon layer (30) has been etched, but before the resist layer (82) is stripped and the polysilicon annealed. Thus, an amorphous layer (86) is created on the substrate (10) so as to improve the Q factor of the inductor (70), without the need for an additional masking step or adverse impact on the polysilicon layer (30).

Abstract: A semiconductor device is made by forming an oxide layer over a substrate and forming a first conductive layer over the oxide layer. The first conductive layer is connected to ground. A second conductive layer is formed over the first conductive layer as a plurality of segments. A third conductive layer is formed over the second conductive layer as a plurality of segments. If the conductive layers are electrically isolated, then a conductive via is formed through these layers. A first segment of the third conductive layer operates as a first passive circuit element. A second segment operates as a second passive circuit element. A third segment is connected to ground and operates as a shield disposed between the first and second segments. The shield has a height at least equal to a height of the passive circuit elements to block cross-talk between the passive circuit elements.

Abstract: A semiconductor device includes a fuse pattern formed as conductive polymer layer having a low melting point. The fuse pattern is easily cut at low temperature to improve repair efficiency. The semiconductor device includes first and second fuse connecting patterns that are separated from each other by a distance, a fuse pattern including a conductive polymer layer formed between the first and second fuse connection patterns and connecting the first and second fuse connection patterns, and a fuse box structure that exposes the fuse pattern.

Abstract: A COF packaging structure includes a substrate, a first conductive foil, and a second conductive foil. The substrate has a first surface and a second surface opposite to the first surface. The first conductive foil is disposed on the first surface of the substrate and has a first designated pattern for bump bonding. The second conductive foil is disposed on the second surface of the substrate and has a second designated pattern, wherein the area of the second designated pattern is not smaller than the area of the first designated pattern.

Abstract: The present invention provides an organic LED element in which the extraction efficiency is improved up to 80% of emitted light. Further, the invention relates to an electrode-attached translucent substrate having a translucent substrate, a scattering layer formed over the glass substrate and containing a base material having a first refractive index for at least one wavelength of wavelengths of emitted light of an organic LED element and a plurality of scattering materials positioned in the base material and having a second refractive index different from that of the base material, and a translucent electrode formed over the scattering layer and having a third refractive index equal to or lower than the first refractive index, in which distribution of the scattering materials in the scattering layer decreases from the inside of the scattering layer toward the translucent electrode.

Abstract: A microresonator comprising a single-crystal silicon resonant element and at least one activation electrode placed close to the resonant element, in which the resonant element is placed in an opening of a semiconductor layer covering a substrate, the activation electrode being formed in the semiconductor layer and being level at the opening.

Abstract: The present invention provides an RFID device having a substrate body, and an IC component and antenna disposed thereon. The RFID device may further include one or more spacing elements, wherein at least a portion of the substrate body is adapted to be disposed around at least a portion the spacing element, thus reducing the overall size of the substrate body with proper impedance matching. The RFID device may further include an EAS element coupled to the substrate body and/or the spacing element in order to create a combination RFID/EAS device with the ability to reduce its overall footprint without sacrificing the ability to provide both identification and article surveillance functions.

Abstract: To provide a nonvolatile memory having an excellent data holding property and a technique for manufacturing the memory, a polycrystalline silicon film 7 and an insulating film 8 are sequentially stacked on a gate insulating film 6, then the polycrystalline silicon film 7 and the insulating film 8 are patterned to form gate electrodes 7A, 7B, and then sidewall spacers 12 including a silicon oxide film are formed on sidewalls of the gate electrodes 7A, 7B. After that, a silicon nitride film 19 is deposited on a substrate 1 by a plasma enhanced CVD process so that the gate electrodes 7A, 7B are not directly contacted to the silicon nitride film 19.

Abstract: Fuses and methods of forming fuses. The fuse includes: a dielectric layer on a semiconductor substrate; a cathode stack on the dielectric layer, a sidewall of the cathode stack extending from a top surface of the cathode stack to a top surface of the dielectric layer; a continuous polysilicon layer comprising a cathode region, an anode region, a link region between the cathode and anode regions and a transition region between the cathode region and the link region, the transition region proximate to the sidewall of the cathode stack, the cathode region on a top surface of the cathode stack, the link region on a top surface of the dielectric layer, both a first thickness of the cathode region and a second thickness of the link region greater than a third thickness of the transition region; and a metal silicide layer on a top surface of the polysilicon layer.

Abstract: A pinned photodiode, which is a double pinned photodiode having increased electron capacitance, and a method for forming the same are disclosed. The invention provides a pinned photodiode structure comprising a substrate base over which is a first layer of semiconductor material. There is a base layer of a first conductivity type, wherein the base layer of a first conductivity type is the substrate base or is a doped layer over the substrate base. At least one doped region of a second conductivity type is below the surface of said first layer, and extends to form a first junction with the base layer. A doped surface layer of a first conductivity type is over the at least one region of a second conductivity type and forms a second junction with said at least one region of a second conductivity type.

Abstract: A phase change memory array is disclosed, comprising a first cell having a patterned phase change layer, and a second cell having a patterned phase change layer, wherein the patterned phase change layer of the first cell and the patterned phase change layer of the second cell are disposed at different layers.

Abstract: A memory cell includes a first electrode, a second electrode, storage material positioned between the first electrode and the second electrode, and a nanocomposite insulator contacting the storage material.

Abstract: A method for assembling a camera module includes following steps: providing a circuit board having a connecting region; disposing a liquid anisotropic conductive adhesive on the connecting region of the circuit board; placing an image sensor module, on the connecting region of the circuit board; thermal press-bonding the image sensor module onto the circuit board to fix the image sensor module with the circuit board. Because the anisotropic conductive adhesive before being disposed on the circuit board is liquid and doesn't needs to be cut, flow-shop operations are easy to achieve, and costs are decreased.

Abstract: A method for removing at least one photoresist defect is disclosed. The photoresist defect is exposed to a plasma produced from a source gas including oxygen and a non-oxidizing gas in a plasma reactor, wherein the oxygen is present in the source gas at from 1% by volume to about 89% by volume. The non-oxidizing gas includes a mixture of hydrogen and nitrogen, ammonia or combinations thereof. A method for processing a semiconductor device structure is also disclosed, as are embodiments of the source gas.

Abstract: Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.

Abstract: An object is to provide an antifuse with little power consumption at the time of writing. The antifuse is used for a memory element in a read-only memory device. The antifuse includes a first conductive layer, a multilayer film of two or more layers in which an amorphous silicon film and an insulating film are alternately stacked over the first conductive layer, and a second conductive layer over the multilayer film. Voltage is applied between the first and second conductive layers and resistance of the multilayer film is decreased, whereby data is written to the memory element. When an insulating film having higher resistance than amorphous silicon is formed between the first and second conductive layers, current flowing through the antifuse at the time of writing is reduced.

Abstract: A method for fabricating a semiconductor device includes forming a fuse over a substrate, the fuse having a barrier layer, a metal layer, and an anti-reflective layer stacked, selectively removing the anti-reflective layer, forming an insulation layer over a whole surface of the resultant structure including the fuse, and performing repair-etching such that part of the insulation layer remains above the fuse.

Abstract: Disclosed are embodiments of a device and method of forming the device that utilize metal ion migration under controllable conditions. The device embodiments comprise two metal electrodes separated by one or more different dielectric materials. One electrode is sealed from the dielectric material, the other is not. The device is adapted to allow controlled migration of embedded metal ions from the unsealed electrode into dielectric material to form a conductive path under field between the electrodes and, thereby, to decrease the resistance of the dielectric material. Reversing the field causes the metal ions to reverse their migration, to break the conductive metallic path between the electrodes and, thereby, to increase the resistance of the dielectric material. Thus, the device can comprise a simple switch or programmable resistor.

Abstract: A method and structure for an integrated circuit chip has a logic core which includes a plurality of insulating and conducting levels, an exterior conductor level and passive devices having a conductive polymer directly connected to the exterior conductor level. The passive devices contain RF devices which also includes resistor, capacitor, and/or inductor. The resistors can be serpentine resistors and the capacitors can be interdigitated capacitors.

Abstract: The invention relates to a semiconductor device (10) with a semiconductor body (1) comprising a high-ohmic semiconductor substrate (2) which is covered with a dielectric layer (3) containing charges, on which dielectric layer one or more passive electronic components (4) comprising conductor tracks (4) are present, and at the location of the passive elements (4) a semiconductor region (5) is present at the interface between the semiconductor substrate (2) and the dielectric layer (3, 4), a first conductivity-type conducting channel induced in the semiconductor substrate (2) by the charges being interrupted by, and at the location of, the semiconductor region (5). According to the invention, the semiconductor region (5) is monocrystalline and of a second conductivity type, opposite to the first conductivity type. In this way the charge of an induced channel is locally compensated by the charge of the semiconductor regions (5).

Abstract: A structure and method of fabricating reversible fuse and antifuse structures for semiconductor devices is provided. In one embodiment, the method includes forming at least one line having a via opening for exposing a portion of a plurality of interconnect features; conformally depositing a first material layer over the via opening; depositing a second material layer over the first material layer, wherein the depositing overhangs a portion of the second material layer on a top portion of the via opening; and depositing a blanket layer of insulating material, where the depositing forms a plurality of fuse elements each having an airgap between the insulating material and the second material layer. The method further includes forming a plurality of electroplates in the insulator material connecting the fuse elements.

Abstract: Provided are methods for producing multiple distinct transistors from a single semiconductor layer, and apparatus incorporating transistors so produced.

Abstract: A flip chip semiconductor device has a substrate with a plurality of active devices formed thereon. A passive device is formed on the substrate by depositing a first conductive layer over the substrate, depositing an insulating layer over the first conductive layer, and depositing a second conductive layer over the insulating layer. The passive device is a metal-insulator-metal capacitor. The deposition of the insulating layer and first and second conductive layers is performed without photolithography. An under bump metallization (UBM) layer is formed on the substrate in electrical contact with the plurality of active devices. A solder bump is formed over the UBM layer. The passive device can also be a resistor by depositing a resistive layer over the first conductive layer and depositing a third conductive layer over the resistive layer. The passive device electrically contacts the solder bump.

Abstract: A device (10) comprises a semiconductor diode (12) and a switchable element (14) positioned in stacked adjacent relationship. The semiconductor diode (12) and the switchable element (14) are electrically connected in series with one another. The switchable element (14) is switchable from a low-conductance state to a high-conductance state in response to the application of a low-density forming current and/or a low voltage.

Abstract: A structure for shielding high frequency passive elements includes a first face of a semi-conductive substrate in parallel with a second face of a non-conductive substrate. The first face of the semi-conductive substrate is substantially parallel to a second face thereof. A passive element is disposed in the non-conductive substrate and is isolated from the second face of the non-conductive substrate. A plurality of conductive conduits disposed in the semi-conductive substrate extends from the first face to the second face thereof, each of the conduits isolated from one another by the semi-conductive substrate material and disposed substantially beneath the passive element. A ground plane disposed on the second face of the semi-conductive substrate electrically connects the conductive conduits disposed therein. An electrical connection between an electronic circuit in the semi-conductive substrate, the passive element and the ground plane holds the passive device and the ground plane at different potentials.

Abstract: A method for integrally forming a metal-oxide-semiconductor (MOS) device and an electrical fuse device on a semiconductor substrate includes the following steps. An isolation structure is formed on the semiconductor substrate. A dielectric layer is deposited over the isolation structure and the semiconductor substrate. A metal layer is deposited on the dielectric layer. A polysilicon layer is deposited on the metal layer. The dielectric layer, the metal layer and the polysilicon layer are patterned into a first stack of the dielectric layer, the metal layer and the polysilicon layer on the isolation structure for functioning as the electrical fuse device, and a second stack of the dielectric layer, the metal layer and the polysilicon layer on the semiconductor substrate for functioning as a gate of the MOS device.

Abstract: A fuse structure includes a substrate, a fuse conductive trace disposed closer to a first chip surface than to a second chip surface facing away from the first chip surface, a metallization layer on the substrate disposed on a side of the fuse conductive trace facing away from the first chip surface, and a planar barrier multilayer assembly disposed between the fuse conductive trace and the metallization layer and including multiple barrier layers of different materials, wherein the fuse conductive trace, the metallization layer and the barrier multilayer assembly are arranged such that when cutting the fuse conductive trace and the barrier multilayer assembly, a first area of the metallization layer is electrically isolated from a second area of the metallization layer.

Abstract: Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.

Abstract: The invention relates to a DNR (differential negative resistance) exhibiting device that can be programmed to store information as readable current amplitudes and to methods of making such a device. The stored data is semi-volatile. Generally, information written to a device in accordance with the invention can maintain its memory for a matter of minutes, hours, or days before a refresh is necessary. The power requirements of the device are far reduced compared to DRAM. The memory function of the device is highly stable, repeatable, and predictable. The device can be produced in a variety of ways.

Abstract: A novel arrangement and method for depositing evaporation control agents so as to coat immersion lithographic solutions which are employed on the surface of semiconductor wafers in connection with the etching of the surfaces of the wafer through the intermediary of an immersion lithographic process.

Abstract: According to an exemplary embodiment, a wafer level package includes a device wafer including at least one device wafer contact pad and a device, and where the at least one device wafer contact pad is electrically connected to the device. The wafer level package includes a first polymer layer situated over the device wafer. The wafer level package includes at least one passive component situated over the first polymer layer and having a first terminal and a second terminal. The first terminal of the at least one passive component is electrically connected to the at least one device wafer contact pad. The wafer level package includes a second polymer layer situated over the at least one passive component. The wafer level package includes at least one polymer layer contact pad situated over the second polymer layer and electrically connected to the second terminal of the at least one passive component.

Abstract: A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel and one layer attached to another to form a laminated 3D chip.

Abstract: Aspects of the invention can provide an ejection method to form a micro lens efficiently on each of a plurality of semiconductor lasers in a wafer state. So that a distance in an x-axis direction between two mutually adjacent sections subject to ejection and a distance between any two nozzles of a plurality of nozzles arranged in the x-axis direction may be in agreement, the ejection method can include a step of positioning a substrate having the two sections subject to ejection, a step of moving relatively the plurality of nozzles along a y-axis direction intersecting the x-axis direction perpendicularly to the substrate, and a step of ejecting a liquid material respectively from the two nozzles to the two sections subject to ejection if the two nozzles should respectively penetrate areas corresponding to the two sections.

Abstract: A method of making integrated circuit thin film resistor includes forming a first dielectric layer (18B) over a substrate and providing a structure to reduce variation of head resistivity thereof by forming a dummy fill layer (9A) on the first dielectric layer, and forming a second dielectric layer (18D) over the first dummy fill layer. A thin film resistor (2) is formed on the second dielectric layer (18D). A first inter-level dielectric layer (21A) is formed on the thin film resistor and the second dielectric layer. A first metal layer (22A) is formed on the first inter-level dielectric layer and electrically contacts a portion of the thin film resistor. Preferably, the first dummy fill layer is formed as a repetitive pattern of sections such that the repetitive pattern is symmetrically aligned with respect to multiple edges of the thin-film resistor (2).