Abstract: A semiconductor chip comprising a capacitor capable of effectively controlling the voltage drop of an LSI is provided. A semiconductor substrate is provided with an element electrode having at least its surface constituted of an aluminum electrode. The surface of the aluminum electrode is roughened. An oxide film is provided on the aluminum electrode. A conductive film is provided on the oxide film. The aluminum electrode, oxide film and conductive film form a capacitor.

Abstract: A capacitor is made by forming a buffer oxide layer, an etching stop layer, and a mold insulation layer over a semiconductor substrate having a storage node contact plug. The mold insulation layer and the etching stop layer are etched to form a hole in an upper portion of the storage node contact plug. A tapering layer is deposited over the mold insulation layer including the hole. The tapering layer and the buffer oxide layer are etched back so that the tapering layer is remained only at the upper end portion of the etched hole. A metal storage node layer formed on the etched hole over the remaining tapering layer. The mold insulation layer and the remaining tapering layer are removed to form a cylindrical storage node having a tapered upper end. A dielectric layer and a plate node are formed over the storage node.

Abstract: A method for manufacturing a semiconductor device. The method comprises depositing a material layer on a semiconductor substrate and patterning the material layer with a patterning material. Patterning forms a patterned structure of a semiconductor device, wherein the patterned structure has a sidewall with a roughness associated therewith. The method also comprises removing the patterning material from the patterned structure and annealing an outer surface of the patterned structure such that the roughness is reduced.

Abstract: A method of fabricating an MIM type capacitor includes at least one of: Forming a first trench within an insulating interlayer formed on a semiconductor substrate. Forming a lower electrode layer of a metal nitride layer substance to fill an inside of the first trench. Forming a second trench on a surface of the lower electrode layer to have a depth less than the first trench. Forming a capacitor dielectric layer conformal along a surface of the lower electrode layer including the second trench. Forming an upper electrode layer of a metal nitride layer substance on the capacitor dielectric layer. Sequentially patterning the upper electrode layer and the capacitor dielectric layer by photolithography.

Abstract: An integrated circuit arrangement is disclosed. In one embodiment, the integrated circuit arrangement includes at least three conductive structures levels and elongated interconnects.

Abstract: Methods for forming the lower electrode of a capacitor in a semiconductor circuit, and the capacitors formed by such methods are provided. The lower electrode is fabricated by forming a texturizing underlayer and then depositing a conductive material thereover. In one embodiment of a method of forming the lower electrode, the texturizing layer is formed by depositing a polymeric material comprising a hydrocarbon block and a silicon-containing block, over the insulative layer of a container, and then subsequently converting the polymeric film to relief or porous nanostructures by exposure to UV radiation and ozone, resulting in a textured porous or relief silicon oxycarbide film. A conductive material is then deposited over the texturizing layer resulting in a lower electrode have an upper roughened surface.

Abstract: A method of producing a capacitor that includes producing a first electrode having a first surface; forming a recess in an element, walls of the element and the first surface of the first electrode defining the recess, the element having a first surface exterior of the recess; forming a dielectric layer on the element, the dielectric layer oriented against the first surface of the element and against the walls of the element within the recess; polishing off at least a portion of the dielectric layer oriented against the first surface of the element to electrically isolate the portion of the dielectric layer located in the recess from any portion of the dielectric layer remaining outside the recess; and producing a second electrode, the second electrode oriented at least partially within the recess with the dielectric layer oriented between the first electrode and the second electrode.

Abstract: High capacitance value capacitors are formed using bimetal foils of an aluminum layer attached to a copper layer. The copper side of a bimetallic copper/aluminum foil or a monometallic aluminum foil is temporarily protected using aluminum or other materials, to form a sandwich. The exposed aluminum is treated to increase the surface area of the aluminum by at least one order of magnitude, while not attacking any portion of the protected metal. When the sandwich is separated, the treated bimetal foil is formed into a capacitor, where the copper layer is one electrode of the capacitor and the treated aluminum layer is in intimate contact with a dielectric layer of the capacitor.

Abstract: A capacitor structure for an integrated circuit. An insulating layer is disposed on a substrate. A first conductive line is embedded in a first level of the insulating layer. A second conductive line is embedded in a second level of the insulating layer lower than the first level and has a projection onto the substrate completely covered by the first conductive line. A third conductive line is embedded in the second level of the insulating layer and separated from the second conductive line by a predetermined space, and has a projection onto the substrate partially covered by the first conductive line. The second conductive line is coupled to the first conductive line by at least one first conductive plug and has a polarity opposite to the third conductive line.

Abstract: Methods for forming the lower electrode of a capacitor in a semiconductor circuit, and the capacitors formed by such methods are provided. The lower electrode is fabricated by forming a texturizing underlayer and then depositing a conductive material thereover. In one embodiment of a method of forming the lower electrode, the texturizing layer is formed by depositing a polymeric material comprising a hydrocarbon block and a silicon-containing block, over the insulative layer of a container, and then subsequently converting the polymeric film to relief or porous nanostructures by exposure to UV radiation and ozone, resulting in a textured porous or relief silicon oxycarbide film. A conductive material is then deposited over the texturizing layer resulting in a lower electrode have an upper roughened surface.

Abstract: A method of forming a metal trench pattern in a thin-film device includes a step of depositing an electrode film on a substrate or on a base layer, a step of forming a resist pattern layer having a trench forming portion used to make a trench pattern, on the deposited electrode film, a step of forming a metal layer for filling spaces in the trench forming portion and for covering the trench forming portion, by performing plating through the formed resist pattern layer using the deposited electrode film as an electrode, a step of planarizing at least a top surface of the formed metal layer until the trench forming portion of the resist pattern layer is at least exposed, and a step of removing the exposed trench forming portion of the resist pattern layer.

Abstract: According to one embodiment, a gate structure including a gate insulation pattern, a gate pattern and a gate mask is formed on a channel region of a substrate to form a semiconductor device. A spacer is formed on a surface of the gate structure. An insulating interlayer pattern is formed on the substrate including the gate structure, and an opening is formed through the insulating interlayer pattern corresponding to an impurity region of the substrate. A conductive pattern is formed in the opening and a top surface thereof is higher than a top surface of the insulating interlayer pattern. Thus, an upper portion of the conductive pattern is protruded from the insulating interlayer pattern. A capping pattern is formed on the insulating interlayer pattern, and a sidewall of the protruded portion of the conductive pattern is covered with the capping pattern. Accordingly, the capping pattern compensates for a thickness reduction of the gate mask.

Abstract: Structurally-stable, tall capacitors having unique three-dimensional architectures for semiconductor devices are disclosed. The capacitors include monolithically-fabricated upright microstructures, i.e., those having large height/width (H/W) ratios, which are mechanical reinforcement against shear forces and the like, by a brace layer that transversely extends between lateral sides of at least two of the free-standing microstructures. The brace layer is formed as a microbridge type structure spanning between the upper ends of the two or more microstructures.

Abstract: In embodiments, a method for manufacturing a semiconductor device may include forming a diffusion preventing layer on a semiconductor substrate having a conductive layer, forming an intermetallic insulating layer on the diffusion preventing layer, forming a trench photo resist layer formed above the intermetallic insulating layer of a first photo resist material, forming a via hole photo resist layer of a second photo resist material at an upper portion and a sidewall in a contact hole of the trench photo resist layer, etching the intermetallic insulating layer and the diffusion preventing layer using the via hole photo resist layer and the trench photo resist layer to substantially simultaneously form a via hole and a trench, and filling the via hole and the trench with a metal thin film to form a metal line.

Abstract: Capacitors having a horizontally folded dielectric layer and methods of manufacturing is the same are provided. An example method for manufacturing a capacitor includes forming a first insulating layer pattern above a substrate, forming a first silicon epitaxial growth layer above a region of the silicon substrate exposed by the first insulating layer pattern through epitaxial growth of a first silicon layer, selectively etching the first insulating layer pattern, forming a dielectric layer pattern above the lateral surface of the first silicon epitaxial growth layer in a shape of a spacer, and forming a second silicon epitaxial growth layer above the silicon substrate through epitaxial growth of a second silicon layer. A capacitor including electrodes made of the first and second silicon epitaxial growth layers with the dielectric layer pattern formed therebetween may be formed by such a method.

Abstract: The present invention relates to semiconductor devices, preferably dynamic random access memory (DRAM) cells, each of which contains at least one trench capacitor with a buried isolation collar. The trench capacitor is located in a trench in a semiconductor substrate, and it comprises inner and outer electrodes and a dielectric layer. The buried isolation collar is recessed into a sidewall of the trench and has a substantially uniform thickness. Such a buried isolation collar is preferably formed by oxygen implantation before trench etching.

Abstract: A method for forming a capacitor of a semiconductor device includes the steps of forming first and second sacrificial insulation layers over a semiconductor substrate divided into first and second regions. The second and first sacrificial insulation layers in the first region are etched to define in the first region of the semiconductor substrate. Storage nodes on surfaces of the holes are formed. A partial thickness of the second sacrificial insulation layer is etched to partially expose upper portions of the storage nodes. A mask pattern is formed to cover the first region while exposing the second sacrificial insulation layer remaining in the second region. The exposed second sacrificial insulation layer in the second region is removed to expose the first sacrificial insulation layer in the second region. The exposed first sacrificial insulation layer in the second region and the first sacrificial insulation layer in the first region is removed. The mask pattern is removed.

Abstract: Some embodiments of the invention include a memory cell having a vertical transistor and a trench capacitor. The trench capacitor includes a capacitor plate with a roughened surface for increased surface area. Other embodiments are described and claims.

Abstract: The invention relates to a memory device electrode, in particular for a resistively switching memory device, wherein the surface of the electrode is provided with a structure, in particular comprises one or a plurality of shoulders or projections, respectively. Furthermore, the invention relates to a memory cell comprising at least one such electrode, a memory device, as well as a method for manufacturing a memory device electrode.

Abstract: A method for fabricating a semiconductor device is disclosed. The semiconductor device includes a capacitor and a support insulator. The capacitor includes a cylindrical electrode. The cylindrical electrode comprises upper and lower sections. The lower section has a roughened inner surface and an outer surface supported by the support insulator. The upper section upwardly projects from the support insulator. An initial cylindrical electrode is formed, wherein the initial cylindrical electrode comprises an initial upper section and an initial lower section which correspond to the upper section and the lower section of the cylindrical electrode, respectively. The initial upper section is supported by the support insulator. Specific impurities are implanted into the initial upper section, wherein the specific impurities serve to prevent the initial upper section from being roughened.

Abstract: An integrated circuit capacitor includes first and second electrodes and at least one dielectric layer extending between the first and second electrodes. The first electrode includes at least one carbon nanotube. The capacitor further includes an electrically conductive catalyst material. This catalyst material may be selected from the group consisting of iron, nickel and cobalt and alloys thereof.

Abstract: The present invention is generally directed to a method of manufacturing sidewall spacers on a memory device, and a memory device comprising such sidewall spacers. In one illustrative embodiment, the method includes forming sidewall spacers on a memory device comprised of a memory array and at least one peripheral circuit by forming a first sidewall spacer adjacent a word line structure in the memory array, the first sidewall spacer having a first thickness and forming a second sidewall spacer adjacent a transistor structure in the peripheral circuit, the second sidewall spacer having a second thickness that is greater than the first thickness, wherein the first and second sidewall spacers comprise material from a single layer of spacer material.

Abstract: A MIM capacitor includes a lower electrode disposed on a semiconductor substrate. A dielectric layer is disposed on the lower electrode to completely cover an exposed surface of-the lower electrode. An upper electrode is disposed on the dielectric layer. A method for forming a MIM capacitor includes forming a lower electrode on a semiconductor substrate. A dielectric layer and an upper metal layer are formed on an entire surface of the substrate to cover the lower electrode. The dielectric and upper metal layers are patterned on the lower electrode.

Abstract: Various methods and apparatus for simultaneously processing two single-sided hard memory disks is provided. Disks are positioned in pairs, with one surface of one disk positioned adjacent one surface of the second disk, with the disk surfaces touching or with a slight separation between them. In this back-to-back orientation, the disk pairs may be processed using conventional double-sided disk processing equipment and techniques. However, each disk will not have two active surfaces. Because of the positioning of the disks during processing, only one surface of each disk will be subjected to full processing. Therefore, each disk will only have one active side.

Abstract: In a capacitor of a semiconductor device, a bottom electrode is formed on a substrate and has an uneven top surface. An interlayer insulation layer is formed on the substrate and has a via hole exposing the top surface of the bottom electrode. A dielectric layer is formed unevenly on the bottom electrode. A top electrode is formed on the dielectric layer while filling the via hole.

Abstract: An enhanced-surface-area conductive layer compatible with high-dielectric constant materials is created by forming a film or layer having at least two phases, at least one of which is electrically conductive. The film may be formed in any convenient manner, such as by chemical vapor deposition techniques, which may be followed by an anneal to better define and/or crystallize the at least two phases. The film may be formed over an underlying conductive layer. At least one of the at least two phases is selectively removed from the film, such as by an etch process that preferentially etches at least one of the at least two phases so as to leave at least a portion of the electrically conductive phase. Ruthenium and ruthenium oxide, both conductive, may be used for the two or more phases. Iridium and its oxide, rhodium and its oxide, and platinum and platinum-rhodium may also be used. A wet etchant comprising ceric ammonium nitrate and acetic acid may be used.

Abstract: A method of manufacturing electric double layer capacitors is disclosed. The method assumes a model in which solute is dissolved in solvent before preparing electrolyte, and estimates a withstanding voltage through a simulation. The electrolyte, of which withstanding voltage is expected to exceed a target value, is selectively prepared. The method adjusts respective surface areas of the positive electrode and the negative electrode of the capacitor for making full use of the withstanding voltage of the electrolyte. According to this method, a time for developing electrolyte can be substantially shortened, and an electric double layer capacitor having a high withstanding voltage can be efficiently developed.

Abstract: A hemispherical silicon grain (HSG) process is described. A doped poly-Si layer is formed on a substrate, and then an oxidative gas is used to oxidize the surface of the doped poly-Si layer to form an oxide layer. An a-Si layer is then formed on the oxide layer, and the a-Si layer is converted into HSG.

Abstract: According to some embodiments, a capacitor includes a storage conductive pattern, a storage electrode having a complementary member enclosing a storage conductive pattern so as to complement an etch loss of the storage electrode, a dielectric layer disposed on the storage electrode, and a plate electrode disposed on the dielectric layer. Because the complementary member compensates for the etch loss of the storage electrode during several etching processes, the deterioration of the structural stability of the storage electrode may be prevented. Additionally, because the complementary member is formed on an upper portion of the storage electrode, the storage electrode may have a sufficient thickness to enhance the electrical characteristics of the capacitor that includes the storage electrode.

Abstract: The invention provides a method of selectively etching a Hemispherical Silicon Grain (HSG) layer during deep trench capacitor fabrication. A substrate having a pad structure and a deep trench is provided. A buried oxide layer is formed on the upper sidewall of the deep trench and a HSG layer and an ASG layer are formed in the deep trench sequentially. A mask layer is filled into the deep trench and recessed; the exposed ASG layer is then removed. The HSG layer is doped to form a plasma doping layer on the upper portion of the deep trench, which is removed without damaging the silicon substrate. After the mask layer is removed, a cap oxide layer is formed on the deep trench, and the substrate is subjected to a thermal treatment to form a buried plate.