Abstract: A method of forming a metal interconnect for an integrated circuit includes depositing a barrier layer on a dielectric layer having a trench formed therein, depositing an adhesion layer on the barrier layer, depositing a metal layer on the adhesion layer, removing the metal layer using a CMP process until at least a portion of the adhesion layer is exposed, and removing portions of the adhesion layer and the barrier layer sited substantially outside of the trench using a dissolution process. The dissolution process applies an electrolyte solution to those portions of the adhesion layer and the barrier layer sited substantially outside of the trench to dissolve and remove them.

Abstract: Some embodiments include formation of at least one cavity in a first semiconductor material, followed by epitaxially growing a second semiconductor material over the first semiconductor material and bridging across the at least one cavity. The cavity may be left open, or material may be provided within the cavity. The material provided within the cavity may be suitable for forming, for example, one or more of electromagnetic radiation interaction components, transistor gates, insulative structures, and coolant structures. Some embodiments include one or more of transistor devices, electromagnetic radiation interaction components, transistor devices, coolant structures, insulative structures and gas reservoirs.

Abstract: According to an exemplary embodiment, a method for fabricating a multilayer semiconductor structure includes forming first and second patterned segments, where a first patterned segment sidewall is separated from a second patterned segment sidewall by a first gap; forming a first conformal layer over first and second patterned segments and first gap, where the first conformal layer forms a depression over the first gap; forming a third patterned segment in the depression such that a third patterned segment sidewall is separated from the first patterned segment sidewall by a distance, where the third patterned segment sidewall is separated from a depression sidewall by a second gap; and forming a second conformal layer over the first conformal layer, third patterned segment, and second gap, where a dip is formed in the second conformal layer over the second gap. The distance is controlled so as to reduce a size of the dip.

Abstract: A technology for easily forming a multi-layer wiring structure that is fine and reliable. In the multi-layer wiring structure, the lower-layer wiring and the upper-layer wiring that are formed to sandwich an insulating layer are electrically connected to each other in a projection formed in the lower-layer wiring. The projection includes a columnar conductive member and the upper and lower layers thereof and each of the lower layer and the upper layer is formed of a conductive layer formed over the entire lower-layer wiring. The upper-layer is electrically connected to the lower-layer wiring in the portion where the projection is exposed substantially on the same plane as the top surface of the insulating layer.

Abstract: A semiconductor device and a method for manufacturing the same of the present invention in which the semiconductor device is provided with a fuse structure or an electrode pad structure, suppress the copper blowing-out from a copper containing metal film. The semiconductor device comprises a silicon substrate, SiO2 film provided on the silicon substrate, copper films embedded in the SiO2 film, TiN films covering an upper face of a boundary region between an upper face of copper films and the copper films, and the SiO2 film, and SiON films covering an upper face of the TiN films.

Abstract: A method of processing a substrate of a device comprises the as following steps. Form a cap layer over the substrate. Form a dummy layer over the cap layer, the cap layer having a top surface. Etch the dummy layer forming patterned dummy elements of variable widths and exposing sidewalls of the dummy elements and portions of the top surface of the cap layer aside from the dummy elements. Deposit a spacer layer over the device covering the patterned dummy elements and exposed surfaces of the cap layer. Etch back the spacer layer forming sidewall spacers aside from the sidewalls of the patterned dummy elements spaced above a minimum spacing and forming super-wide spacers between sidewalls of the patterned dummy elements spaced less than the minimum spacing. Strip the patterned dummy elements. Expose portions of the substrate aside from the sidewall spacers. Pattern exposed portions of the substrate by etching into the substrate.

Abstract: A capacitive transducer includes a substrate having a first surface and a second surface. The first surface of the substrate defines a first plane. The substrate has a cavity with an interior peripheral edge. The cavity extends between the first surface and the second surface. A body is provided that has an exterior peripheral edge. The body is parallel to the first plane and at least partially blocking the cavity. The body is connected to the substrate by resilient hinges such that, upon the application of a force, the body moves perpendicular to the first plane. A first set of comb fingers is mounted to the substrate. The first set of comb fingers is connected to a first electrical connection. A second set of comb fingers is mounted to the body and extends past the exterior peripheral edge of the body. The second set of comb fingers is connected to a second electrical connection that is isolated from the first connection.

Abstract: A method that controls the distribution of plasma generated in a vacuum chamber, for example, as part of a plasma thin film deposition or plasma etching process. For thin film deposition, the method serves to minimize variations in film thickness caused by the variations of the film deposition conditions. The vacuum chamber includes a high-frequency-wave electrode connected to a high-frequency electric power supply and an earth electrode connected to ground potential. High frequency-electric power is fed to the high-frequency-wave electrode and peak-to peak voltages are measured at multiple measuring points on one of the two electrodes. The distribution of the plasma is controlled by adjusting the chamber pressure to minimize the differences between the measured peak-to-peak voltages.

Abstract: The present invention provides a method of forming a interconnect barrier layer 100. In the method, physical vapor deposition of barrier material 200 is performed within an opening 140 located in a dielectric layer 135 of a substrate 110. RF plasma etching of the barrier material 200 that is deposited in the opening 140 occurs simultaneously with conducting the physical vapor deposition of the barrier material 200.

Abstract: A method for use in fabrication of a semiconductor device comprises forming a conformal conductive layer over a planarized surface of a dielectric layer, and within an opening formed in the dielectric layer. The opening will typically have an aspect ratio of about 4:1 or greater. An etch is performed with specified gasses under a range of specified conditions which removes the conformal conductive layer from the planarized surface, but which leaves unetched the conformal conductive layer within the opening.

Abstract: A chip-type solid electrolytic capacitor comprises capacitor elements. A cathode terminal comprising a plate-like conductor is interposed between cathode layers of the capacitor elements. The capacitor elements are bonded to each other by a bonding agent such as a solder or a conductive adhesive. The cathode terminal is provided with a through hole formed at a portion to be brought into contact with each of the capacitor elements. Bonding surfaces of the capacitor elements are directly connected at the through hole.

Abstract: A lower electrode projects outward from a common end face of an upper electrode and a capacitor film. A protective film, which is made of a different material from the capacitor film, is deposited on top of a part of the lower electrode outside the end face. The protective film also extends to the position at a certain distance inward from the end face, so that it is placed between the capacitor film and the lower electrode. The capacitor film thereby has a stepped surface near the end face due to the presence of the protective film, which suppresses the progress of damage during etching of the upper electrode and the capacitor film. Further, the protective film prevents the occurrence of damage in the lower electrode.

Abstract: A modulator has a transparent substrate with a first surface. At least one interferometric modulator element resides on the first surface. At least one thin film circuit component electrically connected to the element resides on the surface. When more than one interferometric element resides on the first surface, there is at least one thin film circuit component corresponding to each element residing on the first surface. A method of manufacturing interferometric modulators with thin film transistors is also disclosed.

Abstract: A method for forming a wiring pattern according to an aspect of the invention forms a wiring pattern in a certain area on a substrate by using a droplet discharge technique, and includes forming a bank surrounding the certain area on the substrate; discharging a first functional liquid containing a material of the wiring pattern to an area surrounded by the bank to form a first wiring pattern; discharging a second functional liquid onto the first wiring pattern to form a second wiring pattern; and collectively baking the wiring pattern of a plurality of layers including the first wiring pattern and the second wiring pattern.

Abstract: Methods of etching silicon nitride material, and more particularly, etching nitride selective to silicon dioxide or silicide, are disclosed. The methods include exposing a substrate having silicon nitride thereon to a plasma including at least one fluorohydrocarbon and a non-carbon containing fluorine source such as sulfur hexafluoride (SF6). The plasma may also include oxygen (O2) and the fluorohydrocarbons may include at least one of: trifluoromethane (CHF3), difluoromethane (CH2F2), and methyl fluoride (CH3F). In an alternative embodiment, the plasma includes one of hydrogen (H2) and nitrogen trifluoride (NF3) and one of tetrafluoromethane (CF4) and octafluorocyclobutane (C4F8). The methods are preferably carried out using a low bias voltage, e.g. <100 V.

Abstract: The invention includes methods of forming capacitor structures and removing organic material. An organic material, such as a photoresist, is disposed on a substrate. The organic material is contacted with a chemical mechanical polishing pad and a polishing fluid to remove the organic material from the substrate. The polishing fluid can be essentially free of particles, and can be water.

Abstract: Methods of forming an integrated circuit device may include forming an insulating layer on an integrated circuit substrate, forming a first conductive layer on the insulating layer, and forming a second conductive layer on the first conductive layer so that the first conductive layer is between the second conductive layer and the insulating layer. Moreover, the first conductive layer may be a layer of a first material, the second conductive layer may be a layer of a second material, and the first and second materials may be different. A hole may be formed in the second conductive layer so that portions of the first conductive layer are exposed through the hole. After forming the hole in the second conductive layer, the first and second conductive layers may be patterned so that portions of the first and second conductive layers surrounding portions of the first conductive layer exposed through the hole are removed while maintaining portions of the first conductive layer previously exposed through the hole.

Abstract: In fabricating a microelectromechanical structure (MEMS), a method of forming a narrow gap in the MEMS includes a) depositing a layer of sacrificial material on the surface of a supporting substrate, b) photoresist masking and at least partially etching the sacrificial material to form at least one blade of sacrificial material, c) depositing a structural layer over the sacrificial layer, and d) removing the sacrificial layer including the blade of the sacrificial material with a narrow gap remaining in the structural layer where the blade of sacrificial material was removed.

Abstract: The present invention provides a method of manufacturing a semiconductor element having a miniaturized structure and a semiconductor device in which the semiconductor element having a miniaturized structure is integrated highly, by overcoming reduction of the yield caused by alignment accuracy, accuracy of a processing technique by reduced projection exposure, a finished dimension of a resist mask, an etching technique and the like. An insulating film covering a gate electrode is formed, and a source region and a drain region are exposed, a conductive film is formed thereover, a resist having a different film thickness is formed by applying the resist over the conductive film, the entire surface of the resist is exposed to light and developed, or the entire surface of the resist is etched to form a resist mask, and the conductive film is etched by using the resist mask to form a source and drain electrode.

Abstract: A method for manufacturing a color filter having a picture element part surrounded by a partition wall and provided in the plural number on a substrate including a step of forming the partition wall that has a lyophobic quality on the substrate, step of forming a lyophilic layer in the picture element part by applying a lyophilic liquid that develops the lyophobic quality to a substantially whole surface of the substrate on which the partition wall is formed all at once and a step of applying a droplet of colorant to the picture element part in which the lyophilic layer is formed.

Abstract: A semiconductor device includes a transmission power amplifier having cascaded MOSFET amplification stages disposed over a main surface of a semiconductor substrate. A CMOSFET control circuit controls the amplification stages. A first capacitor is also provided having upper and lower metal film electrodes formed over the main surface of the semiconductor substrate. The amplification stages are electrically coupled to one another via an inter-stage matching circuit which includes the first capacitor.

Abstract: A method for etching a trench is provided. The method initiates with providing a substrate having a patterned feature. The method includes alternating between deposition of a protective layer onto inner surfaces of the patterned feature and etching the trench into the substrate. The alternating may be achieved through a gas modulation technique and in one embodiment, the deposition and the etching are performed in the same chamber, i.e., the substrate does not move to a different chamber between the etch and deposition processes. The alternating is continued until the trench is completed and then the trench is filled. A semiconductor processing system is also provided.

Abstract: A method including introducing a dielectric layer over a substrate between an interconnection line and the substrate, the dielectric layer comprising a plurality of alternating material layers; and patterning an interconnection to the substrate. An apparatus comprising a substrate comprising a plurality of devices formed thereon; and an interlayer dielectric layer comprising a base layer and a cap layer, the cap layer comprising a plurality of alternating material layers overlying the substrate.