Abstract: A method of fabricating an inductor (70) in a silicon substrate (10), wherein an Argon implantation step (84) is performed after the resist layer (82) has been deposited and the polysilicon layer (30) has been etched, but before the resist layer (82) is stripped and the polysilicon annealed. Thus, an amorphous layer (86) is created on the substrate (10) so as to improve the Q factor of the inductor (70), without the need for an additional masking step or adverse impact on the polysilicon layer (30).

Abstract: An electronic circuit includes a filtering circuit implemented with a distributed inductor-and-capacitor (LC) network that includes metal oxide effect (MOS) trenches opened in a semiconductor substrate filled with dielectric material for functioning as capacitors for the distributed LC network. The electronic circuit further includes a transient voltage suppressing (TVS) circuit integrated with the filtering circuit that functions as a low pass filter wherein the TVS circuit includes a bipolar transistor triggered by a diode disposed in the semiconductor substrate. The distributed LC network further includes metal coils to function as inductors disposed on a top surface of the semiconductor electrically contacting the MOS trenches.

Abstract: The bow in a wafer that results from fabricating a large number of MEMS devices on the top surface of the passivation layer of the wafer so that a MEMS device is formed over each die region is reduced by forming a stress relief layer between the passivation layer and the MEMS devices.

Abstract: A scalable MEMS inductor is formed on the top surface of a semiconductor die. The MEMS inductor includes a plurality of magnetic lower laminations, a circular trace that lies over and spaced apart from the magnetic lower laminations, and a plurality of upper laminations that lie over and spaced apart from the circular trace.

Abstract: A process for the realization of a high integration density power MOS device includes the following steps of: providing a doped semiconductor substrate with a first type of conductivity; forming, on the substrate, a semiconductor layer with lower conductivity; forming, on the semiconductor layer, a dielectric layer of thickness comprised between 3000 and 13000 A (Angstroms); depositing, on the dielectric layer, a hard mask layer; masking the hard mask layer by means of a masking layer; etching the hard mask layers and the underlying dielectric layer for defining a plurality of hard mask portions to protect said dielectric layer; removing the masking layer; isotropically and laterally etching said dielectric layer forming lateral cavities in said dielectric layer below said hard mask portions; forming a gate oxide of thickness comprised between 150 and 1500 A (Angstroms) depositing a conductor material in said cavities and above the same to form a recess spacer, which is totally aligned with a gate structure c

Abstract: A multilayer winding inductor. The inductor at least includes multi-level interconnect and single-level interconnect structures. The multi-level interconnect structure includes a plurality of conductive plugs and a plurality of looped conductive traces overlapping and separated from each other. Each looped conductive trace has a gap to define first and second ends and at least two conductive plugs disposed between the neighboring looped conductive traces. The single-level interconnect structure is located over the multi-level interconnect structure, comprising an uppermost looped conductive trace and a second conductive plug. The uppermost looped conductive trace has a gap to define first and second ends, and the second conductive plug is disposed between the second end of the uppermost looped conductive trace and the first end of the looped conductive trace adjacent thereto, thereby electrically connecting the multi-level and single-level interconnect structures.

Abstract: A semiconductor structure. The semiconductor structure includes: a substrate having a metal wiring level within the substrate; a capping layer on and above the substrate; an insulative layer on and above the capping layer; a first layer of photo-imagable material on and above the insulative layer; a layer of oxide on and above the first layer of photo-imagable material; a second layer of photo-imagable material on and above the layer of oxide; an inductor; and a wire bond pad. A first portion of the inductor is in the second layer of photo-imagable material, the layer of oxide, the first layer of photo-imagable material, the insulative layer, and the capping layer. A second portion of the inductor is in only the second layer of photo-imagable material. The wire bond pad in only the first layer of photo-imagable material, the insulative layer, and the capping layer.

Abstract: A semiconductor configuration having an integrated coupler is provided. The semiconductor configuration includes a coupler which is integrated in the substrate and which includes a first port and a second port. The coupler defines, in a plan view onto the substrate, an inner region of the substrate surrounded at least in sections by the coupler, and an outer region of the substrate arranged outside to the coupler. The coupler is at least a magnetic coupler, a capacitive coupler, or a combination of both. At least a circuit element is integrated in the inner region of the substrate and includes a port which is electrically connected to the second port of the coupler.

Abstract: A semiconductor device including inductors with improved reliability and a method of manufacturing the same are provided. The semiconductor device may include a substrate, an insulating film pattern formed on the substrate and having an opening, an amorphous metal nitride film formed inside the opening, a diffusion reducing or preventing film formed on the amorphous metal nitride film, and a conductive film including the diffusion reducing or preventing film filling the inside of the opening.

Abstract: In accordance with the invention, there are inductors with an air gap, semiconductor devices, integrated circuits, and methods of fabricating them. The method of making an inductor with an air gap can include fabricating a first level of inductor in an intra-metal dielectric layer including one or more inductor loops, one or more vias, and one or more copper bulkhead structures, forming an inter-level dielectric layer over the first level and repeating the steps to form two or more levels of inductor. The method can also include forming an extraction via, forming an air gap between the inductor loops by removing portions of the intra-metal dielectric layer coupled to the extraction via using super critical fluid process, and forming a non-conformal layer to seal the extraction via.

Abstract: Methods and associated structures of forming microelectronic devices are described. Those methods may include forming a first layer of magnetic material and at least one via structure disposed in a first dielectric layer, forming a second dielectric layer disposed on the first magnetic layer, forming at least one conductive structure disposed in the second dielectric layer, forming a third layer of dielectric material disposed on the conductive structure, forming a second layer of magnetic material disposed in the third layer of dielectric material and in the second layer of dielectric material, wherein the first and second layers of the magnetic material are coupled to one another.

Abstract: Manufacturing an inductor includes forming a spiral metal wire on a semiconductor substrate; forming a connection hole exposing a portion of the metal wire by selectively etching a first dielectric film formed to bury the metal wire, and forming a first metal film on the first dielectric film on which the connection hole is formed; forming a second dielectric film on the first metal film; and forming a first photoresist film for forming a second metal wire corresponding to the spiral metal wire on the second dielectric film, and forming the second metal wire by selectively etching the second dielectric film and the first metal film using the first photoresist pattern as an etching mask; wherein the second dielectric film prevents an etching of the top of the second metal wire resulting from the difference in etch rate between the first photoresist pattern and first metal film.

Abstract: Semiconductor package assemblies having integrated circuits mounted onto passive electrical components. The assemblies each include an inductor having a magnetic core and an wire wrapped around the magnetic core. An integrated circuit die is positioned either on or within a recess formed in the magnetic core of the inductor. Electrical traces are formed on the magnetic core. The electrical traces are configured to electrically couple the inductive wire of the inductor with the integrated circuit die positioned on or recessed within the inductor.

Abstract: A method for manufacturing passive components is disclosed. First, a substrate is provided, and a connecting region, a capacitor region and an inductance region are defined in the substrate. The substrate includes a first metal layer and an insulating layer on the first metal layer. Subsequently, the insulating layer is etched, and then the first metal layer is etched. Thus, an outer connecting pad in the connecting region and a bottom electrode in the capacitor region are formed simultaneously, and a part of the insulating layer on the bottom electrode remains. Thereafter, a dielectric layer is deposited, and then a dual damascene copper process is performed to form an inductance structure and a top electrode of a capacitor in the dielectric layer simultaneously. Next, a passive layer is deposited and an etching process is thereafter performed to expose the outer connecting pad.

Abstract: A method for fabricating an inductor structure having an increased quality factor (Q) is provided. In one embodiment, a substrate is provided over which a spirally patterned conductor layer is formed to produce a planar spiral inductor. A via hole is formed in the substrate within the spirally patterned conductor layer, the via hole being formed by through silicon via (TSV). Thereafter, the via hole is filled with a core layer, wherein the core layer extends from a bottom surface of the substrate to a top surface thereof.

Abstract: A manufacturing method of a semiconductor device with a copper redistribution line, a copper inductor and aluminum wire bond pads and the integration of the resulting device with an integrated circuit on a single chip, resulting in the decreased size of the chip.

Abstract: Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip inductors formed on the chip backside and connected to integrated circuits on the chip frontside using through-wafer interconnects. For example, a semiconductor device with a backside integrated inductor includes a semiconductor substrate having a frontside, a backside and a buried insulating layer interposed between the front and backsides of the substrate. An integrated circuit is formed on the frontside of the semiconductor substrate and an integrated inductor is formed on the backside of the semiconductor substrate. An interconnection structure is formed through the buried insulating layer to connect the integrated inductor to the integrated circuit. The semiconductor substrate may be an SOI (silicon on insulator) structure.

Abstract: A miniature inductor suitable for integrated circuits comprises a semiconductor substrate having a coplanar strip line and a plurality of metal-insulator-metal (MIM) capacitors, wherein the plurality of MIM capacitors are connected between the transmission lines of the coplanar strip line in parallel, and the coplanar strip line connected with the MIM capacitors further comprises a crossed planar strip line structure or a shifted planar strip line structure. The present invention reduces the occupied area for an inductor by adding the MIM capacitors and folding the transmission lines, and alleviates the quality factor degradation of the inductor caused by substrate loss.

Abstract: A semiconductor device has a substrate with an inductor formed on its surface. First and second contact pads are formed on the substrate. A passivation layer is formed over the substrate and first and second contact pads. An insulating layer is formed over the passivation layer. The insulating layer is removed over the first contact pad, but not from the second contact pad. A metal layer is formed over the first contact pad. The metal layer is coiled on the surface of the substrate to produce inductive properties. The formation of the metal layer involves use of a wet etchant. The second contact pad is protected from the wet etchant by the insulating layer. The insulating layer is removed from the second contact pad after forming the metal layer over the first contact pad. An external connection is formed on the second contact pad.

Abstract: A line structure is provided which includes a ferroelectric film which is formed on at least one surface of both sides of a substrate and a permittivity of which changes according to a magnitude of an applied voltage, an inductor which is formed on a first side of the substrate, and a capacitor which has a capacitance corresponding to the permittivity of the ferroelectric film and the substrate.

Abstract: An electronic device can include an inductor overlying a shock-absorbing layer. In one aspect, the electronic device can include a substrate, an interconnect level overlying the substrate, and the shock-absorbing layer overlying the interconnect level. The inductor can include conductive traces and looped wires. The conductive traces can be attached to the conductive traces over the shock-absorbing layer. In another aspect, a process can be used to form the electronic device including the inductor. In still another aspect, an electronic device can a toroidal-shaped inductor that includes linear inductor segments that are connected in series.

Abstract: In a semiconductor device having a WCSP type construction package, to increase inductance without increasing further an area conventionally occupied by a coil. A pseudo-post part 27 comprising a magnetic body is extended in a direction perpendicular to a main surface 12a of a semiconductor chip 12, on a second insulating layer 21 of a WCSP 10. A first conductive part 15a and a second conductive part 15b constructed as square frames are respectively provided so as to surround the pseudo-post part, on respective top surfaces of a second insulation layer and a third insulating layer 22 which are separated parallel to each other, in an extension direction of the pseudo-post part. A coil 100 being a substantially spiral shape conductive path is formed from, the first conductive part, the second conductive part, and a connection part 26 which electrically connects the one ends of the first and second conductive parts.

Abstract: A very, very low resistance micro-electromechanical system (MEMS) inductor, which provides resistance in the single-digit milliohm range, is formed by utilizing a single thick wide loop of metal formed around a magnetic core structure. The magnetic core structure, in turn, can utilize a laminated Ni—Fe structure that has an easy axis and a hard axis.

Abstract: A semiconductor device including an inductor and a fabricating method thereof are provided. The semiconductor device can include a connection wiring provided on a semiconductor substrate; a metal wiring provided on an insulating layer in a spiral shape and electrically connected to the connection wiring; and holes provided in the insulating layer and between the metal wiring and the silicon substrate.

Abstract: An inductor of a semiconductor device and a method for manufacturing the same are disclosed. The inductor has a spiral structure, and includes a semiconductor substrate formed with a sub-structure. At least one metal line layer may be formed over the semiconductor substrate. At least one inductor line layer may be formed over the metal line layer. A space layer may be formed between the inductor line layer and the semiconductor substrate.

Abstract: An improved electromagnetic shielding structure has been discovered. In one embodiment of the invention, an apparatus includes an inductor and an electrically conductive enclosure that electromagnetically shields the inductor. The electrically conductive enclosure has an aperture at least as large as the inductor. The aperture is substantially centered around a projected surface of the inductor. The apparatus may include one or more electrically conductive links extending across the aperture and electrically coupled to the electrically conductive enclosure. The electrically conductive links reduce an effect of electromagnetic signals external to the electrically conductive enclosure on the inductor.

Abstract: A method of fabricating an inductor in a semiconductor device is disclosed. Embodiments include forming a first metal wire in a trench formed by etching a layer of a semiconductor substrate, forming an insulating layer over the substrate including the first metal wire, forming a via hole by etching the insulating layer to expose a portion of the first metal wire, forming a plated layer by electroplating to partially fill the via hole with the plated layer, and forming a second metal wire over the insulating layer including the plated layer.

Abstract: Provided is a three-dimensional aluminum package module including: an aluminum substrate; an aluminum oxide layer formed on the aluminum substrate and having at least one first opening of which sidewalls are perpendicular to an upper surface of the aluminum substrate; a semiconductor device mounted in the first opening using an adhesive; an organic layer covering the aluminum oxide layer and the semiconductor device; and a first interconnection line and a passive device circuit formed on the organic layer and the aluminum oxide layer.

Abstract: A transformer comprises a substrate comprising a semiconductor material, a first conductor over the substrate, a second conductor over the substrate, and a magnetic layer over the substrate. The first conductor defines a generally spiral-shaped signal path having at least one turn. The second conductor defines a generally spiral-shaped signal path having at least one turn.

Abstract: A method of manufacturing a semiconductor device including at least one of the following steps: Forming an insulating film having at least one trench on and/or over a semiconductor substrate. Forming a metal film on and/or over a surface of an insulating film, including inside the trench. Forming a metal seed layer on and/or over the metal film inside the trench. Forming a metal plating layer on and/or over the metal seed layer to fill the trench.

Abstract: A circuit system includes: forming a first electrode over a substrate; applying a dielectric layer over the first electrode and the substrate; forming a second electrode over the dielectric layer; and forming a dielectric structure from the dielectric layer with the dielectric structure within a first horizontal boundary of the first electrode.

Abstract: In accordance with the invention, there are inductors with an air gap, semiconductor devices, integrated circuits, and methods of fabricating them. The method of making an inductor with an air gap can include fabricating a first level of inductor in an intra-metal dielectric layer including one or more inductor loops, one or more vias, and one or more copper bulkhead structures, forming an inter-level dielectric layer over the first level and repeating the steps to form two or more levels of inductor. The method can also include forming an extraction via, forming an air gap between the inductor loops by removing portions of the intra-metal dielectric layer coupled to the extraction via using super critical fluid process, and forming a non-conformal layer to seal the extraction via.

Abstract: Systems and methods associated with semiconductor articles are disclosed, including forming a first layer of material on a substrate, etching trenches within regions defining a passive element in the first layer, forming metal regions on sidewalls of the trenches, and forming a region of dielectric or polymer material over or in the substrate. Moreover, an exemplary method may also include forming areas of metal regions on the sidewalls of the trenches such that planar strip portions of the areas form electrically conductive regions of the passive element(s) that are aligned substantially perpendicularly with respect to a primary plane of the substrate. Other exemplary embodiments may comprise various articles or methods including capacitive and/or inductive aspects, Titanium- and/or Tantalum-based resistive aspects, products, products by processes, packages and composites consistent with one or more aspects of the innovations set forth herein.

Abstract: An inductor formed on a semiconductor substrate is provided in the present invention. The inductor includes a metal layer and an insulator layer. The metal layer constitutes the coil of the inductor. The insulator layer includes at least one insulator slot, and each insulator slot is encompassed in the metal layer.

Abstract: A method of forming a semiconductor substrate. A substrate is provided. At least one metal wiring level is within the substrate. A first insulative layer is deposited on a surface of the substrate. A portion of a wire bond pad is formed within the first insulative layer. A second insulative layer is deposited on the first insulative layer. An iductor is within the second insulative layer using a patterned plate process. A remaining portion of the wire bond pad is formed within the second insulative layer, wherein at least a portion of the wire bond pad is substantially co-planar with the inductor.

Abstract: A hybrid method of fabricating magnetic core elements of an on-chip inductor structure addresses issues associated with conventional bottom up and damascene magnetic core plating techniques. The process uses two seed layers: a low resistance seed layer that solves the IR drop problem associated with the damascene plating techniques and a high resistance seed layer that is local to magnetic core features thus avoiding eddy current related performance degradation associated with the bottom up techniques.

Abstract: Integrated circuit inductors (5) are formed by interconnecting various metal layers (10) in an integrated circuit with continuous vias (200). Using continuous vias (200) improves the Q factor over existing methods for high frequency applications. The contiguous length of the continuous vias should be greater than three percent of the length of the inductor (5).

Abstract: A transformer system includes a package substrate having a surface. A plurality of electrically conductive pads are arranged in spaced apart relationship relative to each other on the substrate surface. A first winding is defined by a first electrically conductive path between a first input and a first output, the first electrically conductive path including at least one wire connected between at least one first pad pair of the electrically conductive pads. At least one electrically conductive pad of each first pad pair is at the substrate surface. A second winding is defined by a second electrically conductive path between a second input and a second output, the second electrically conductive path including at least one wire connected between at least one second pad pair of the electrically conductive pads. At least one electrically conductive pad of each second pad pair is at the substrate surface.

Abstract: Disclosed herein is a method of forming an inductor in a semiconductor device, the method including forming an etching-prevention film, a first interlayer insulating film, and a first hard mask film over a silicon semiconductor substrate in this sequence; selectively etching the first hard mask film to form a hole; forming a second interlayer insulating film over the first hard mask film; forming a second hard mask film over the second interlayer insulating film; forming a photoresist pattern having a trench forming opening over the second hard mask film; removing a part of the second hard mask film and a part of the second interlayer insulating film by using the photoresist pattern as an etching mask, to form a first trench in the second interlayer insulating film; removing the photoresist pattern and polymers produced in the first trench by ashing and cleaning process; etching the second interlayer insulating film by using the second hard mask film as an etching mask until the first hard mask film is expose

Abstract: According to one example embodiment, an inductive element is used for power-conversion applications. The inductive element includes a substrate (188) having a first metal layer (190) on the substrate having a thickness greater than one micrometer and arranged as a first set of adjacent non-intersecting conducting segments. There is a ferromagnetic-based body (192) located on the first metal layer that has a ferromagnetic inner core area. At least one other metal layer (198) is on the ferromagnetic-based body and arranged as a second set of adjacent non-intersecting conducting segments. A plurality of conductive vias (194) are located in the ferromagnetic-based body and are arranged to connect respective ones of the first set of adjacent non-intersecting conducting segments to respective ones of the second set of adjacent non-intersecting conducting segments therein providing a contiguous conductive wrap around the inner core area.

Abstract: A method for forming and packaging an integrated circuit having a plurality of circuit components on a semi conductive substrate die. The plurality of circuit components include at least one active component that operates on an information signal, a tuning node coupled to the at least one active component, an Electro Static Discharge (ESD) protection inductor, and a chip pad. The chip pad couples to the tuning node. The ESD protection inductor communicatively couples between the tuning node and a rail formed on the semi conductive substrate die. The ESD protection inductor provides ESD protection prior to packaging of the semi conductive substrate die or in some cases prior to the installation of the packaged die on a PC board or the equivalent. The bond wire couples between the chip pad and a package pad and serves as a tuning inductor for the circuit.

Abstract: A semiconductor device includes a stack structure in which multiple channel layers are stacked on a substrate so as to be sandwiched between bit line layers, a gate electrode that is provided to the side of the lateral surface of an interior of a groove portion formed within the stack structure, and a charge storage layer that is provided between the gate electrode and the channel layer.

Abstract: The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting discrete electrical components at a significant distance removed from the underlying silicon surface.

Abstract: A method for generating metal ions by sputtering a metal target (56) by plasma, attracting the metal ions by bias power to a target object S which is to be processed and is mounted on a mounting table (20) in a processing vessel, and depositing a metal film (74) on the target object having a recess (2) thus filling the recess. The bias power is set to realize such a state as the metal deposition rate by attraction of metal ions is substantially balanced with the etching rate of plasma sputter etching on the surface of the target object. Consequently, the recess in the target object can be filled with metal without causing such a defect as void.

Abstract: An inductor layout and manufacturing method thereof are provided. The inductor layout includes a substrate and a conductive path. The substrate includes at least an active region, wherein the active region includes at least a circuit. The conductive path is disposed over the substrate and arranged near the edge of the active region along the direction of the edge of the active region. Wherein, two ends of the conductive path are the two ends of the inductor.

Abstract: A method is provided for fabricating a microelectronic chip which includes a passive device such, as an inductor, overlying an air gap. In such method, a plurality of front-end-of-line (“FEOL”) devices are formed in a semiconductor region of the microelectronic chip, and a plurality of stacked interlevel dielectric (“ILD”) layers are formed to overlie the plurality of FEOL devices, the plurality of stacked ILD layers including a first ILD layer and a second ILD layer, where the second ILD layer is resistant to attack by a first etchant which attacks the first ILD layer. A passive device is formed to overlie at least the first ILD layer. Using the first etchant, a portion of the first ILD layer in registration with the passive device is removed to form an air gap which underlies the passive device in registration with the passive device.

Abstract: Integrated circuit inductors (5) are formed by interconnecting various metal layers (10) in an integrated circuit with continuous vias (200). Using continuous vias (200) improves the Q factor over existing methods for high frequency applications. The contiguous length of the continuous vias should be greater than three percent of the length of the inductor (5).

Abstract: A method of forming a high performance inductor comprises providing a substrate; forming a plurality of wiring levels over the substrate, wherein each of the wiring levels comprise a dielectric layer; forming a first trench having a first depth in a first dielectric layer on a first wiring level; forming a second trench in the first dielectric layer having a second depth extending at least into a second wiring level; forming a conductor layer substantially simultaneously in the first and second trenches; and removing portions of the conductor layer overfilling the first and second trenches to form a spiral-shaped inductor in the second trench. The method may further comprise forming an interconnect structure in the first trench.

Abstract: A planar inductor comprises a metal element (11-14) on a substrate (300, 310), said metal element being provided with at least one groove (20) extending along and into said element from at least one surface (2) of said element. Said groove or grooves (20) extend into the element in a direction substantially perpendicular to the surface of the substrate (300, 310), giving rise to a higher Q value and a lower serial resistance are also achieved. The inductor may comprise grooved (11, 13, 14) and non-grooved (12) layers. The invention also relates to a method of manufacturing the inductor.

Abstract: An integrated electronic circuit chip having an inductor placed above a protective layer for the metallization levels of the chip, the inductor having a thickness in a direction perpendicular to a surface of a substrate of the chip. The inductor has a reduced electrical resistance and a high quality factor. In addition, an inductor is realized at the same time as the pads for connecting the chip to a supporting board using flip-chip technology.