Abstract: A stacked non-volatile memory device uses amorphous silicon based thin film transistors stacked vertically. Each layer of transistors or cells is formed from a deposited a-Si channel region layer having a predetermined concentration of carbon to form a carbon rich silicon film or silicon carbide film, depending on the carbon content. The dielectric stack is formed over the channel region layer. In one embodiment, the dielectric stack is an ONO structure. The control gate is formed over the dielectric stack. This structure is repeated vertically to form the stacked structure. In one embodiment, the carbon content of the channel region layer is reduced for each subsequently formed layer.

Abstract: A silicon carbide semiconductor device includes a substrate, a drift layer located on a first surface of the substrate, a base region located on the drift layer, a source region located on the base region, a trench sandwiched by each of the base region to the drift layer, a channel layer located in the trench, a gate insulating layer located on the channel layer, a gate electrode located on the gate insulating layer, a source electrode electrically coupled with the source region and the base region, a drain electrode located on a second surface of the substrate, and a deep layer located under the base region and extending to a depth deeper than the trench. The deep layer is formed into a lattice pattern.

Abstract: A semiconductor device includes a substrate formed of a single crystal. a silicon carbide layer disposed on a surface of the single crystal substrate and an intermediate layer disposed on a surface of the silicon carbide layer and formed of a Group III nitride semiconductor, wherein the silicon carbide layer is formed of a cubic crystal stoichiometrically containing silicon copiously and the surface thereof has a (3×3) reconstruction structure.

Abstract: A method for fabricating a semiconductor device utilizing the step of forming a first insulating film of a porous material over a substrate; the step of forming on the first insulating film a second insulating film containing a silicon compound containing Si—CH3 bonds by 30-90%, and the step of irradiating UV radiation with the second insulating film formed on the first insulating film to cure the first insulating film. Thus, UV radiation having the wavelength which eliminates CH3 groups is sufficiently absorbed by the second insulating film, whereby the first insulating film is highly strengthened with priority by the UV cure, and the first insulating film can have the film density increased without having the dielectric constant increased.

Abstract: A semiconductor device includes: a semiconductor substrate of silicon carbide of a first conductivity type; a silicon carbide epitaxial layer of the first conductivity type, which has been grown on the principal surface of the substrate; well regions of a second conductivity type, which form parts of the silicon carbide epitaxial layer; and source regions of the first conductivity type, which form respective parts of the well regions. A channel epitaxial layer of silicon carbide is grown over the well regions and source regions of the silicon carbide epitaxial layer. A portion of the channel epitaxial layer located over the well regions functions as a channel region. A dopant of the first conductivity type is implanted into the other portions and of the channel epitaxial layer except the channel region.

Abstract: A method of growing polygonal carbon from photoresist and resulting structures are disclosed. Embodiments of the invention provide a way to produce polygonal carbon, such as graphene, by energizing semiconductor photoresist. The polygonal carbon can then be used for conductive paths in a finished semiconductor device, to replace the channel layers in MOSFET devices on a silicon carbide base, or any other purpose for which graphene or graphene-like carbon material formed on a substrate is suited. In some embodiments, the photoresist layer forms both the polygonal carbon layer and an amorphous carbon layer over the polygonal carbon layer, and the amorphous carbon layer is removed to leave the polygonal carbon on the substrate.

Abstract: Self-aligned fabrication of silicon carbide semiconductor devices is a desirable technique enabling reduction in the number of photolithographic steps, simplified alignment of different device regions, and reduced spacing between the device regions. This invention provides a method of fabricating silicon carbide (SiC) devices utilizing low temperature selective epitaxial growth which allows avoiding degradation of many masking materials attractive for selective epitaxial growth. Another aspect of this invention is a combination of the low temperature selective epitaxial growth of SiC and self-aligned processes.

Abstract: A gate structure is formed on a substrate. An insulating interlayer is formed covering the gate structure. The substrate is heat treated while exposing a surface of the insulating interlayer to a hydrogen gas atmosphere. A silicon nitride layer is formed directly on the interlayer insulating layer after the heat treatment and a metal wiring is formed on the insulating interlayer. The metal wiring may include copper. Heat treating the substrate while exposing a surface of the interlayer insulating layer to a hydrogen gas atmosphere may be preceded by forming a plug through the first insulating interlayer that contacts the substrate, and the metal wiring may be electrically connected to the plug. The plug may include tungsten.

Abstract: Copper diffusion barrier films having low dielectric constants are suitable for a variety of copper/inter-metal dielectric integration schemes. Copper diffusion barrier films in accordance with the invention are composed of one or more layers of silicon carbide, at least one of the silicon carbide layers having a composition of at least 40% carbon (C), for example, between about 45 and 60% carbon (C). The films' high carbon-content layer will have a composition wherein the ratio of C to Si is greater than 2:1; or >3:1; or >4:1; or >5.1. The high carbon-content copper diffusion barrier films have a reduced effective k relative to conventional barrier materials.

Abstract: In a first aspect, a method of forming an epitaxial film on a substrate is provided. The method includes (a) providing a substrate; (b) exposing the substrate to a silicon source and a carbon source so as to form a carbon-containing silicon epitaxial film; (c) encapsulating the carbon-containing silicon epitaxial film with an encapsulating film; and (d) exposing the substrate to Cl2 so as to etch the encapsulating film. Numerous other aspects are provided.

Abstract: In an atmosphere in which a silicon carbide (SiC) substrate implanted with impurities is annealed to activate the impurities, by setting a partial pressure of H2O to be not larger than 10?2 Pa, preferably not larger than 10?3 Pa, surface irregularity of the silicon carbide (SiC) substrate is controlled to be not greater than 2 nm, more preferably not greater than 1 nm in RMS value.

Abstract: Silicon carbide metal-oxide semiconductor field effect transistors (MOSFETs) may include an n-type silicon carbide drift layer, a first p-type silicon carbide region adjacent the drift layer and having a first n-type silicon carbide region therein, an oxide layer on the drift layer, and an n-type silicon carbide limiting region disposed between the drift layer and a portion of the first p-type region. The limiting region may have a carrier concentration that is greater than the carrier concentration of the drift layer. Methods of fabricating silicon carbide MOSFET devices are also provided.

Abstract: A SiC semiconductor device includes: a SiC substrate; a SiC drift layer on the substrate having an impurity concentration lower than the substrate; a semiconductor element in a cell region of the drift layer; an outer periphery structure including a RESURF layer in a surface portion of the drift layer and surrounding the cell region; and an electric field relaxation layer in another surface portion of the drift layer so that the electric field relaxation layer is separated from the RESURF layer. The electric field relaxation layer is disposed on an inside of the RESURF layer so that the electric field relaxation layer is disposed in the cell region. The electric field relaxation layer has a ring shape.

Abstract: A semiconductor device includes a semiconductor substrate, a cell region, an outer peripheral region, a field plate, an outermost peripheral ring, outer peripheral region layer, an insulator film, and a Zener diode. The semiconductor substrate has a superjunction structure. The outer peripheral region is disposed at an outer periphery of the cell region. The Zener diode is disposed on the insulator film for electrically connecting the field plate with the outermost peripheral ring. The Zener diode has a first conductivity type region and a second conductivity type region that are alternately arranged in a direction from the cell region to the outer peripheral region.

Abstract: A silicon carbide semiconductor device comprising a region of germanium and a region of crystalline or polycrystalline silicon carbide. The germanium region and the silicon carbide region are configured to form a germanium/silicon carbide heterojunction.

Abstract: A display device having a thin film semiconductor device including a semiconductor thin film having first and second semiconductor regions formed each into a predetermined shape above an insulative substrate, a conductor fabricated into a predetermined shape to the semiconductor thin film and a dielectric film put between the semiconductor thin film and the conductor, in which the semiconductor thin film is a polycrystal thin film with the crystallization ratio thereof exceeding 90% and the difference of unevenness on the surface of the semiconductor thin film does not exceed 10 nm.

Abstract: Provided is an image sensor having a heterojunction bipolar transistor (HBT) and a method of fabricating the same. The image sensor is fabricated by SiGe BiCMOS technology. In the image sensor, a PD employs a floating-base-type SiGe HBT. A floating base of the SiGe HBT produces a positive voltage with respect to a collector during an exposure process, and the HBT performs a reverse bipolar operation due to the positive voltage so that the collector and an emitter exchange functions. The SiGe HBT can sense an optical current signal and also amplify the optical current signal. The image sensor requires only three transistors in a pixel so that the degree of integration can increase. The image sensor has an improved sensitivity of signals in the short wavelength region and a sensing signal has excellent linearity such that both a sensing mechanism and control circuit are very simple.

Abstract: Embodiments of the invention relate generally to semiconductors and semiconductor fabrication techniques, and more particularly, to devices, integrated circuits, substrates, and methods to form silicon carbide structures, including doped epitaxial layers (e.g., P-doped silicon carbide epitaxial layers), by supplying sources of silicon and carbon with sequential emphasis. In some embodiments, a method of forming an epitaxial layer of silicon carbide can include depositing a layer in the presence of a silicon source, and purging gaseous materials subsequent to depositing the layer. Further, the method can include converting the layer into a sub-layer of silicon carbide in the presence of a carbon source and a dopant, and purging other gaseous materials. In some embodiments, the presence of the silicon source can be independent of the presence of the carbon source and/or the dopant.

Abstract: A complementary metal-oxide-semiconductor (CMOS) optical sensor structure includes a pixel containing a charge collection well of a same semiconductor material as a semiconductor layer in a semiconductor substrate and at least another pixel containing another charge collection well of a different semiconductor material than the material of the semiconductor layer. The charge collections wells have different band gaps, and consequently, generate charge carriers in response to light having different wavelengths. The CMOS sensor structure thus includes at least two pixels responding to light of different wavelengths, enabling wavelength-sensitive, or color-sensitive, capture of an optical data.

Abstract: An embodiment of a process for forming an interface between a silicon carbide (SiC) layer and a silicon oxide (SiO2) layer of a structure designed to conduct current is disclosed. A first epitaxial layer having a first doping level is homo-epitaxially grown on a substrate. The homo-epitaxial growth is preceded by growing, on the first epitaxial layer, a second epitaxial layer having a second doping level higher than the first doping level. Finally, the second epitaxial layer is oxidized so as to be totally removed. Thereby, a silicon oxide layer of high quality is formed, and the interface between the second epitaxial layer and silicon oxide has a low trap density.

Abstract: A method is set forth of forming an ohmic electrode having good characteristics on a SiC semiconductor layer. In the method, a Ti-layer and an Al-layer are formed on a surface of the SiC substrate. The SiC substrate having the Ti-layer and the Al-layer is maintained at a temperature that is higher than or equal to a first temperature and lower than a second temperature until all Ti in the Ti-layer has reacted with Al. The first temperature is the minimum temperature of a temperature zone at which the Ti reacts with the Al to form Al3Ti, and the second temperature is the minimum temperature of a temperature zone at which the Al3Ti reacts with SiC to form Ti3SiC2. As a result of this maintaining of temperature step, an Al3Ti-layer is formed on the surface of the SiC substrate. The method also comprises further heating the SiC substrate having the Al3Ti-layer to a temperature that is higher than the second temperature.

Abstract: A unit cell of a metal-semiconductor field-effect transistor (MESFET) includes a semi-insulating substrate having a surface, an implanted n-type channel region in the substrate, and implanted source and drain regions extending from the surface of the substrate into the implanted channel region. A gate contact is between the source and the drain regions, and an implanted p-type region is beneath the source region. The implanted p-type region has an end that extends towards the drain region, is spaced apart vertically from the implanted channel layer, and is electrically coupled to the source region. Methods of forming transistors including implanted channels and implanted p-type regions beneath the source region are also disclosed.

Abstract: A semiconductor device and a method of manufacturing the device using a (000-1)-faced silicon carbide substrate are provided. A SiC semiconductor device having a high blocking voltage and high channel mobility is manufactured by optimizing the heat-treatment method used following the gate oxidation. The method of manufacturing a semiconductor device includes the steps of forming a gate insulation layer on a semiconductor region formed of silicon carbide having a (000-1) face orientation, forming a gate electrode on the gate insulation layer, forming an electrode on the semiconductor region, cleaning the semiconductor region surface. The gate insulation layer is formed in an atmosphere containing 1% or more H2O (water) vapor at a temperature of from 800° C. to 1150° C. to reduce the interface trap density of the interface between the gate insulation layer and the semiconductor region.

Abstract: There is provided a method for modifying a high-k dielectric thin film provided on the surface of an object using a metal organic compound material. The method includes a preparation process for providing the object with the high-k dielectric thin film formed on the surface thereof, and a modification process for applying UV rays to the highly dielectric thin film in an inert gas atmosphere while maintaining the object at a predetermined temperature to modify the high-k dielectric thin film. According to the above constitution, the carbon component can be eliminated from the high-k dielectric thin film, and the whole material can be thermally shrunk to improve the density, whereby the occurrence of defects can be prevented and the film density can be improved to enhance the specific permittivity and thus to provide a high level of electric properties.

Abstract: A method of forming an interconnect structure, comprising forming a first interconnect layer (123) embedded in a first dielectric layer (118), forming a dielectric tantalum nitride barrier (150) by means of atomic layer deposition on the surface of the first interconnect (123), depositing a second dielectric layer (134) over the first interconnect (123) and the barrier (150) and etching a via (154) in the dielectric layer (134) to the barrier (150). The barrier (150) is then exposed to a treatment through the via (154) to change it from the dielectric phase to the conductive phase (180) and the via (154) is subsequently filled with conductive material (123).

Abstract: A structure and method for a silicon carbide (SiC) gate turn-off (GTO) thyristor device operable to provide an increased turn-off gain comprises a cathode region, a drift region having an upper portion and a lower portion, wherein the drift region overlies the cathode region, a gate region overlying the drift region, an anode region overlying the gate, and at least one ohmic contact positioned on each of the gate region, anode region, and cathode region, wherein the upper portion of the drift region, the gate region, and the anode region have a free carrier lifetime and mobility lower than a comparable SiC GTO thyristor for providing the device with an increased turn-off gain, wherein the free carrier lifetime is approximately 10 nanoseconds. The reduced free carrier lifetime and mobility are affected by altering the growth conditions, such as temperature under which epitaxy occurs.

Abstract: Disclosed are embodiments of field effect transistors (FETs) having suppressed sub-threshold corner leakage, as a function of channel material band-edge modulation. Specifically, the FET channel region is formed with different materials at the edges as compared to the center. Different materials with different band structures and specific locations of those materials are selected in order to effectively raise the threshold voltage (Vt) at the edges of the channel region relative to the Vt at the center of the channel region and, thereby to suppress of sub-threshold corner leakage. Also disclosed are design structures for such FETs and method embodiments for forming such FETs.

Abstract: A method for improving the quality of a SiC layer by effectively reducing or eliminating the carrier trapping centers by high temperature annealing and a SiC semiconductor device fabricated by the method. The method for improving the quality of a SiC layer by eliminating or reducing some carrier trapping centers includes the steps of: (a) carrying out ion implantation of carbon atom interstitials (C), silicon atoms, hydrogen atoms, or helium atoms into a shallow surface layer (A) of the starting SiC crystal layer (E) to introduce excess carbon interstitials into the implanted surface layer, and (b) heating the layer for making the carbon interstitials (C) to diffuse out from the implanted surface layer (A) into a bulk layer (E) and for making the electrically active point defects in the bulk layer inactive. After the above steps, the surface layer (A) can be etched or mechanically removed. The SiC semiconductor device is fabricated by the method.

Abstract: An SiC semiconductor device and a related manufacturing method are disclosed having a structure provided with a p+-type deep layer formed in a depth equal to or greater than that of a trench to cause a depletion layer between at a PN junction between the p+-type deep layer and an n?-type drift layer to extend into the n?-type drift layer in a remarkable length, making it difficult for a high voltage, resulting from an adverse affect arising from a drain voltage, to enter a gate oxide film. This results in a capability of minimizing an electric field concentration in the gate oxide film, i.e., an electric field concentration occurring at the gate oxide film at a bottom wall of the trench.

Abstract: A semiconductor device and a manufacturing method thereof uses a semiconductor substrate of silicon carbide. On one principal surface side of the substrate, at its central section, a layer of silicon carbide or gallium nitride as a semiconductor layer having the thickness at least necessary for breakdown voltage blocking is epitaxially grown or formed from part of the substrate. A recess is formed in the other principal surface side of substrate at a position facing the central section. A supporting section surrounds the bottom of the recess and provides the side face of the recess. The recess is formed by processing such as dry etching. The semiconductor device, even though the semiconductor substrate is made thinner for the realization of small on-resistance, can maintain the strength of the semiconductor substrate capable of reducing occurrence of a wafer cracking during the manufacturing process.

Abstract: A semiconductor device includes a first conductor disposed on a semiconductor substrate; an oxygen-containing insulation film disposed on the semiconductor substrate and on the first conductor, the insulation film having a contact hole which extends to the first conductor and a trench which is connected to an upper portion of the contact hole; a zirconium oxide film disposed on a side surface of the contact hole and a side surface and a bottom surface of the trench; a zirconium film disposed on the zirconium oxide film inside the contact hole and inside the trench; and a second conductor composed of Cu embedded into the contact hole and into the trench.

Abstract: With a view to preventing increases in forward voltage due to a change with the lapse of time of a bipolar semiconductor device using a silicon carbide semiconductor, a buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on a growth surface, which is given by a surface of a crystal of a silicon carbide semiconductor having an off-angle ? of 8 degrees from a (000-1) carbon surface of the crystal, at a film growth rate having a film-thickness increasing rate per hour h of 10 ?m/h, which is three times or more higher than conventional counterparts. The flow rate of silane and propane material gases and dopant gases is largely increased to enhance the film growth rate.

Abstract: A process is described for producing silicon carbide crystals having increased minority carrier lifetimes. The process includes the steps of heating and slowly cooling a silicon carbide crystal having a first concentration of minority carrier recombination centers such that the resultant concentration of minority carrier recombination centers is lower than the first concentration.

Abstract: A single crystal SiC substrate is produced with low cost in which a polycrystalline SiC substrate with relatively low cost is used as a base material substrate where the single crystal SiC substrate has less strain, good crystallinity and large size. The method including a P-type ion introduction step for implanting P-type ions from a side of a surface Si layer 3 into an SOI substrate 1 in which the surface Si layer 3 and an embedded oxide layer 4 having a predetermined thickness are foamed on an Si base material layer 2 to convert the embedded oxide layer 4 into a PSG layer 6 to lower a softening point, and an SiC forming step for heating the SOI substrate 1 having the PSG layer 6 formed therein in an atmosphere of hydrocarbon-based gas to convert the surface Si layer 3 into SiC, and thereafter, cooling the resulting substrate to foam a single crystal SiC layer 5 on a surface thereof.

Abstract: LED devices and methods for making such devices are provided. One such method may include forming epitaxially a substantially single crystal SiC layer on a substantially single crystal Si wafer, forming epitaxially a substantially single crystal diamond layer on the SiC layer, doping the diamond layer to form a conductive diamond layer, removing the Si wafer to expose the SiC layer opposite to the conductive diamond layer, forming epitaxially a plurality of semiconductor layers on the SiC layer such that at least one of the semiconductive layers contacts the SiC layer, and coupling an n-type electrode to at least one of the semiconductor layers such that the plurality of semiconductor layers is functionally located between the conductive diamond layer and the n-type electrode.

Abstract: Stress is exerted to the SiC crystal in the region, in which the carriers of a SiC semiconductor device flow, to change the crystal lattice intervals of the SiC crystal. Since the degeneration of the conduction bands in the bottoms thereof is dissolved, since the inter-band scattering is prevented from causing, and since the effective electron mass is reduced due to the crystal lattice interval change, the carrier mobility in the SiC crystal is improved, the resistance of the SiC crystal is reduced and, therefore, the on-resistance of the SiC semiconductor device is reduced.

Abstract: Semiconductor devices and methods for making such devices are provided. One such method may include forming an epitaxial layer of single crystal SiC on a single crystal Si growth substrate, forming an epitaxial diamond layer on the layer of SiC, forming a Si layer on the diamond layer, bonding a SiO2 surface of a Si carrier substrate to the Si layer, and removing the Si growth substrate to expose the SiC layer. In yet another aspect, a semiconductor layer may be deposited onto the SiC layer. The semiconductor layer may further be deposited epitaxially.

Abstract: A method for fabricating a SiC MOSFET is disclosed. The method includes growing a SiC epilayer over a substrate, planarizing the SiC epilayer to provide a planarized SiC epilayer, and forming a gate dielectric layer in contact with the planarized epilayer.

Abstract: By forming a stressed semiconductor material in a gate electrode, a biaxial tensile strain may be induced in the channel region, thereby significantly increasing the charge carrier mobility. This concept may be advantageously combined with additional strain-inducing sources, such as embedded strained semiconductor materials in the drain and source regions, thereby providing the potential for enhancing transistor performance without contributing to process complexity.

Abstract: By recessing portions of the drain and source areas on the basis of a spacer structure, the subsequent implantation process for forming the deep drain and source regions may result in a moderately high dopant concentration extending down to the buried insulating layer of an SOI transistor. Furthermore, the spacer structure maintains a significant amount of a strained semiconductor alloy with its original thickness, thereby providing an efficient strain-inducing mechanism. By using sophisticated anneal techniques, undue lateral diffusion may be avoided, thereby allowing a reduction of the lateral width of the respective spacers and thus a reduction of the length of the transistor devices. Hence, enhanced charge carrier mobility in combination with reduced junction capacitance may be accomplished on the basis of reduced lateral dimensions.

Abstract: An epitaxial crystal for a field effect transistor which has a nitride-based III-V group semiconductor epitaxial crystal grown on a SiC single crystal base substrate having micropipes by use of an epitaxial growth method, wherein at least a part of the micropipes spreading from the SiC single crystal base substrate into the epitaxial crystal terminate between an active layer of the transistor and the SiC single crystal base substrate.

Abstract: An insulated gate bipolar transistor (IGBT) includes a first conductivity type substrate and a second conductivity type drift layer on the substrate. The second conductivity type is opposite the first conductivity type. The IGBT further includes a current suppressing layer on the drift layer. The current suppressing layer has the second conductivity type and has a doping concentration that is larger than a doping concentration of the drift layer. A first conductivity type well region is in the current suppressing layer. The well region has a junction depth that is less than a thickness of the current suppressing layer, and the current suppressing layer extends laterally beneath the well region. A second conductivity type emitter region is in the well region.

Abstract: In an SiC vertical MOSFET comprising a channel region and an n-type inverted electron guide path formed through ion implantation in a low-concentration p-type deposition film, the width of the channel region may be partly narrowed owing to implantation mask positioning failure, and the withstand voltage of the device may lower, and therefore, the device could hardly satisfy both low on-resistance and high withstand voltage. In the invention, second inverted layers (41, 42) are provided at the same distance on the right and left sides from the inverted layer (40) to be the electron guide path in the device, and the inverted layers are formed through simultaneous ion implantation using the same mask, and accordingly, the length of all the channel regions in the device is made uniform, thereby solving the problem.

Abstract: A semiconductor manufacturing apparatus and substrate processing method includes a step of acquiring a measurement value based on a first detecting and a second detecting section and determining a first difference of measurement values between the first detecting section and the second detecting section, comparing between a previously stored second difference between measurement values concerning the first detecting section and the second detecting section, calculating a correction value for a pressure in a cooling-gas passage provided between a process chamber and a heating device depending upon the first difference when the first difference is different from the second difference, and correcting the pressure value based on the pressure correction value, and a step of processing the substrate by flowing a cooling gas through the cooling-gas passage while heating the process chamber, and placing the heating device and the cooling device under a control section depending upon a pressure value corrected.

Abstract: In one aspect the present invention provides a method for manufacturing a silicon carbide semiconductor device. A layer of silicon dioxide is formed on a silicon carbide substrate and nitrogen is incorporated at the silicon dioxide/silicon carbide interface. In one embodiment, nitrogen is incorporated by annealing the semiconductor device in nitric oxide or nitrous oxide. In another embodiment, nitrogen is incorporated by annealing the semiconductor device in ammonia.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a SiC film, forming trenches at a surface of the SiC film, heat-treating the SiC film with silicon supplied to the surface of the SiC film, and obtaining a plurality of macrosteps to constitute channels, at the surface of the SiC film by the step of heat-treating. Taking the length of one cycle of the trenches as L and the height of the trenches as h, a relation L=h(cot ?+cot ?) (where ? and ? are variables that satisfy the relations 0.5??,?,?45) holds between the length L and the height h. Consequently, the semiconductor device can be improved in property.

Abstract: A method of producing a silicon carbide semiconductor device, including: step (A) of forming an impurity-doped region by implanting impurity ions 3 into at least a portion of a silicon carbide layer 2 formed on a first principal face of a silicon carbide substrate 1 having first and second principal faces; step (B) of forming capping layers 6 having thermal resistance on at least an upper face 2a of the silicon carbide layer 2 and on at least a second principal face 12a of the silicon carbide substrate 1; and step (C) of performing an activation annealing treatment by heating the silicon carbide layer 2 at a predetermined temperature.

Abstract: A method of manufacturing a silicon carbide semiconductor device having a MOS structure includes preparing a substrate made of silicon carbide, and forming a channel region, a first impurity region, a second impurity region, a gate insulation layer, and a gate electrode to form a semiconductor element on the substrate. In addition, a film is formed on the semiconductor element to provide a material of an interlayer insulation layer, and a reflow process is performed at a temperature about 700° C. or over in an wet atmosphere so that the interlayer insulation layer is formed from the film and an edge portion of the gate electrode is rounded and oxidized.

Abstract: Method for forming a structure provided with at least one zone of one or several semiconductor nanocrystals (13). It consists in: exposing with a beam of electrons (11) at least one zone (12) of a semiconductor film (1) lying on an electrically insulating support (2), the exposed zone (12) contributing to defining at least one dewetting zone (10) of the film (1), annealing the film (1) at high temperature in such a way that the dewetting zone (10) retracts giving the zone of one or several nanocrystals (13).

Abstract: A method for manufacturing an ion implantation mask is disclosed which includes the steps of: forming an oxide film as a protective film over the entire surface of a semiconductor substrate; forming a thin metal film over the oxide film; and forming an ion-inhibiting layer composed of an ion-inhibiting metal over the thin metal film. The obtained ion implantation mask is used to form a deeper selectively electroconductive region.