Abstract: An electronic device includes a silicon carbide drift region having a first conductivity type, a Schottky contact on the drift region, and a plurality of junction barrier Schottky (JBS) regions at a surface of the drift region adjacent the Schottky contact. The JBS regions have a second conductivity type opposite the first conductivity type and have a first spacing between adjacent ones of the JBS regions. The device further includes a plurality of surge protection subregions having the second conductivity type. Each of the surge protection subregions has a second spacing between adjacent ones of the surge protection subregions that is less than the first spacing.

Abstract: Stacked gate structures for a NAND string are created on a substrate. Source implantations are performed at a first implantation angle to areas between the stacked gate structures. Drain implantations are performed at a second implantation angle to areas between the stacked gate structures. The drain implantations create lower doped regions of a first conductivity type in the substrate on drain sides of the stacked gate structures. The source implantations create higher doped regions of the first conductivity type in the substrate on source sides of the stacked gate structures.

Abstract: A method is disclosed for doping a target area of a semiconductor substrate, such as a source or drain region of a transistor, with an electronically active dopant (such as an N-type dopant used to create active areas in NMOS devices, or a P-type dopant used to create active areas in PMOS devices) having a well-controlled placement profile and strong activation. The method comprises placing a carbon-containing diffusion suppressant in the target area at approximately 50% of the concentration of the dopant, and activating the dopant by an approximately 1,040 degree Celsius thermal anneal. In many cases, a thermal anneal at such a high temperature induces excessive diffusion of the dopant out of the target area, but this relative concentration of carbon produces a heretofore unexpected reduction in dopant diffusion during such a high-temperature thermal anneal.

Abstract: A method for fabricating an NMOS transistor is disclosed. First, a substrate having a gate structure thereon is provided. A carbon implantation process is performed thereafter by implanting carbon atoms into the substrate for forming a silicon carbide region in the substrate. Subsequently, a source/drain region is formed surrounding the gate structure. By conducting a carbon implantation process into the substrate and a corresponding amorphorized implantation process before or after the carbon implantation process is completed, the present invention eliminates the need of forming a recess for accommodating an epitaxial layer composed of silicon carbide while facilitates the formation of silicon carbide from the combination of both implantation processes.

Abstract: Stacked gate structures for a NAND string are created on a substrate. Source implantations are performed at a first implantation angle to areas between the stacked gate structures. Drain implantations are performed at a second implantation angle to areas between the stacked gate structures. The drain implantations create lower doped regions of a first conductivity type in the substrate on drain sides of the stacked gate structures. The source implantations create higher doped regions of the first conductivity type in the substrate on source sides of the stacked gate structures.

Abstract: In a production process for a semiconductor device employing an SiC semiconductor substrate (1), the SiC semiconductor substrate (1) is mounted on a susceptor (23), and a C heating member (3) of carbon is placed on a surface of the SiC semiconductor substrate (1). An annealing process is performed to form an impurity region in the surface of the SiC semiconductor substrate (1) by causing the susceptor (23) and the C heating member (3) to generate heat at high temperatures.

Abstract: A method for epitaxially forming a first semiconductor structure attached to a second semiconductor structure is provided. Devices and methods described include advantages such as reduced lattice mismatch at an epitaxial interface between two different semiconductor materials. One advantageous application of such an interface includes an electrical-optical communication structure. Methods such as deposition of layers at an elevated temperature provide easy formation of semiconductor structures with a modified lattice constant that permits an improved epitaxial interface.

Abstract: A doping method comprising the steps of; obtaining a proportion X of ions of a compound including a donor or an acceptor impurity in total ions from mass spectrum by using a first source gas of a first concentration; analyzing a peak concentration Y of the compound in a first processing object which is doped by using a second source gas of a second concentration equal to or lower than the first concentration, referring to a dose amount of total ions as D0 and setting an acceleration voltage at a value, obtaining a dose amount D1 of total ions from a expression, Y=(D1/D0)(aX+b), and doping a second processing object with the donor or the acceptor impurity by a ion doping apparatus using a third source gas, wherein a dose amount of total ions is set at D1, and an acceleration voltage is set at the value.

Abstract: A method and device for reducing a dopant diffusion rate in a doped semiconductor region is provided. The methods and devices include selecting a plurality of impurity elements, including at least one dopant element. Selection of a plurality of impurity elements includes selecting a first impurity element with a first atomic radius larger than an average host matrix atomic radius and selecting a second impurity element with a second atomic radius smaller than an average host matrix atomic radius. The methods and devices further include selecting amounts of each impurity element of the plurality of impurity elements wherein amounts and atomic radii of each of the plurality of impurity elements complement each other to reduce a host matrix lattice strain.

Abstract: A method and device for reducing a dopant diffusion rate in a doped semiconductor region is provided. The methods and devices include selecting a plurality of impurity elements, including at least one dopant element. Selection of a plurality of impurity elements includes selecting a first impurity element with a first atomic radius larger than an average host matrix atomic radius and selecting a second impurity element with a second atomic radius smaller than an average host matrix atomic radius. The methods and devices further include selecting amounts of each impurity element of the plurality of impurity elements wherein amounts and atomic radii of each of the plurality of impurity elements complement each other to reduce a host matrix lattice strain.

Abstract: The invention relates to a method for generating very short gate structures. In a method for generating a structure on a substrate in accordance with one embodiment of the invention, first of all a layer sequence of a first oxide layer, a first nitride layer and a second oxide layer is disposed onto the substrate. Subsequently, a portion of the second oxide layer and a portion of the first nitride layer is removed in order to expose a portion of the first oxide layer. Then, a part of the first nitride layer above the first oxide layer and below the second oxide layer is removed in order to expose the area of the structure.

Abstract: An impurity can be introduced into a semiconductor layer of a workpiece to affect the oxidation and the relative concentration of one element with respect to another element within the semiconductor layer. The impurity can be selectively implanted using one or more masks, manipulating the beam line of an ion implant tool, moving a workpiece relative to the ion beam, or the like. The dose can vary as a function of distance from the center of the workpiece or vary locally based on the design of the electronic device or desires of the electronic device fabricator. In one embodiment, the impurity can be implanted in such a way as to result in a more uniform SiGe condensation across the substrate or across one or more portions of the substrate when the semiconductor layer includes a SiGe layer.

Abstract: A system and method for suppressing sub-oxide formation during the manufacturing of semiconductor devices (such as MOSFET transistor) with high-k gate dielectric is disclosed. In one example, the MOSFET transistor includes a gate structure including a high-k gate dielectric and a gate electrode. In this example, the gate structure is covered with a nitride layer that is used to prevent oxygen from entering the structure during processing, yet is sufficiently thin to be effectively transparent to the processing.

Abstract: A structure (and method for forming the structure) includes a photodetector, a substrate formed under the photodetector, and a barrier layer formed over the substrate. The buried barrier layer preferably includes a single or dual p-n junction, or a bubble layer for blocking or eliminating the slow photon-generated carriers in the region where the drift field is low.

Abstract: A method of manufacturing semiconductor devices includes forming element isolation regions in a semiconductor substrate, a gate insulation film in an element region surrounded by the element isolation regions and an impurity doped metal silicide film on the gate insulation film; irradiating energy beams to heat the silicide film; forming a gate electrode film by patterning the silicide film; and forming source and drain regions by doping an impurity into said element region by using at least the gate electrode film as a mask.