Abstract: A semiconductor layer structure may include a substrate, a buffer layer formed on the substrate, and a set of epitaxial layers formed on the buffer layer. The buffer layer may have a thickness that is greater than 2 micrometers (?m). The set of epitaxial layers may include a quantum well layer. A quantum well intermixing region may be formed in association with the quantum well layer and a material diffused from a region of a surface of the semiconductor layer structure.

Abstract: A method of forming a strained channel for a field effect transistor, including forming a sacrificial layer on a substrate, forming a channel layer on the sacrificial layer, forming a stressor layer on the channel layer, wherein the stressor layer applies a stress to the channel layer, forming at least one etching trench by removing at least a portion of the stressor layer, channel layer, and sacrificial layer, wherein the etching trench exposes at least a portion of a sidewall of the sacrificial layer, and separates the stressor layer, channel layer, and sacrificial layer into two or more stressor islands, channel blocks, and sacrificial slabs, and removing the sacrificial slabs to release the channel blocks from the substrate using a selective etch, wherein the channel blocks adhere to the substrate surface.

Abstract: Provided is a light emitting device, which includes a second conductive type semiconductor layer, an active layer, a first conductive type semiconductor layer, and a intermediate refraction layer. The active layer is disposed on the second conductive type semiconductor layer. The first conductive type semiconductor layer is disposed on the active layer. The intermediate refraction layer is disposed on the first conductive type semiconductor layer. The intermediate refraction layer has a refractivity that is smaller than that of the first conductive type semiconductor layer and is greater than that of air.

Abstract: Disclosed are methods for preparing a resistive random-access memory (ReRAM) based on resistive switching using a resistance-switchable conductive filler. When a resistance-switchable conductive filler prepared by coating a conductive filler with a material whose resistance is changeable is mixed with a dielectric material, the dielectric material is given the resistive switching characteristics without losing its inherent properties. Therefore, various resistance-switchable materials having various properties can be prepared by mixing the resistance-switchable conductive filler with different dielectric materials. The resulting resistance-switchable material shows resistive switching characteristics comparable to those of the existing metal oxide film-based resistance-switchable materials. Accordingly, a ReRAM device having the inherent properties of a dielectric material can be prepared using the resistance-switchable conductive filler.

Abstract: A compound semiconductor device includes: a substrate; a GaN compound semiconductor multilayer structure disposed over the substrate; and a stress relief layer which is AlN-based and which is disposed between the substrate and the GaN compound semiconductor multilayer structure, wherein a surface of the stress relief layer that is in contact with the GaN compound semiconductor multilayer structure includes recesses that have a depth of 5 nm or more and that are formed at a number density of 2×1010 cm?2 or more.

Abstract: A method for forming a selective ohmic contact for a Group III-nitride heterojunction structured device may include forming a conductive layer and a capping layer on an epitaxial substrate including at least one Group III-nitride heterojunction layer and having a defined ohmic contact region, the capping layer being formed on the conductive layer or between the conductive layer and the Group III-nitride heterojunction layer in one of the ohmic contact region and non-ohmic contact region, and applying at least one of a laser annealing process and an induction annealing process on the substrate at a temperature of less than or equal to about 750° C. to complete the selective ohmic contact in the ohmic contact region.

Abstract: Provided is a light emitting device, which includes a second conductive type semiconductor layer, an active layer, a first conductive type semiconductor layer, and a intermediate refraction layer. The active layer is disposed on the second conductive type semiconductor layer. The first conductive type semiconductor layer is disposed on the active layer. The intermediate refraction layer is disposed on the first conductive type semiconductor layer. The intermediate refraction layer has a refractivity that is smaller than that of the first conductive type semiconductor layer and is greater than that of air.

Abstract: A phase change memory device and an associated method of making same are presented. The phase change memory device, includes first wiring lines, second wiring lines, memory cells, and conduction contacts. The first wiring lines are arranged substantially in parallel to each other so that the first wiring lines are grouped into odd and even numbered first wiring lines. The memory cells are coupled to the first and second wiring lines. The conduction contacts coupled to the first wiring lines so that only one conduction contact is coupled to a center of a corresponding odd numbered first wiring line. Also only two corresponding conduction contacts are coupled to opposing edges of a corresponding even numbered first wiring line. Accordingly, the conduction contacts are arranged on the first wiring lines so that conduction contacts are not adjacent to each other with respect to immediately adjacent first wiring lines.

Abstract: A semiconductor device has a satisfactory ohmic contact on a p-type principal surface tilting from a c-plane. The principal surface 13a of a p-type semiconductor region 13 extends along a plane tilting from a c-axis (axis <0001>) of hexagonal group-III nitride. A metal layer 15 is deposited on the principal surface 13a of the p-type semiconductor region 13. The metal layer 15 and the p-type semiconductor region 13 are separated by an interface 17 such that the metal layer functions as a non-alloy electrode. Since the hexagonal group-III nitride contains gallium as a group-III element, the principal surface 13a comprising the hexagonal group-III nitride is more susceptible to oxidation compared to the c-plane of the hexagonal group-III nitride. The interface 17 avoids an increase in amount of oxide after the formation of the metal layer 15 for the electrode.

Abstract: Methods of depositing a III-V semiconductor material on a substrate include sequentially introducing a gaseous precursor of a group III element and a gaseous precursor of a group V element to the substrate by altering spatial positioning of the substrate with respect to a plurality of gas columns. For example, the substrate may be moved relative to a plurality of substantially aligned gas columns, each disposing a different precursor. Thermalizing gas injectors for generating the precursors may include an inlet, a thermalizing conduit, a liquid container configured to hold a liquid reagent therein, and an outlet. Deposition systems for forming one or more III-V semiconductor materials on a surface of the substrate may include one or more such thermalizing gas injectors configured to direct the precursor to the substrate via the plurality of gas columns.

Abstract: Programmable metallization memory cells having a first metal contact and a second metal contact with an ion conductor solid electrolyte material between the metal contacts. The first metal contact has a filament placement structure thereon extending into the ion conductor material. In some embodiments, the second metal contact also has a filament placement structure thereon extending into the ion conductor material toward the first filament placement structure. The filament placement structure may have a height of at least about 2 nm.

Abstract: A semiconductor structure is provided. The semiconductor structure includes one or more III-IV material-based semiconductor layers. A tensile-strained Ge layer is formed on the one or more a III-IV material-based semiconductor layers. The tensile-strained Ge layer is produced through lattice-mismatched heteroepitaxy on the one or more a III-IV material-based semiconductor layers.

Abstract: Disclosed herein is a high-quality group III-nitride semiconductor thin film and group III-nitride semiconductor light emitting device using the same. To obtain the group III-nitride semiconductor thin film, an AlInN buffer layer is formed on a (1-102)-plane (so called r-plane) sapphire substrate by use of a MOCVD apparatus under atmospheric pressure while controlling a temperature of the substrate within a range from 850 to 950 degrees Celsius, and then, GaN-based compound, such as GaN, AlGaN or the like, is epitaxially grown on the buffer layer at a high temperature. The group III-nitride semiconductor light emitting device is fabricated by using the group III-nitride semiconductor thin film as a base layer.

Abstract: A memory device may include a switching device and a storage node coupled with the switching device. The storage node may include a first electrode, a second electrode, a data storage layer and at least one contact layer. The data storage layer may be disposed between the first electrode and the second electrode and may include a transition metal oxide or aluminum oxide. The at least one contact layer may be disposed at least one of above or below the data storage layer and may include a conductive metal oxide.

Abstract: Various methods and devices are implemented using efficient silicon compatible integrated light communicators. According to one embodiment of the present invention, a semiconductor device is implemented for communicating light, such as by detecting, modulating or emitting light. The device has a silicon-seeding location, an insulator layer and a second layer on the insulator layer. The second layer includes a silicon-on-insulator region and an active region surrounded by the silicon-on-insulator region and connected to the silicon-seeding location. The active region includes a single-crystalline germanium-based material that extends from the silicon-seeding location through a passageway with a cross-sectional area that is sufficiently small to mitigate crystalline growth defects.

Abstract: A thick gallium nitride (GaN) film is formed on a LiAlO2 substrate through two stages. First, GaN nanorods are formed on the LiAlO2 substrate through chemical vapor deposition (CVD). Then the thick GaN film is formed through hydride vapor phase epitaxy (HVPE) by using the GaN nanorods as nucleus sites. In this way, a quantum confined stark effect (QCSE) becomes small and a problem of spreading lithium element into gaps in GaN on using the LiAlO2 substrate is mended.

Abstract: A semiconductor film is formed on a GaAs substrate (semiconductor substrate). An SiO2 film (insulating film) is formed on the semiconductor film, and the SiO2 film is patterned. The semiconductor film is etched using the SiO2 film as a mask to form a mesa structure. The surface of the SiO2 film is treated by ashing, using SF6 gas (fluorine-containing gas), to terminate the surface of the SiO2 film with fluorine. The mesa structure is selectively buried with a III-V compound semiconductor film, using the SiO2 film having the surface that has been terminated by fluorine, as a mask.

Abstract: A semiconductor device having a capacitor and a method of fabricating the same may be provided. A method of fabricating a semiconductor device may include forming an etch stop layer and a mold layer sequentially on a substrate, patterning the mold layer to form a mold electrode hole exposing a portion of the etch stop layer, etching selectively the exposed etch stop layer by an isotropic dry etching process to form a contact electrode hole through the etch stop layer to expose a portion of the substrate, forming a conductive layer on the substrate and removing the conductive layer on the mold layer on the mold layer to form a cylindrical bottom electrode in the mold and contact electrode holes. The isotropic dry etching process may utilize a process gas including main etching gas and selectivity adjusting gas. The selectivity adjusting gas may increase an etch rate of the etch stop layer by more than an etch rate of the mold layer by the isotropic wet etching process.

Abstract: A semiconductor laser element having an advantageous vertical light confinement efficiency, a low threshold current and a low element resistance is provided. The semiconductor laser element has a substrate and a stacked structure formed thereon, where the stacked structure comprises a buffer layer, an n-Al0.6Ga0.4As cladding layer, an n-Al0.47Ga0.53As cladding layer, an active layer, a p-Al0.47Ga0.53As first cladding layer, an Al0.55Ga0.45As etching stop layer, a p-Al0.47Ga0.53As second cladding layer, a p-Al0.6Ga0.4As third cladding layer, and a p-GaAs contact layer. The second and third cladding layers, and the contact layer are formed as a stripe-patterned ridge, and serve as a current injection regions. Both lateral portions of the ridge are filled with an n-type current blocking layer and serve as non-current-injection regions.

Abstract: A method of fabricating a semiconductor device having high output power and excellent long-term reliability by preventing thermal adverse influence exerted at the time of window structure formation is provided. The method comprises a 1st step of forming predetermined semiconductor layers 2 to 9 containing at least an active layer 4b consisting of a quantum well active layer on a semiconductor substrate 1; a 2nd step of forming a first dielectric film 10 on a first portion of the surface of the semiconductor layers 2 to 9; a 3rd step of forming a second dielectric film 12 made of the same material as that of the first dielectric film 10 and having a density lower than that of the first dielectric film 10 on a second portion of the surface of the semiconductor layers 2 to 9; and a 4th step of heat-treating a multilayer body containing the semiconductor layers 2 to 9, the first dielectric film 10, and the second dielectric film 12 to disorder the quantum well layer below the second dielectric film 12.

Abstract: A semiconductor device, includes: a first conductivity type semiconductor base having a main face; a hetero semiconductor region contacting the main face of the semiconductor base and forming a hetero junction in combination with the semiconductor base, the semiconductor base and the hetero semiconductor region in combination defining a junction end part; a gate insulating film defining a junction face in contact with the semiconductor base and having a thickness; and a gate electrode disposed adjacent to the junction end part via the gate insulating film and defining a shortest point in a position away from the junction end part by a shortest interval, a line extending from the shortest point to a contact point vertically relative to the junction face, forming such a distance between the contact point and the junction end part as to be smaller than the thickness of the gate insulating film contacting the semiconductor base.

Abstract: A base layer, comprising an electrically conductive element, is formed. An upper layer, including a third, lower planarization stop layer, a second layer and a first, upper layer is formed on the base layer. A keyhole opening is formed through the upper layer to expose a surface of an electrically conductive element in the base layer. The first layer has an overhanging portion extending into the opening so that the opening in the first layer is shorter than in the second layer. A dielectric material is deposited into the keyhole opening to create a self-converged void within the deposited dielectric material. In some examples the keyhole forming step comprises increasing the volume of the first layer while in other examples the keyhole forming step comprises etching back the second layer.

Abstract: A nitride semiconductor device, which includes a III-V Group nitride semiconductor layer being composed of a III Group element consisting of at least one of a group containing of gallium, aluminum, boron and indium and V Group element consisting of at least nitrogen among a group consisting of nitrogen, phosphorus and arsenic, including a first nitride semiconductor layer including the III-V Group nitride semiconductor layer being deposited on a substrate, a second nitride semiconductor layer including the III-V Group nitride semiconductor layer being deposited on the first nitride semiconductor and not containing aluminum and a control electrode making Schottky contact with the second nitride semiconductor layer wherein the second nitride semiconductor layer includes a film whose film forming temperature is lower than the first nitride semiconductor layer.

Abstract: A nitride semiconductor device includes: first through third nitride semiconductor layers formed in sequence over a substrate. The second nitride semiconductor layer has a band gap energy larger than that of the first nitride semiconductor layer. The third nitride semiconductor layer has an opening. A p-type fourth nitride semiconductor layer is formed so that the opening is filled therewith. A gate electrode is formed on the fourth nitride semiconductor layer.

Abstract: A semiconductor heterostructure that includes a support substrate with a first in-plane lattice parameter, a buffer structure formed on the support substrate and having on top in a relaxed state a second in-plane lattice parameter, and a multi-layer stack of ungraded layers formed on the buffer structure. This semiconductor hetero-structure possess a lower surface roughness than other heterostructures. In the heterostructure, the ungraded layers are strained layers that comprise at least one strained smoothing layer of a semiconductor material having in a relaxed state a third in-plane lattice parameter which has a value between the first and the second lattice parameter.

Abstract: A base layer, comprising an electrically conductive element, is formed. An upper layer, including a third, lower planarization stop layer, a second layer and a first, upper layer is formed on the base layer. A keyhole opening is formed through the upper layer to expose a surface of an electrically conductive element in the base layer. The first layer has an overhanging portion extending into the opening so that the opening in the first layer is shorter than in the second layer. A dielectric material is deposited into the keyhole opening to create a self-converged void within the deposited dielectric material. In some examples the keyhole forming step comprises increasing the volume of the first layer while in other examples the keyhole forming step comprises etching back the second layer.

Abstract: A light-generating semiconductor region is grown by epitaxy on a silicon substrate. The light-generating semiconductor region is a lamination of layers of semiconducting nitrides containing a Group III element or elements. The silicon substrate has a p-type impurity-diffused layer formed therein by thermal diffusion of the Group III element or elements from the light-generating semiconductor region as a secondary product of the epitaxial growth of this region on the substrate. The p-type impurity-diffused layer is utilized as a part of overvoltage protector diodes which are serially interconnected with each other and in parallel with the LED section of the device between a pair of electrodes.

Abstract: An improved solution for producing nitride-based heterostructure(s), heterostructure device(s), integrated circuit(s) and/or Micro-Electro-Mechanical System(s) is provided. A nitride-based etch stop layer that includes Indium (In) is included in a heterostructure. An adjacent layer of the heterostructure is selectively etched to expose at least a portion of the etch stop layer. The etch stop layer also can be selectively etched. In one embodiment, the adjacent layer can be etched using reactive ion etching (RIE) and the etch stop layer is selectively etched using a wet chemical etch. In any event, the selectively etched area can be used to generate a contact or the like for a device.

Abstract: This invention makes it possible to simplify a process of manufacturing an SOI substrate whose insulator is not exposed to the side surface. The SOI substrate manufacturing method includes a first step of forming a structure (230) in which an insulating layer (204b) and semiconductor layer (203b) are in turn formed on a semiconductor member (211) by bonding a first substrate (210) to a second substrate (220), a second step of making the edge portion of an insulating layer (204b) of the structure (230) retreat toward the center so that the edge portion of a semiconductor layer (203c) overhangs the edge portion of an insulating layer (204c), and a third step of moving atoms which form the edge portion of the semiconductor layer (203c) such that the edge portion of a semiconductor layer (203d) covers the periphery of the insulating layer (204c) and connects to the semiconductor member (211).

Abstract: A method for controlling the color contrast of a multi-wavelength light-emitting diode (LED) made according to the present invention is disclosed. The present invention includes at least the step of increasing the junction temperature of a multi-quantum-well LED, such that holes are distributed in a deeper quantum-well layer of the LED to increase luminous intensity of the deeper quantum-well layer, thereby controlling the relative intensity ratios of the multiple wavelengths emitted by the LED. The step of increasing junction temperature of the multi-quantum-well LED is achieved either by controlling resistance through modulating thickness of a p-type electrode layer of the LED or by modifying the mesa area size to control its relative heat radiation surface area.

Abstract: A method for fabricating a semiconductor device in a semiconductor structure, provides enhanced quantum well intermixing in desired regions of the device by forming a first, relatively high quality, epitaxial layer on a substrate, the high quality layer including a quantum well; forming a second, relatively lower quality, epitaxial defect layer on top of the high quality layer, and thermally processing the structure to effect at least partial diffusion of the defects from the defect layer into the high quality layer in order to achieve quantum well intermixing in the structure. The use of an epitaxially grown defect layer on top of, or within, a high quality epitaxially grown device body enables quantum well intermixing techniques to be performed at lower temperatures and thereby improves device characteristics.

Abstract: A method for bonding microstructures to a semiconductor substrate using attractive forces, such as, hydrophobic, van der Waals, and covalent bonding is provided. The microstructures maintain their absolute position with respect to each other and translate vertically onto a wafer surface during the bonding process. The vertical translation of the micro-slabs is also referred to herein as “in-place bonding”. Semiconductor structures which include the attractively bonded microstructures and substrate are also disclosed.

Abstract: A method of controlling the degree of IFVEI for post-growth tuning of an optical bandgap of a semiconductor heterostructure. The resultant layer structure may contain a semi-conductor heterostructure with one or more regions with selectively modified bandgap. According to one aspect of the invention, a metal interlayer is deposited between the heterostructure and a dielectric layer such as silica. According to another aspect of the invention, an oxidized surface is provided between a dielectric layer and the heterostructure. The presence of the oxide layer improves stability and reproducibility in the post-annealing process. In a further aspect, the oxide layer may be provided between the interlayer and the heterostructure. In one embodiment of the invention, a photoresist mask with a specific pattern is deposited on the surface of the heterostructure so that the interlayer is deposited in an unmasked region whereon post-growth tuning results.