Abstract: An object of the present invention is to provide a simple process to manufacture a wiring connecting photoelectric cells in a photoelectric conversion device. Another object of this invention is to prevent defective rupture from occurring in the said wiring. The photoelectric conversion device comprises a first and a second photoelectric conversion cells comprising respectively a first and a second single crystal semiconductor layers. First electrodes are provided on the downwards surfaces of the first and second photoelectric conversion cells, and second electrodes are provided on their upwards surfaces. The first and second photoelectric conversion cells are fixed onto a support substrate side by side. The second single crystal semiconductor layer has a through hole which reaches the first electrode. The second electrode of the first photoelectric conversion cell is extended to the through hole to be electrically connected to the first electrode of the second photoelectric conversion cell.

Abstract: A semiconductor layer structure includes a donor substrate and a detach region carried by the donor substrate. A device structure is carried by the donor substrate and positioned proximate to the detach region. The device structure includes a stack of crystalline semiconductor layers. The stack of crystalline semiconductor layers includes a pn junction.

Abstract: The invention provides methods of direct bonding substrates at least one of which includes a layer of semiconductor material that extends over its front face or in the proximity thereof. The provided methods include, prior to bonding, subjecting the bonding face of at least one substrate comprising a semiconductor material to selected heat treatment at a selected temperature and in a selected gaseous atmosphere. The bonded substrates are useful for electronic, optic, or optoelectronic applications.

Abstract: A method for manufacturing a semiconductor device, includes: bringing a first major surface of a first substrate into close contact with a second major surface of a second substrate being different in thermal expansion coefficient from the first substrate at a first temperature higher than room temperature; and bonding the first substrate and the second substrate by heating the first substrate and the second substrate to a second temperature higher than the first temperature with the first major surface being in close contact with the second major surface.

Abstract: The present method of manufacturing a group III nitride semiconductor layer bonded substrate includes the steps of: implanting ions I of at least any of hydrogen and helium in a region having a prescribed depth D from one main surface of a group III nitride semiconductor substrate; bonding a different-composition substrate with the main surface of the group III nitride semiconductor substrate; obtaining a group III nitride semiconductor layer bonded substrate by separating the group III nitride semiconductor substrate at a region implanted with the ions I; and annealing the group III nitride semiconductor layer bonded substrate at a temperature not lower than 700° C. in an atmosphere of a nitrogen-containing gas N. Thus, a group III nitride semiconductor layer bonded substrate high in crystallinity of a group III nitride semiconductor layer is provided.

Abstract: A novel semiconductor article manufacturing method and the like are provided. A method of manufacturing a semiconductor article having a compound semiconductor multilayer film formed on a semiconductor substrate includes: preparing a member including an etching sacrificial layer (1010), a compound semiconductor multilayer film (1020), an insulating film (2010), and a semiconductor substrate (2000) on a compound semiconductor substrate (1000), and having a first groove (2005) which passes through the semiconductor substrate and the insulating film, and a semiconductor substrate groove (1025) which is a second groove provided in the compound semiconductor multilayer film so as to be connected to the first groove, and bringing an etchant into contact with the etching sacrificial layer through the first groove and then the second groove and etching the etching sacrificial layer to separate the compound semiconductor substrate from the member.

Abstract: Under consideration here is a method for the production of periodic nanostructuring on one of the surfaces of a substrate (10), presenting a periodic network of dislocations, embedded within a crystalline area (4) located in the neighborhood of an interface (5) between the crystalline material surfaces of two components (1, 2) assembled by bonding to form the substrate (10). It comprises the following steps: formation, in the dislocations (3), of implants (6) made of a material other than that of the crystalline area (4); irradiation of the substrate (10) with electromagnetic waves (11) in order to cause absorption of electromagnetic energy localized in the implants (6), this absorption leading to the appearance of the periodic nanostructuring (12) on the surface of the substrate (10).

Abstract: A method of bonding a semiconductor substrate to a metal substrate is disclosed. In some embodiments the method includes forming a semiconductor device in a semiconductor substrate, the semiconductor device comprising a first surface. The method further includes obtaining a metal substrate. The metal substrate is bonded to the first surface of the semiconductor device, wherein at least a portion of the metal substrate forms an electrical terminal for the semiconductor device.

Abstract: Presented is a method for producing an optoelectronic component. The method includes separating a semiconductor layer based on a III-V-compound semiconductor material from a substrate by irradiation with a laser beam having a plateau-like spatial beam profile, where individual regions of the semiconductor layer are irradiated successively.

Abstract: The invention relates to a method for bonding wafers along their corresponding surfaces.

Abstract: The present invention provides a light-emitting element, a method of manufacturing the light-emitting element, a light-emitting device, and a method of manufacturing the light-emitting device. A method of manufacturing a light-emitting element includes: forming a first conductive layer of a first conductive type, a light-emitting layer, and a second conductive layer of a second conductive type on at least one first substrate, forming an ohmic layer on the second conductive layer and bonding the at least one first substrate to a second substrate. The second substrate being larger than the first substrate. The method further includes etching portions of the ohmic layer, the second conductive layer, and the light-emitting layer to expose a portion of the first conductive layer.

Abstract: According to the present invention, there is provided a method for manufacturing a semiconductor device that includes preparing a first semiconductor substrate and a second semiconductor substrate, forming a first insulating film on a surface of the first semiconductor substrate, forming circuit elements on a first surface of the second semiconductor substrate, grinding a second surface of the second semiconductor substrate, forming a second insulating film on the second surface of the second semiconductor substrate, and bonding the first insulating film and the second insulating film.

Abstract: A semiconductor device includes a substrate which is composed of a zinc oxide semiconductor having a hexagonal crystal structure and includes a first principal surface which is a polar plane; and four side surfaces which are adjacent to the first principal surface, the side surfaces being orthogonal to the principal surface and are at angles of 40 to 50 degrees to a base nonpolar plane orthogonal to the first principal surface; and a semiconductor layer provided on the first principal surface.

Abstract: A method for forming a device wafer with a recyclable support by providing a wafer having first and second surfaces, with at least the first surface of the wafer comprising a semiconductor material that is suitable for receiving or forming electronic devices thereon, providing a supporting substrate having upper and lower surfaces, and providing the second surface of the wafer or the upper surface of the supporting substrate with void features in an amount sufficient to enable a connecting bond therebetween to form a construct wherein the bond is formed at an interface between the wafer and the substrate and is suitable to maintain the wafer and supporting substrate in association while forming or applying electronic devices to the first surface of the wafer, but which connecting bond is severable at the interface due to the void features to separate the substrate from the wafer so that the substrate can be reused.

Abstract: A method for forming an internal electrode pattern having a predetermined shape includes the following: a step of forming a conductive layer by applying a metal paste on a first support, the metal paste containing metal powder and a binder; a step of forming a resin layer on a second support, the resin layer having a pattern negative to the internal electrode pattern; a step of compression bonding the first support and the second support to each other in such a manner that the conductive layer and the resin layer are opposite to each other; and a step of removing the second support from the first support so as to transfer a conductive layer to the second support, the conductive layer having the pattern negative to the internal electrode pattern, thereby forming the internal electrode pattern having the predetermined shape on the first support.

Abstract: A semiconductor donor body is affixed to a receiver element, and a thin semiconductor lamina is cleaved from the donor body, remaining affixed to the receiver element. A photovoltaic assembly is fabricated which includes the lamina and the receiver element, wherein a photovoltaic cell comprises the lamina. The bond between the semiconductor donor body and the receiver element must survive processing to complete the cell, as well as eventual assembly, transport, and operation in a finished photovoltaic module. It has been found that inclusion of a conductive layer such as titanium or aluminum aids bonding between the semiconductor donor body and the receiver element. In some embodiments, the conductive layer may also serve as an electrical contact and/or as a reflective layer.

Abstract: To achieve enlargement and high definition of a display portion, a single crystal semiconductor film is used as a transistor in a pixel, and the following steps are included: bonding a plurality of single crystal semiconductor substrates to a base substrate; separating part of the plurality of single crystal semiconductor substrates to form a plurality of regions each comprising a single crystal semiconductor film over the base substrate; forming a plurality of transistors each comprising the single crystal semiconductor film as a channel formation region; and forming a plurality of pixel electrodes over the region provided with the single crystal semiconductor film and a region not provided with the single crystal semiconductor film. Some of the transistors electrically connecting to the pixel electrodes formed over the region not provided with the single crystal semiconductor film are formed in the region provided with the single crystal semiconductor film.

Abstract: The present invention relates to a flexible single-crystal film and a method of manufacturing the same from a single-crystal wafer. That is, the present invention can manufacture a silicon-on-insulator (SOI) wafer comprising a base wafer, one or more buried insulator layers, and a single-crystal layer into a flexible single-crystal film with a desired thickness by employing various wafer thinning techniques. The method for manufacturing a flexible film comprises the steps of (i) providing a SOI wafer comprising a base wafer, one or more buried insulator layers on the base wafer, and a single-crystal layer on said one or more buried insulator layers, (ii) forming one or more protective insulator layers on said single-crystal layer, (iii) removing said base wafer, and (iv) removing one or more of the insulator layers.

Abstract: A method of fabricating a thin film is disclosed. The method comprises: implanting ions by bombarding a face of a substrate comprising a semiconductor material to form a concentrated layer of the implanted ions at a predetermined mean depth in the substrate, the concentrated layer and the face of the substrate defining a thin film therebetween; trapping contaminants included in the substrate or the thin film, in the concentrated layer by heat treating the substrate such that the heat treatment does not split the substrate at the concentrated layer; detaching the thin film from the substrate after the trapping by splitting the substrate at the concentrated layer; and withdrawing a zone of the thin film perturbed by the trapping and the detaching.

Abstract: A method of manufacturing an integrated circuit including a first isolated chip electrically and mechanically connected via wafer bonding to a second isolated chip, wherein the active faces of the chips face one another, includes: forming metallic contact zones on active faces of first and second wafers, positioning and fixing the wafers one above another at a predetermined distance such that the active faces of the wafers face one another and the contact zones are aligned, placing the fixed wafers in a bath for electroless metal deposition onto the contact zones; and removing the fixed wafers in the event that the metal layers growing on the aligned contact zones of the first and second wafers have grown together.

Abstract: A method of fabricating a hybrid substrate by direct bonding of donor and receiver substrates where each substrate has a respective front face and surface, with the front face of the receiver substrate having a semiconductor material near the surface, and the donor substrate including a zone of weakness that defines a layer to be transferred. The method includes preparing the substrate surfaces by exposing the surface of the receiver substrate to a temperature from about 900° C. to about 1200° C. in an inert atmosphere for at least 30 sec; directly bonding together the front faces of the prepared substrates to form a composite substrate; heat treating the composite substrate to increase bonding strength between the front surfaces of the donor and receiver substrates; and transferring the layer from the donor substrate by detaching the remainder of the donor substrate at the zone of weakness.

Abstract: A semiconductor device including a compound semiconductor laminated structure having a plurality of compound semiconductor layers formed over a semiconductor substrate, a first insulation film covering at least a part of a surface of the compound semiconductor laminated structure, and a second insulation film formed on the first insulation film, wherein the second insulation film includes more hydrogen than the first insulation film.

Abstract: The present invention contemplates preventing clogging of a dicer for forming separation trenches in a semiconductor wafer, and as well improving the yield of a semiconductor device cut out of the semiconductor wafer. A second adhesive to be charged into spaces contains an epoxy material as a base material. Silica filler particles (diameter: about 2 to about 4 ?m) are added to the base material in an appropriate amount. Charging of the second adhesive may be performed by adding the adhesive dropwise to a side wall of a semiconductor wafer, or by immersing an edge of the semiconductor wafer in the adhesive in the form of liquid. When a liquid-form epoxy material of low viscosity is employed, the spaces can be evenly filled with the second adhesive by capillary action. An n-electrode is formed on an exposed surface of an n-type layer through vapor deposition employing a resist mask. Separation trenches are formed through half-cut dicing from the exposed surface of the n-type layer toward the second adhesive.

Abstract: The HVIC includes a dielectric layer and an SOI active layer stacked on a silicon substrate, a transistor formed in the surface of the SOI active layer, and a trench isolation region formed around the transistor. The dielectric layer includes a first buried oxide film formed in the surface of the silicon substrate, a shield layer formed below the first buried oxide film opposite the element area, a second buried oxide film formed around the shield layer, and a third buried oxide film formed below the shield layer and the second buried oxide film. Therefore, the potential distribution curves PC within the dielectric layer are low in density and a high withstand voltage is achieved.

Abstract: The invention includes a semiconductor construction having a wire bonding region associated with a metal-containing layer, and having radiation-imageable material over the metal-containing layer. The radiation-imageable material can be configured as a multi-level pattern having a first topographical region with a first elevational height and a second topographical region with a second elevational height above the first elevational height. The second topographical region can be laterally displaced from the bonding region by at least a lateral width of the first topographical region, with said lateral width being at least about 10 microns. Additionally, or alternatively, the elevational height of the second topographical region can be at least about 2 microns above the elevational height of the first topographical region.

Abstract: Systems, methods and apparatus are provided through which in some embodiments a mass spectrometer micro-leak includes a number of channels fabricated by semiconductor processing tools and that includes a number of inlet holes that provide access to the channels.

Abstract: A method for fabricating III-N semiconductor devices on the N-face of layers comprising (a) growing a III-nitride semiconductor device structure in a Ga-polar direction on a substrate, (b) attaching a Ga face of the III-nitride semiconductor device structure to a host substrate, and (c) removing the substrate to expose the N-face surface of the III-nitride semiconductor device structure. An N-polar (000-1) oriented III-nitride semiconductor device is also disclosed, comprising one or more (000-1) oriented nitride layers, each having an N-face opposite a group III-face, wherein at least one N-face is an at least partially exposed N-face, and a host substrate attached to one of the group III-faces.

Abstract: A method for fabricating germanium-on-insulator (GOI) substrate materials, the GOI substrate materials produced by the method and various structures that can include at least the GOI substrate materials of the present invention are provided. The GOI substrate material include at least a substrate, a buried insulator layer located atop the substrate, and a Ge-containing layer, preferably pure Ge, located atop the buried insulator layer. In the GOI substrate materials of the present invention, the Ge-containing layer may also be referred to as the GOI film. The GOI film is the layer of the inventive substrate material in which devices can be formed.

Abstract: To provide a manufacturing method of a semiconductor device using an SOI substrate, by which mobility can be improved. A plurality of semiconductor films formed using a plurality of bond substrates (semiconductor substrates) are bonded to one base substrate (support substrate). At least one of the plurality of bond substrates has a crystal plane orientation different from that of the other bond substrates. Accordingly, at least one of the plurality of semiconductor films formed over one base substrate has a crystal plane orientation different from that of the other semiconductor films. The crystal plane orientation of the semiconductor film is determined in accordance with the polarity of a semiconductor element formed using the semiconductor film. For example, an n-channel element in which electrons are majority carriers is formed using a semiconductor film having a face {100}, and a p-channel element in which holes are majority carriers is formed using a semiconductor film having a face {110}.

Abstract: Various embodiments of the present invention are related to microresonator systems that can be used as a laser, a modulator, and a photodetector and to methods for fabricating the microresonator systems. In one embodiment, a microresonator system comprises a substrate having a top surface layer, at least one waveguide embedded within the substrate, and a microdisk having a top layer, an intermediate layer, a bottom layer, current isolation region, and a peripheral annular region. The bottom layer of the microdisk is in electrical communication with the top surface layer of the substrate and is positioned so that at least a portion of the peripheral annular region is located above the at least one waveguide. The current isolation region is configured to occupy at least a portion of a central region of the microdisk and has a relatively lower refractive index and relatively larger bandgap than the peripheral annular region.

Abstract: A method for forming a composite substrate structure. The method includes providing a first substrate, the first substrate having a surface region and a backside region, providing a handling substrate, the handling substrate having a bonding surface and a handling surface, and activating at least one of the surface region of the first substrate and the bonding surface of the handling substrate using a surface activation process. The method also includes thereafter contacting the surface region of the first substrate to the bonding surface of the handling substrate to form a composite substrate structure, and thereafter applying a voltage to the backside region and the handling surface of the composite substrate structure. In one embodiment, the step of activating at least one of the surface region of the first substrate and the bonding surface of the handling substrate is performed in a plasma activation chamber.

Abstract: A method of making CMOS devices on strained silicon on glass includes preparing a glass substrate, including forming a strained silicon layer on the glass substrate; forming a silicon oxide layer by plasma oxidation of the strained silicon layer; depositing a layer of doped polysilicon on the silicon oxide layer; forming a polysilicon gate; implanting ions to form a LDD structure; depositing and forming a spacer dielectric on the gate structure; implanting and activation ions to form source and drain structures; depositing a layer of metal film; annealing the layer of metal film to form salicide on the source, drain and gate structures; removing any unreacted metal film; depositing a layer of interlayer dielectric; and forming contact holes and metallizing.

Abstract: Hybrid orientation substrates allow the fabrication of complementary metal oxide semiconductor (CMOS) circuits in which the n-type field effect transistors (nFETs) are disposed in a semiconductor orientation which is optimal for electron mobility and the p-type field effect transistors (pFETs) are disposed in a semiconductor orientation which is optimal for hole mobility. This invention discloses that the performance advantages of FETs formed entirely in the optimal semiconductor orientation may be achieved by only requiring that the device's channel be disposed in a semiconductor with the optimal orientation. A variety of new FET structures are described, all with the characteristic that at least some part of the FET's channel has a different orientation than at least some part of the FET's source and/or drain. Hybrid substrates into which these new FETs might be incorporated are described along with their methods of making.

Abstract: A method for bonding microstructures to a semiconductor substrate using attractive forces, such as, hydrophobic, van der Waals, and covalent bonding is provided. The microstructures maintain their absolute position with respect to each other and translate vertically onto a wafer surface during the bonding process. The vertical translation of the micro-slabs is also referred to herein as “in-place bonding”. Semiconductor structures which include the attractively bonded microstructures and substrate are also disclosed.

Abstract: A method of manufacturing a photodetecting device, by providing a first wafer that includes a photosensitive layer made of a semiconductor material and a second wafer that includes a circuit layer of electronic components, with one of the photosensitive layer or the circuit layer incorporating a field isolation layer; bonding the first and second wafers to form a structure comprising successively the circuit layer, the field isolation layer and the photosensitive layer; and forming electrically conductive vias to electrically connect the photosensitive layer to at least some of the electronic components of the circuit layer. Also, photodetecting devices prepared by these methods.

Abstract: Under consideration here is a method for the production of periodic nanostructuring on one of the surfaces of a substrate (10), presenting a periodic network of dislocations, embedded within a crystalline area (4) located in the neighbourhood of an interface (5) between the crystalline material surfaces of two components (1, 2) assembled by bonding to form the substrate (10). It comprises the following steps: formation, in the dislocations (3), of implants (6) made of a material other than that of the crystalline area (4); irradiation of the sbstrate (10) with electromagnetic waves (11) in order to cause absorption of electromagnetic energy localised in the implants (6), this absorption leading to the appearance of the periodic nanostructuring (12) on the surface of the substrate (10).

Abstract: A high quality bonded substrate is obtained in which generation of microprotrusions and cracked particles are restricted on a surface of an active layer of the bonded substrate and the surface of the active layer is flattened. A laminated body is formed by overlapping a first semiconductor substrate serving as an active layer onto a second semiconductor substrate serving as a support substrate via an oxide film or without an oxide film; the active layer is formed by forming a thin film from the first semiconductor substrate; and the surface of the active layer is flattened by vapor-phase etching. After forming a thin film from the first semiconductor substrate and before flattening the surface of the active layer by the vapor-phase etching, an organic substance adhering to the surface of the active layer is removed and a native oxide film generated on the surface of the active layer is removed after removing the organic substance.

Abstract: Systems and methods are provided for an on-chip decoupling device and method. One aspect of the present subject matter is a capacitor. One embodiment of the capacitor includes a substrate, a high K dielectric layer doped with nano crystals disposed on the substrate, and a top plate layer disposed on the high K dielectric layer. According to one embodiment, the high K dielectric layer includes Al2O3. According to other embodiments, the nano crystals include gold nano crystals and gold nano crystals. One capacitor embodiment includes a MIS (metal-insulator-silicon) capacitor fabricated on silicon substrate, and another capacitor embodiment includes a MIM (metal-insulator-metal) capacitor fabricated between the interconnect layers above silicon substrate. The structure of the capacitor is useful for reducing a resonance impedance and a resonance frequency for an integrated circuit chip. Other aspects are provided herein.

Abstract: A semiconductor structure for use as a template for forming high-performance metal oxide semiconductor field effect transistor (MOSFET) devices is provided. More specifically, the present invention provides a structure that includes a SiGe-on-insulator substrate including a tensile-strained SiGe alloy layer located atop an insulating layer; and a strained Si layer atop the tensile-strained SiGe alloy layer. The present invention also provides a method of forming the tensile-strained SGOI substrate as well as the heterostructure described above. The method of the present invention decouples the preference for high strain in the strained Si layer and the Ge content in the underlying layer by providing a tensile-strained SiGe alloy layer directly atop on an insulating layer.

Abstract: A cell suitable for use with an atomic clock and a method for making the same, the cell including: a silicon wafer having a recess formed therein; at least one amorphous silicate member having an ion mobility and temperature expansion coefficient approximately that of silicon sealing the recess; and, an alkali metal containing component and buffer gas contained in the recess. The method includes: providing a silicon wafer; forming a cavity through the silicon wafer; introducing an alkali metal containing component and buffer gas into the cavity; and, anodically bonding at least one amorphous silicate member having an ion mobility and temperature expansion coefficient approximately that of silicon to the wafer to close the cavity.

Abstract: A semiconductor fabrication process includes forming a sacrificial layer on a substrate of a donor wafer and implanting hydrogen ions into the substrate through the sacrificial layer to create a stress layer in the substrate. After forming the stress layer, multiple layer stacks are formed on the donor wafer substrate including a bottom gate conductor layer and a bottom gate dielectric layer. An upper surface of the donor wafer is bonded to an upper surface of a handle wafer. An oxide or low-k layer may be formed on the handle wafer. A portion of the substrate of the donor wafer is then cleaved. The bottom gate conductor layer is selected from the group including polysilicon, alpha silicon, alpha germanium, W, Ti, Ta, TiN, and TaSiN.

Abstract: A method of making a virtual substrate includes providing a device substrate of a first material containing a device layer of a second material different from the first material located over a first side of the device substrate, implanting ions into the device substrate such that a damaged region is formed in the device substrate below the device layer, bonding the device layer to a handle substrate, and separating at least a portion of the device substrate from the device layer bonded to the handle substrate along the damaged region to form a virtual substrate comprising the device layer bonded to the handle substrate.

Abstract: By performing at least one additional wet chemical etch process in the edge region and in particular on the bevel of a substrate during the formation of a metallization layer, the dielectric material, especially the low-k dielectric material, may be reliably removed from the bevel prior to the formation of any barrier and metal layers. Moreover, an additional wet chemical etch process may be performed after the deposition of the metal to remove any unwanted metal and barrier material from the edge region and the bevel. Accordingly, defect issues and contamination of substrates and process tools may be efficiently reduced.

Abstract: A semiconductor substrate whose surface roughness is reduced by optimizing an inclination (off angle) with respect to a {110} surface of the semiconductor substrate surface and a manufacturing method thereof are provided. The surface of the semiconductor substrate has the inclination (off angle) of 0 degree or more and 0.12 degrees or less, or 5 degrees or more and 11 degrees or less, preferably 6 degrees or more and 9 degrees or less with respect to the {110} surface. The manufacturing method of a semiconductor substrate has a process in which a semiconductor single crystal ingot is sliced at an inclination (off angle) of 5 degrees or more and 11 degrees or less, preferably 6 degrees or more and 9 degrees or less with respect to the {110} surface.

Abstract: A method for forming three-dimensional (3D) integrated circuits includes providing a first wafer comprising a silicon layer on a top surface of the first wafer, providing a second wafer comprising a silicon oxide layer on a top surface of the second wafer, bonding the first and the second wafers by placing a top surface of the silicon oxide layer against a top surface of the silicon layer and applying a pressure, and forming vias electrically interconnecting integrated circuits in the first and second wafers. The bonding is preferably preformed using a low pressure. A CMP and a plasma treatment are preferably performed to substantially flatten the surface of the silicon oxide layer before bonding.

Abstract: This invention makes it possible to simplify a process of manufacturing an SOI substrate whose insulator is not exposed to the side surface. The SOI substrate manufacturing method includes a first step of forming a structure (230) in which an insulating layer (204b) and semiconductor layer (203b) are in turn formed on a semiconductor member (211) by bonding a first substrate (210) to a second substrate (220), a second step of making the edge portion of an insulating layer (204b) of the structure (230) retreat toward the center so that the edge portion of a semiconductor layer (203c) overhangs the edge portion of an insulating layer (204c), and a third step of moving atoms which form the edge portion of the semiconductor layer (203c) such that the edge portion of a semiconductor layer (203d) covers the periphery of the insulating layer (204c) and connects to the semiconductor member (211).

Abstract: A method of fabricating a hybrid substrate by direct bonding of donor and receiver substrates where each substrate has a respective front face and surface, with the front face of the receiver substrate having a semiconductor material near the surface, and the donor substrate including a zone of weakness that defines a layer to be transferred. The method includes preparing the substrate surfaces by exposing the surface of the receiver substrate to a temperature from about 900° C. to about 1200° C. in an inert atmosphere for at least 30 sec; directly bonding together the front faces of the prepared substrates to form a composite substrate; heat treating the composite substrate to increase bonding strength between the front surfaces of the donor and receiver substrates; and transferring the layer from the donor substrate by detaching the remainder of the donor substrate at the zone of weakness.

Abstract: A method for fabricating a semiconductor substrate includes epitaxially growing an elemental semiconductor layer on a compound semiconductor substrate. An insulating layer is deposited on top of the elemental semiconductor layer, so as to form a first substrate. The first substrate is wafer bonded onto a monocrystalline Si substrate, such that the insulating layer bonds with the monocrystalline Si substrate. A semiconductor device includes a monocrystalline substrate, and a dielectric layer formed on the monocrystalline substrate. A semiconductor compound is formed on the dielectric layer and an elemental semiconductor material formed in proximity of the semiconductor compound and lattice-matched to the semiconductor compound.

Abstract: A bonded device structure including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads formed by contact bonding of the first non-metallic region to the second non-metallic region. At least one of the first and second substrates may be elastically deformed.

Abstract: There are included a semiconductor substrate provided with a desirable element region, an electrode pad formed to come in contact with a surface of the semiconductor substrate or a wiring layer provided on the surface of the semiconductor substrate, a bonding pad formed on a surface of the electrode pad through an intermediate layer, and a resin insulating film for covering a peripheral edge of the bonding pad such that an interface of the bonding pad and the intermediate layer is not exposed to a side wall.