Abstract: It is an object of the invention to provide a technique forming a crystalline semiconductor film whose orientation is uniform by control of crystal orientation and obtaining a crystalline semiconductor film in which concentration of an impurity is reduced. A configuration of the invention is that a first semiconductor region is formed on a substrate having transparent characteristics of a visible light region, a barrier film is formed over the first semiconductor region, a heat retaining film covering a top and side surfaces of the first semiconductor region is formed through the barrier film, the first semiconductor region is crystallized by scanning of a continuous wave laser beam from one edge of the first semiconductor region to the other through the substrate, the heat retaining film and the barrier film are removed, then a second semiconductor region is formed as an active layer of TFT by etching the first semiconductor region.

Abstract: By a laser crystallization method, a crystalline semiconductor film in which grain boundaries are all in one direction is provided as well as a manufacturing method thereof. In crystallizing a semiconductor film formed over a substrate with linear laser light, a phase-shift mask in which trenches are formed in a stripe form is used. The stripe-form trenches formed in the phase-shift mask are formed so as to make a nearly perpendicular angle with a major axis direction of the linear laser light. CW laser light is used as the laser light, and a scanning direction of the laser light is nearly parallel to a direction of the stripe-form trenches (grooves). By changing luminance of the laser light periodically in the major axis direction, a crystal nucleation position in a semiconductor that is completely melted can be controlled.

Abstract: To create a laminated film of a silicon oxide film and a silicon nitride film, with large current driving force and large dielectric constant. A manufacturing method of a semiconductor device includes: forming an amorphous silicon film on the silicon oxide film; and forming a single crystal silicon film by annealing the amorphous silicon film.

Abstract: A TFT is manufactured using at least five photomasks in a conventional liquid crystal display device, and therefore the manufacturing cost is high. By performing the formation of the pixel electrode 127, the source region 123 and the drain region 124 by using three photomasks in three photolithography steps, a liquid crystal display device prepared with a pixel TFT portion, having a reverse stagger type n-channel TFT, and a storage capacitor can be realized.

Abstract: A method of manufacturing a semiconductor device that forms laminate layers includes the steps of reducing contamination containing the single bond of carbon on at least one part of a surface on which the laminate films are formed by activated hydrogen before the laminate films are formed, and forming the laminate films on the surface on which the laminate films are formed.

Abstract: A transistor includes one or more channel taps containing a stack consisting at least in part of a semiconductor an interfacial III-VI layered compound and a conductor. The III-VI compound consists primarily of atoms from Groups IIIA-B and from Group VIA of the Periodic Table of the Elements in an approximate 1:1 ratio. These materials may be formed as layers of covalently bonded elements from Groups IIIA-B and covalently bonded Group VIA elements, adjacent and respective planes of which may be bonded by Van der Waals forces (e.g., to form a single bilayer consisting of a single plane of atoms from Groups IIIA-B and a single plane of Group VIA atoms). One particular III-VI material from which the interfacial layer is made, especially for p-channel transistors, is GaSe. Other III-VI compounds, whether pure compounds or alloys of pure compounds, may also be used.

Abstract: A structure, and method of fabrication, for high performance field effect devices is disclosed. The MOS structures include a crystalline Si body of one conductivity type, a strained SiGe layer epitaxially grown on the Si body serving as a buried channel for holes, a Si layer epitaxially grown on the SiGe layer serving as a surface channel for electrons, and a source and a drain containing an epitaxially deposited, strained SiGe of opposing conductivity type than the Si body. The SiGe source/drain forms a heterojunction and a metallurgical junction with the Si body that coincide with each other with a tolerance of less than about 10 nm, and preferably less than about 5 nm. The heterostructure source/drain is instrumental in reducing short channel effects. These structures are especially advantageous for PMOS due to increased hole mobility in the compressively strained SiGe channel. Representative embodiments include CMOS structures on bulk and on SOI.

Abstract: An SOI device, and a method for producing the SOI device, for use in an SRAM memory having enhanced stability. The SRAM is formed with a wider W and a fully-depleted FET. The wider FET is extended by an expitaxial silicon sidewall, and the performance of the FET is improved.

Abstract: A method for fabricating a thin film transistor is provided. First, a gate is formed on a substrate. A gate-insulating layer is formed to cover the gate. A patterned semiconductor layer is formed on the gate-insulating layer. A first and a second conductive layer are formed on the patterned semiconductor layer in sequence. The second conductive layer is patterned such that each side of thereof above the gate has a taper profile and the first conductive layer is exposed. A first plasma process is performed to transform the surface and the taper profile of the second conductive layer into a first protection layer. The first conductive layer not covered by the first protection layer and the second conductive layer is removed to form a source/drain. The source/drain is with fine dimensions and the diffusion of metallic ions from the second conductive layer to the patterned semiconductor layer can be avoided.

Abstract: An interconnect structure which includes a plating seed layer that has enhanced conductive material, preferably, Cu, diffusion properties is provided that eliminates the need for utilizing separate diffusion and seed layers. Specifically, the present invention provides an oxygen/nitrogen transition region within a plating seed layer for interconnect metal diffusion enhancement. The plating seed layer may include Ru, Ir or alloys thereof, and the interconnect conductive material may include Cu, Al, AlCu, W, Ag, Au and the like. Preferably, the interconnect conductive material is Cu or AlCu. In more specific terms, the present invention provides a single seeding layer which includes an oxygen/nitrogen transition region sandwiched between top and bottom seed regions. The presence of the oxygen/nitrogen transition region within the plating seed layer dramatically enhances the diffusion barrier resistance of the plating seed.

Abstract: A silicon-on-insulator (SOI) substrate including laminated layers of a substrate, an oxide layer, and a silicon layer in order. The oxide layer has an electrifying hole fluidly connected with the substrate and the electrifying hole is filled with a part of the silicon layer. A method for fabricating the floating structure is also disclosed which includes the steps of forming an oxide layer having a predetermined thickness on a substrate, forming one or more electrifying holes in an area of the oxide layer corresponding to an inner part of the floating structure, forming a silicon layer on the oxide layer including an electrification structure electrically connecting the silicon layer to the substrate, forming a pattern for the floating structure on the silicon layer, removing the oxide layer corresponding to an inner area of the pattern, forming a thermal oxide layer on a surface of the silicon layer, and removing the thermal oxide layer to form the floating structure.

Abstract: A liquid crystal display panel manufacturing method includes forming at least one thin film on a flexible plastic substrate by sputtering at a temperature of about 80° C. to about 150° C. Sputtering can be in a chamber evacuated to about 1×10?6 Torr to about 9×10?6 Torr. Sputtering targets and films sputtered on substrates include materials that are conductive or insulating, organic or inorganic, metal or metal alloy, reflective metal or transparent conductive, or combinations thereof. Thin film and pattern formation employ photolithography with laminated or liquid films. Films may be sputtered on opposing sides of a substrate and may be multilayered.