Abstract: A method and system for providing an alloy layer in a semiconductor device are described. The method and system ramping a first gas including a first constituent of the alloy layer from a first level to a second level different from the first level while the alloy layer is grown. The method and system also include ramping a second gas including a second constituent of the alloy layer from a third level to a fourth level different from the third level while the alloy layer is grown. In one aspect, the alloy layer includes silicon and germanium. In this aspect, the first gas includes silicon, while the second gas includes germanium.

Abstract: In a method of making a semiconductor device, a recess is formed in an upper surface of the semiconductor body of a first material. An embedded semiconductor region is formed in the recess. The embedded semiconductor region is formed from a second semiconductor material that is different than the first semiconductor material. An upper surface of the embedded semiconductor region is amorphized to create an amorphous region. A silicide is then formed over the amorphous region.

Abstract: An EPROM cell includes a control gate and a control transistor. A portion of the control transistor is formed as a portion of the control gate.

Abstract: A method to fabricate patterned strain-relaxed SiGe epitaxial with threading dislocation density control is provided. An ion-implanting area is first defined on a silicon substrate, and then proceeds ion-implanting. Finally, a buffer layer and a SiGe epitaxial layer are deposited. According to the disclosure, an active area and a non-active area are defined through ion-implanting. Therefore, the threading dislocation occurring in the active area concentrates in the non-active area, and the density of the threading dislocation is lowered. Furthermore, the performance of the semiconductor is also enhanced.

Abstract: The present invention is a dual-level flash memory cell design that stores 3 or more bits of information per transistor. The dual-level memory cell stores two lower bits in a first level and stores an upper bit in a second level. The lower bits are programmed, erased and read by alternate modes of operation wherein active regions operate as source and drain, and then drain and source. The upper bit is programmed and erased independent of the lower bits. However, reading of the upper bit depends upon read values of the lower bits. Additional levels are employed to store more than 3 bits of information.

Abstract: A method of manufacturing semiconductor substrates. After supporting layers are provided on side walls of grooves formed in a semiconductor substrate, grooves that expose a second semiconductor layer are formed. Etching gas or etching liquid is brought in contact with the first semiconductor layer through the grooves, to form a void portion between the semiconductor substrate 1 and the second semiconductor layer. By thermally oxidizing the semiconductor substrate, the second semiconductor layer and the supporting layers, an oxide film is formed in the void portion between the semiconductor substrate and the second semiconductor layer, an oxide film is formed on side walls of the semiconductor substrate in the grooves, and the supporting layers are changed into oxide films.

Abstract: A method for making a SOI wafer with a strained silicon layer for increased electron and hole mobility is achieved. The method forms a porous silicon layer on a seed wafer. A H2 anneal is used to form a smooth surface on the porous silicon. A strain free (relaxed) epitaxial SixGe1-x layer is deposited and a bonding layer is formed. The seed wafer is then bonded to a handle wafer having an insulator on the surface. A spray etch is used to etch the porous Si layer resulting in a SOI handle wafer having portions of the porous Si layer on the relaxed SixGe1-x. The handle wafer is then annealed in H2 to convert the porous Si to a smooth strained Si layer on the relaxed SiGe layer of the SOI wafer.

Abstract: In a nonvolatile memory cell (110), the select gate transistor is formed as a buried channel transistor to increase the transistor current.

Abstract: The present invention discloses an integration flow of germanium into a conventional CMOS process, with improvements in performing selective area growth, and implementing electrical contacts to the germanium, in a way that has minimal impact on the preexisting transistor devices. The present invention also provides methods to integrate the germanium without impacting the optical or electrical performance of these devices, except where intended, such as in a germanium photodetector, or germanium waveguide photodetector.

Abstract: Growth of multilayer films is carried out in a manner which allows close control of the strain in the grown layers and complete release of the grown films to allow mounting of the released multilayer structures on selected substrates. A layer of material, such as silicon-germanium, is grown onto a template layer, such as silicon, of a substrate having a sacrificial layer on which the template layer is formed. The grown layer has a lattice mismatch with the template layer so that it is strained as deposited. A top layer of crystalline material, such as silicon, is grown on the alloy layer to form a multilayer structure with the grown layer and the template layer. The sacrificial layer is preferentially etched away to release the multilayer structure from the sacrificial layer, relaxing the grown layer and straining the crystalline layers interfaced with it.