Abstract: A transistor includes a substrate. A first electrically conductive material layer, having a thickness, is positioned on the substrate. A second electrically conductive material layer is in contact with and positioned on the first electrically conductive material layer. The second electrically conductive material layer overhangs the first electrically conductive material layer. An electrically insulating material layer, having a thickness, is conformally positioned over the second electrically conductive material layer, the first electrically conductive material layer, and at least a portion of the substrate. The thickness of the first electrically conductive material layer is greater than the thickness of the electrically insulating material layer.

Abstract: III-N material grown on a silicon substrate includes a single crystal buffer positioned on a silicon substrate. The buffer is substantially crystal lattice matched to the surface of the silicon substrate and includes aluminum oxynitride adjacent the substrate and aluminum nitride adjacent the upper surface. A first layer of III-N material is positioned on the upper surface of the buffer. An inter-layer of aluminum nitride (AlN) is positioned on the first III-N layer and an additional layer of III-N material is positioned on the inter-layer. The inter-layer of aluminum nitride and the additional layer of III-N material are repeated n-times to reduce or engineer strain in a final III-N layer.

Abstract: A passivated germanium surface that is a germanium carbide material formed on and in contact with the germanium material. A semiconductor device structure having the passivated germanium having germanium carbide material on the substrate surface is also disclosed.

Abstract: A light emitting device includes: a first layer made of a semiconductor of a first conductivity type; a second layer made of a semiconductor of a second conductivity type; an active layer including a multiple quantum well provided between the first layer and the second layer, impurity concentration of the first conductivity type in each barrier layer of the multiple quantum well having a generally flat distribution or increasing toward the second layer, average of the impurity concentration in the barrier layer on the second layer side as viewed from each well layer of the multiple quantum well being equal to or greater than average of the impurity concentration in the barrier layer on the first layer side, and average of the impurity concentration in the barrier layer nearest to the second layer being higher than average of the impurity concentration in the barrier layer nearest to the first layer.

Abstract: A passivated germanium surface that is a germanium carbide material formed on and in contact with the termanium material. An intermediate semiconductor device structure and a semiconductor device structure, each of which comprises the passivated germanium having germanium carbide material thereon, are also disclosed.

Abstract: To provide a semiconductor device in which resistance of a source region and a drain region of a thin film transistor is reduced and a short channel effect is suppressed, and a manufacturing method thereof. The semiconductor device includes a gate electrode which is formed over a first semiconductor layer with a gate insulating film interposed therebetween; sidewalls which are formed on side surfaces of the gate electrode; and second semiconductor layers which are in contact with and stacked over end portions of the sidewalls and the first semiconductor layer, wherein the second semiconductor layers cover at least a part of the end portions of the sidewalls.

Abstract: Flip chip ball grid array semiconductor devices and methods for fabricating the same. In one example, a near chip scale method of semiconductor die packaging may comprise adhering the die to a substrate in a flip chip configuration, coating the die with a first polymer layer, selectively removing the first polymer layer to provide at least one opening to expose a portion of the die, and depositing a first metal layer over the first polymer layer, the first metal layer at least partially filling the at least one opening to provide an electrical contact to the die, and including a portion that substantially surrounds the die in a plane of an upper surface of the first metal layer to provide an electromagnetic shield around the die.

Abstract: A compound semiconductor substrate which inhibits the generation of a crack or a warp and is preferable for a normally-off type high breakdown voltage device, arranged that a multilayer buffer layer 2 in which AlxGa1-xN single crystal layers (0.6?X?1.0) 21 containing carbon from 1×1018 atoms/cm3 to 1×1021 atoms/cm3 and AlyGa1-yN single crystal layers (0.1?y?0.5) 22 containing carbon from 1×1017 atoms/cm3 to 1×1021 atoms/cm3 are alternately and repeatedly stacked in order, and a nitride active layer 3 provided with an electron transport layer 31 having a carbon concentration of 5×1017 atoms/cm3 or less and an electron supply layer 32 are deposited on a Si single crystal substrate 1 in order. The carbon concentrations of the AlxGa1-xN single crystal layers 21 and that of the AlGa1-yN single crystal layers 22 respectively decrease from the substrate 1 side towards the above-mentioned active layer 3 side. In this way, the compound semiconductor substrate is produced.

Abstract: In a structure for crystalline material growth, there is provided a lower growth confinement layer and an upper growth confinement layer that is disposed above and vertically separated from the lower growth confinement layer. A lateral growth channel is provided between the upper and lower growth confinement layers, and is characterized by a height that is defined by the vertical separation between the upper and lower growth confinement layers. A growth seed is disposed at a site in the lateral growth channel for initiating crystalline material growth in the channel. A growth channel outlet is included for providing formed crystalline material from the growth channel. With this growth confinement structure, crystalline material can be grown from the growth seed to the lateral growth channel outlet.

Abstract: A light emitting device includes: a first layer made of a semiconductor of a first conductivity type; a second layer made of a semiconductor of a second conductivity type; an active layer including a multiple quantum well provided between the first layer and the second layer, impurity concentration of the first conductivity type in each barrier layer of the multiple quantum well having a generally flat distribution or increasing toward the second layer, average of the impurity concentration in the barrier layer on the second layer side as viewed from each well layer of the multiple quantum well being equal to or greater than average of the impurity concentration in the barrier layer on the first layer side, and average of the impurity concentration in the barrier layer nearest to the second layer being higher than average of the impurity concentration in the barrier layer nearest to the first layer.

Abstract: A method is described which includes providing a semiconductor substrate and forming a trench in the semiconductor substrate. An epitaxy region is grown in the trench. An amorphous layer is deposited overlying the epitaxy region. The semiconductor substrate is then annealed. The anneal may convert a portion of the amorphous layer to crystalline material, as found in the epitaxy region. A chemical mechanical polish (CMP) is then performed, which may remove a portion of the amorphous layer which has not been converted. In an embodiment, the amorphous layer and epitaxy region are germanium and the semiconductor substrate is silicon. The formed crystalline region may be used to form a channel of a p-type device.

Abstract: Flip chip ball grid array semiconductor devices and methods for fabricating the same. In one example, a near chip scale method of semiconductor die packaging may comprise adhering the die to a substrate in a flip chip configuration, coating the die with a first polymer layer, selectively removing the first polymer layer to provide at least one opening to expose a portion of the die, and depositing a first metal layer over the first polymer layer, the first metal layer at least partially filling the at least one opening to provide an electrical contact to the die, and including a portion that substantially surrounds the die in a plane of an upper surface of the first metal layer to provide an electromagnetic shield around the die.

Abstract: A method of passivating germanium that comprises providing a germanium material and carburizing the germanium material to form a germanium carbide material. The germanium carbide material may be formed by microwave plasma-enhanced chemical vapor deposition by exposing the germanium material to a microwave-generated plasma that is formed from a carbon-containing source gas and hydrogen. The source gas may be a carbon-containing gas selected from the group consisting of ethylene, acetylene, ethanol, a hydrocarbon gas having from one to ten carbon atoms per molecule, and mixtures thereof. The resulting germanium carbide material may be amorphous and hydrogenated. The germanium material may be carburized without forming a distinct boundary at an interface between the germanium material and the germanium carbide material. An intermediate semiconductor device structure and a semiconductor device structure, each of which comprises the germanium carbide material, are also disclosed.

Abstract: The present disclosure describes methods for preparing semiconductor structures, comprising forming a Ge1-ySny buffer layer on a semiconductor substrate and forming a tensile strained Ge layer on the Ge1-ySny buffer layer using an admixture of (GeH3)2CH2 and Ge2H6 in a ratio of between 1:10 and 1:30. The disclosure further provides semiconductor structures having highly strained Ge epilayers (e.g., between about 0.15% and 0.45%) as well as compositions comprising an admixture of (GeH3)2CH2 and Ge2H6 in a ratio of between about 1:10 and 1:30. The methods herein provide, and the semiconductor structure provide, Ge epilayers having high strain levels which can be useful in semiconductor devices for example, in optical fiber communications devices.

Abstract: The invention relates to a method for forming a semiconductor heterostructure by providing a substrate with a first in-plane lattice parameter a1, providing a buffer layer with a second in-plane lattice parameter a2 and providing a top layer over the buffer layer. In order to improve the surface roughness of the semiconductor heterostructure, an additional layer is provided in between the buffer layer and the top layer, wherein the additional layer has a third in-plane lattice parameter a3 which is in between the first and second lattice parameters.

Abstract: A semiconductor device, includes: a first conductivity type semiconductor base having a main face; a hetero semiconductor region contacting the main face of the semiconductor base and forming a hetero junction in combination with the semiconductor base, the semiconductor base and the hetero semiconductor region in combination defining a junction end part; a gate insulating film defining a junction face in contact with the semiconductor base and having a thickness; and a gate electrode disposed adjacent to the junction end part via the gate insulating film and defining a shortest point in a position away from the junction end part by a shortest interval, a line extending from the shortest point to a contact point vertically relative to the junction face, forming such a distance between the contact point and the junction end part as to be smaller than the thickness of the gate insulating film contacting the semiconductor base.

Abstract: A method for manufacturing a semiconductor substrate comprises: forming a silicon on insulator (SOI) area and an element isolation film on a semiconductor base; forming a first semiconductor layer on the semiconductor base in the SOI structure area; forming a second semiconductor layer having an etching selection ratio smaller than an etching selection ratio of the first semiconductor layer on the first semiconductor layer; removing a part of the second semiconductor layer and a part of the first semiconductor layer in the SOI structure area so as to form a recess exposing the semiconductor base and supporting a support; forming a support forming layer on the semiconductor base so as to bury the recess and cover the second semiconductor layer; etching an area excluding the recess, the element area, and an area covering the element isolation film so as to form the support and an opening face exposing a part of end parts of the first semiconductor layer and the second semiconductor layer, the opening face being

Abstract: Provided is a method of forming a heterojunction of contiguous layers of organic semiconducting polymers. The method comprises firstly forming a layer of a first organic semiconducting polymer on a substrate. A solution of a film-forming material is then deposited on the layer of the first organic semiconducting polymer. The first organic semiconducting polymer is insoluble in this solution and so is not disturbed by its deposition. The deposited solution is then dried to form a temporary film having a thickness of less then 20 nm formed from the film-forming material. Next a solution of a second organic semiconducting polymer dissolved in an organic solvent is deposited on the temporary film and this solution dried. The solubility of the material forming the temporary film in the organic solvent and the thickness of the temporary film are such that the organic solvent permeates through the thickness of the temporary film during drying of the solution of the second organic semiconducting polymer.

Abstract: A method of passivating germanium that comprises providing a germanium material and carburizing the germanium material to form a germanium carbide layer. The germanium carbide layer may be formed by microwave plasma-enhanced chemical vapor deposition by exposing the germanium material to a microwave-generated plasma that is formed from a carbon-containing source gas and hydrogen. The source gas may be a carbon-containing gas selected from the group consisting of ethylene, acetylene, ethanol, a hydrocarbon gas having from one to ten carbon atoms per molecule, and mixtures thereof. The resulting germanium carbide layer may be amorphous and hydrogenated. The germanium material may be carburized without forming a distinct boundary at an interface between the germanium material and the germanium carbide layer. An intermediate semiconductor device structure and a semiconductor device structure, each of which comprises the germanium carbide layer, are also disclosed.

Abstract: Methods for electrodepositing germanium on various semiconductor substrates such as Si, Ge, SiGe, and GaAs are provided. The electrodeposited germanium can be formed as a blanket or patterned film, and may be crystallized by solid phase epitaxy to the orientation of the underlying semiconductor substrate by subsequent annealing. These plated germanium layers may be used as the channel regions of high-mobility channel field effect transistors (FETs) in complementary metal oxide semiconductor (CMOS) circuits.

Abstract: A method of fabricating a thin-film compound solar cell having an n-type buffer layer formed therein for providing a heterojunction with a p-type compound semiconductor light absorbing layer formed on a back electrode by spreading a powder of a sulfur compound containing n-type doping element over the light absorbing layer surface or applying a coat of a solution of a sulfur compound containing n-type doping element onto the light absorbing layer surface and then fusing the powder or the coat thereon by heat. This process can produce a high-quality n-type buffer layer tightly adhered to a p-type compound semiconductor light absorbing layer to achieve stable characteristic of heterojunction therewith.