Abstract: A GaN single crystal 20 is grown on a crystal growth surface of a seed crystal (GaN layer 13) through the flux method in a nitrogen (N2) atmosphere at 3.7 MPa and 870° C. employing a flux mixture including Ga, Na, and Li at about 870° C. Since the back surface of the template 10 is R-plane of the sapphire substrate 11, the template 10 is readily corroded or dissolved in the flux mixture from the back surface thereof. Therefore, the template 10 is gradually dissolved or corroded from the back surface thereof, resulting in separation from the semiconductor or dissolution in the flux. When the GaN single crystal 20 is grown to a sufficient thickness, for example, about 500 ?m or more, the temperature of the crucible is maintained at 850° C. to 880° C., whereby the entirety of the sapphire substrate 11 is dissolved in the flux mixture.

Abstract: In a method for manufacturing a high-quality GaN-based semiconductor layer on a substrate of different material, an AlN nucleation layer is grown on a substrate, a GaN buffer layer is grown on the AlN nucleation layer, and the substrate annealed. The AlN nucleation layer is formed to have a thickness greater than a critical radius of a nucleus of AlN crystal and less than a critical resilient thickness of AlN, and the GaN buffer layer is formed to have a thickness greater than a critical radius of a nucleus of GaN crystal and less than a critical resilient thickness of GaN. Annealing time is greater than L2/DGa where L indicates a diffusion distance of Ga, and DGa indicates a diffusion coefficient of Ga in the AlN nucleation layer.

Abstract: A method for improved growth of a semipolar (Al,In,Ga,B)N semiconductor thin film using an intentionally miscut substrate. Specifically, the method comprises intentionally miscutting a substrate, loading a substrate into a reactor, heating the substrate under a flow of nitrogen and/or hydrogen and/or ammonia, depositing an InxGa1?xN nucleation layer on the heated substrate, depositing a semipolar nitride semiconductor thin film on the InxGa1?xN nucleation layer, and cooling the substrate under a nitrogen overpressure.

Abstract: A method for producing a nitride semiconductor laser light source is provided. The nitride semiconductor laser light source has a nitride semiconductor laser chip, a stem for mounting the laser chip thereon, and a cap for covering the laser chip. The laser chip is encapsulated in a sealed container composed of the stem and the cap. The method for producing this nitride semiconductor, laser light source has a cleaning step of cleaning the surface of the laser chip, the stem, or the cap. In the cleaning step, the laser chip, the stem, or the cap is exposed with ozone or an excited oxygen atom, or baked by heat. The method also has, after the cleaning step, a capping step of encapsulating the laser chip in the sealed container composed of the stem and the cap. During the capping step, the cleaned surface of the laser chip, the stem, or the cap is kept clean.

Abstract: A method for enhancing growth of device-quality planar semipolar nitride semiconductor thin films via metalorganic chemical vapor deposition (MOCVD) by using an (Al,In,Ga)N nucleation layer containing at least some indium. Specifically, the method comprises loading a substrate into a reactor, heating the substrate under a flow of nitrogen and/or hydrogen and/or ammonia, depositing an InxGa1-xN nucleation layer on the heated substrate, depositing a semipolar nitride semiconductor thin film on the InxGa1-xN nucleation layer, and cooling the substrate under a nitrogen overpressure.

Abstract: Disclosed herein is a high-quality group III-nitride semiconductor thin film and group III-nitride semiconductor light emitting device using the same. To obtain the group III-nitride semiconductor thin film, an AlInN buffer layer is formed on a (1-102)-plane (so called r-plane) sapphire substrate by use of a MOCVD apparatus under atmospheric pressure while controlling a temperature of the substrate within a range from 850 to 950 degrees Celsius, and then, GaN-based compound, such as GaN, AlGaN or the like, is epitaxially grown on the buffer layer at a high temperature. The group III-nitride semiconductor light emitting device is fabricated by using the group III-nitride semiconductor thin film as a base layer.

Abstract: In an embodiment, a 3-dimensional flash memory device includes: a gate extending in a vertical direction on a semiconductor substrate; a charge storing layer surrounding the gate; a silicon layer surrounding the charge storing layer; a channel region vertically formed in the silicon layer; and source/drain regions vertically formed on both sides of the channel region in the silicon layer. Integration can be improved by storing data in a 3-dimensional manner; a 2-bit operation can be performed by providing transistors on both sides of the gate.

Abstract: A GaN-based thin film (thick film) is grown using a metal buffer layer grown on a substrate. (a) A metal buffer layer (210) made of, for example, Cr or Cu is vapor-deposited on a sapphire substrate (120). (b) A substrate obtained by vapor-depositing the metal buffer layer (210) on the sapphire substrate (120) is nitrided in an ammonia gas ambient, thereby forming a metal nitride layer (212). (c) A GaN buffer layer (222) is grown on the nitrided metal buffer layers (210, 212). (d) Finally, a GaN single-crystal layer (220) is grown. This GaN single-crystal layer (220) can be grown to have various thicknesses depending on the objects. A freestanding substrate can be fabricated by selective chemical etching of the substrate fabricated by the above steps. It is also possible to use the substrate fabricated by the above steps as a GaN template substrate for fabricating a GaN-based light emitting diode or laser diode.

Abstract: A thin film transistor array substrate including an insulating substrate, a first metallic pattern formed on the insulating substrate, and an insulating film provided on the first metallic pattern. A semiconductor pattern is provided on the insulating film, and a second metallic pattern is provided on the semiconductor pattern. The second metallic pattern is surrounded by the semiconductor pattern.

Abstract: A method for manufacturing a thin film transistor (“TFT”) array includes providing a substrate, a patterned first metal layer on the substrate including a plurality of first conductive lines and a plurality of second conductive lines disposed orthogonal to the first conductive lines, an insulating layer over the patterned first metal layer, a patterned silicon layer, a patterned passivation layer over the patterned silicon layer, and a patterned doped silicon layer and a patterned second metal layer over the patterned passivation layer, filling exposed portions of the patterned silicon layer and exposed portions of the first conductive lines and the second conductive lines, where the patterned second metal layer includes a plurality of third conductive lines and a plurality of fourth conductive lines, each of which corresponding respectively to one of the plurality of first conductive lines and the plurality of second conductive lines.

Abstract: A III group nitride semiconductor substrate according to the present invention is fabricated by forming a metal film or metal nitride film 2? with mesh structure in which micro voids are provided on a starting substrate 1, and growing a III group nitride semiconductor crystal layer 3 via the metal film or metal nitride film 2?.

Abstract: The method for manufacturing the indium gallium aluminium nitride (InGaAlN) thin film on silicon substrate, which comprises the following steps: introducing magnesium metal for processing online region mask film, that is, or forming one magnesium mask film layer or metal transition layer; then forming one metal transition layer or magnesium mask layer, finally forming one layer of indium gallium aluminium nitride semiconductor layer; or firstly forming one layer of metal transition layer on silicon substrate and then forming the first indium gallium aluminium nitride semiconductor layer, magnesium mask layer and second indium gallium aluminium nitride semiconductor layer in this order. This invention can reduce the dislocation density of indium gallium aluminium nitride materials and improve crystal quality.

Abstract: An exemplary method for fabricating a thin film transistor (TFT) array substrate includes: providing an insulating substrate; forming a plurality of gate electrodes and a plurality of reflective patterns on the insulating substrate using a first photo-mask process; forming a gate insulating layer, an amorphous silicon layer, a doped amorphous silicon layer, and a source/drain metal layer on the insulating substrate having the gate electrodes and the reflective patterns; forming a plurality of source electrodes and a plurality of drain electrodes on the doped amorphous silicon layer; depositing a passivation layer on the source electrodes, the drain electrodes and the gate insulating layer; and forming a pixel electrode on the passivation layer.

Abstract: A thin film transistor array panel includes an insulating substrate, a gate wire formed on the insulating substrate. A gate insulating layer covers the gate wire. A semiconductor pattern is formed on the gate insulating layer. A data wire having source electrodes, drain electrodes and data lines is formed on the gate insulating layer and the semiconductor pattern. A protective layer is formed on the data wire. Pixel electrodes connected to the drain electrode via contact holes are formed on the protective layer. The gate wire and the data wire are made of Ag alloy containing Ag and an additive including at least one selected from Zn, In, Sn and Cr.

Abstract: A semiconductor structure of a liquid crystal display and the manufacturing method thereof are described. The manufacturing method includes the following steps. A patterned polysilicon layer and a first dielectric layer are formed on a substrate. A first patterned metal layer is formed to construct a gate electrode and a capacitor electrode. An ion implantation is conducted on the polysilicon layer to form drain and source electrodes. A second dielectric layer and a second patterned metal layer are formed thereon. Sequentially, a third dielectric layer is formed thereon. A plurality of via openings are formed by a patterned photoresist layer, and a third metal layer is formed thereon and filled into the via openings. The patterned photoresist layer and the redundant third metal layer are stripped from the substrate to form via plugs in the via openings. A patterned transparent conductive layer is formed thereon to connect the via plugs.

Abstract: A thermal expansion interface between silicon (Si) and gallium nitride (GaN) films using multiple buffer layers of aluminum compounds has been provided, along with an associated fabrication method. The method provides a (111) Si substrate and deposits a first layer of AlN overlying the substrate by heating the substrate to a relatively high temperature of 1000 to 1200° C. A second layer of AlN is deposited overlying the first layer of AlN at a lower temperature of 500 to 800° C. A third layer of AlN is deposited overlying the second layer of AlN by heating the substrate to the higher temperature range. Then, a grading Al1-XGaXN layer is formed overlying the third layer of AlN, where 0<X<1, followed by a fixed composition Al1-XGaXN layer overlying the first grading Al1-XGaXN layer. An epitaxial GaN layer can then be grown overlying the fixed composition Al1-XGaXN layer.

Abstract: A method for manufacturing a nitride semiconductor substrate including the steps of: forming a nitride semiconductor layer on a sapphire substrate, and manufacturing a freestanding nitride semiconductor substrate by using the nitride semiconductor layer separated from the sapphire substrate, wherein variability of inclinations of the C-axes, being a difference between a maximum value and a minimum value of inclination of the C-axes in a radially-outward direction at each point on a front surface of the sapphire substrate is 0.3° or more and 1° or less.

Abstract: A selectively strained MOS device such as selectively strained PMOS device making up an NMOS and PMOS device pair without affecting a strain in the NMOS device the method including providing a semiconductor substrate comprising a lower semiconductor region, an insulator region overlying the lower semiconductor region and an upper semiconductor region overlying the insulator region; patterning the upper semiconductor region and insulator region to form a MOS active region; forming an MOS device comprising a gate structure and a channel region on the MOS active region; and, carrying out an oxidation process to oxidize a portion of the upper semiconductor region to produce a strain in the channel region.

Abstract: A method of suppressing parasitic particle formation in a metal organic chemical vapor deposition process is described. The method may include providing a substrate to a reaction chamber, and introducing an organometallic precursor, a particle suppression compound and at least a second precursor to the reaction chamber. The second precursor reacts with the organometallic precursor to form a nucleation layer on the substrate. Also, a method of suppressing parasitic particle formation during formation of a III-V nitride layer is described. The method includes introducing a group III metal containing precursor to a reaction chamber. The group III metal precursor may include a halogen. A hydrogen halide gas and a nitrogen containing gas are also introduced to the reaction chamber. The nitrogen containing gas reacts with the group III metal precursor to form the III-V nitride layer on the substrate.

Abstract: Methods are provided of fabricating compound nitride semiconductor structures. A group-III precursor and a nitrogen precursor are flowed into a processing chamber to deposit a first layer over a surface of a first substrate with a thermal chemical-vapor-deposition process. A second layer is deposited over a surface of a second substrate with the thermal chemical-vapor-deposition process using the first group-III precursor and the first nitrogen precursor. The first and second substrates are different outer substrates of a plurality of stacked substrates disposed within the processing chamber as a stack so that the first and second layers are deposited on opposite sides of the stack. Deposition of the first layer and deposition of the second layer are performed simultaneously.

Abstract: A GaN based III-V nitride semiconductor light-emitting device and a method for fabricating the same are provided. In the GaN based III-V nitride semiconductor light-emitting device including first and second electrodes arranged facing opposite directions or the same direction with a high-resistant substrate therebetween and material layers for light emission or lasing, the second electrode directly contacts a region of the outmost material layer exposed through an etched region of the high-resistant substrate. A thermal conductive layer may be formed on the bottom of the high-resistant substrate to cover the exposed region of the outmost material layer.

Abstract: An aluminum nitride single-crystal multi-layered substrate comprising an aluminum nitride single-crystal layer formed by direct reduction nitridation on a single-crystal ?-alumina substrate such as a sapphire substrate and an edge-type dislocation layer having a thickness of 10 nm or less in the vicinity of the interface between the both crystals. Threading dislocation is rarely existent in the aluminum nitride single-crystal layer existent on the surface. It is useful as a semiconductor device substrate.

Abstract: The present invention provides methods for manufacturing a nitride layer and a vertical nitride semiconductor light emitting device. In manufacturing the nitride layer according to the invention, a sapphire substrate is prepared. A buffer layer made of a material having a melting point and a thermal conductivity higher than those of nitride is formed on the sapphire substrate. Also, the nitride layer is formed on the buffer layer. Then a laser beam is irradiated to an underside of the sapphire substrate to remove the nitride layer. According to the invention, the nitride layer is made of a material having a composition expressed by AlxInyGa(1-x-y)N, where 0?x?1, 0?y?1, and 0?x+y?1. In addition, the buffer layer is made of SiC.

Abstract: A surface emitting semiconductor laser chip contains a semiconductor body, which has, at least partly, a crystal structure with principal crystal directions, a radiation exit face, and side faces laterally delimiting the semiconductor body. At least one of the side faces is disposed obliquely with respect to the principal crystal directions.

Abstract: The present invention provides a method of integrated semiconductor devices such that different types of devices are formed upon a specific crystallographic orientation of a hybrid substrate. In accordance with the present invention, junction capacitance of one of the devices is improved in the present invention by forming the source/drain diffusion regions of the device in an epitiaxial semiconductor material such that they are situated on a buried insulating layer that extends partially underneath the body of the second semiconductor device. The second semiconductor device, together with the first semiconductor device, is both located atop the buried insulating layer. Unlike the first semiconductor device in which the body thereof is floating, the second semiconductor device is not floating. Rather, it is in contact with an underlying first semiconducting layer.

Abstract: A method for surface modification of a semiconductor layer and a method of manufacturing a semiconductor device are provided. The method for surface modification of the silicon layer includes following steps. First, a semiconductor layer having several particles on its surface is provided. Next, these particles are removed through a clean process. In the clean process, the semiconductor layer is exposed to an organic matter remover, a first peroxide mixture solution and a second peroxide mixture solution sequentially.

Abstract: A method of connecting stranded wire to a lead-frame body 10 includes the provision of a stranded wire 12. It is ensured that insulation is stripped from an end 14 of the stranded wire. An electrically conductive lead-frame connection structure 16 is associated with the lead-frame body. The end 14 of the stranded wire is inserted into the lead-frame connection structure 16 so that the lead-frame connection structure substantially surrounds the wire end. Solder flux is injected so as to be substantially about a portion of the end of the stranded wire. The lead-frame connection structure is placed in contact with a bottom resistance welding electrode 18 or a top resistance welding electrode 20.

Abstract: A method of fabricating a thick gallium nitride (GaN) layer includes forming a porous GaN layer having a thickness of 10-1000 nm by etching a GaN substrate in a reaction chamber in an HCI and NH3 gas atmosphere and forming an in-situ GaN growth layer in the reaction chamber. The method of forming the porous GaN layer and the thick GaN layer in-situ proceeds in a single chamber. The method is very simplified compared to the prior art. In this way, the entire process is performed in one chamber, and in particular, GaN etching and growth are performed using an HVPE process gas such that costs are greatly reduced.

Abstract: In a display device such as a liquid crystal display device, a large-sized display screen is realized under low power consumption. A surface of a source wiring line of a pixel portion employed in an active matrix type liquid crystal display device is processed by way of a plating process operation so as to lower a resistance value of this source wiring line. The source wiring line of the pixel portion is manufactured at a step different from a step for manufacturing a source wiring line of a drive circuit portion. Further, electrodes of a terminal portion are processed by a plating process operation so as to reduce a resistance value thereof.

Abstract: Methods and systems for growing uniform oxide layers include an example method including growing a first layer of oxide on first and second facets of the substrate, with the first facet having a faster oxide growth rate. The oxide is removed from the first facet and a second oxide layer is grown on the first and second facets. Removing the oxide from the first facet includes shielding the second facet and exposing the substrate to a deoxidizing condition. The second facet is then exposed to receive the second oxide layer. Areas having differing oxide thicknesses are also grown by repeatedly growing oxide layers, selectively shielding areas, and removing oxide from exposed areas.

Abstract: A method of fabricating a p-i-n type light emitting diode using p-type ZnO, and particularly, a technique for fabricating a p-type ZnO thin film doped with copper, a light emitting diode manufactured using the same, and its application to electrical and magnetic devices. The method of fabricating a p-i-n type light emitting diode using p-type ZnO includes depositing a low-temperature ZnO buffer layer on a sapphire single-crystal substrate, depositing an n-type gallium doped ZnO layer on the deposited low-temperature ZnO buffer layer, depositing an intrinsic ZnO thin film on the deposited n-type gallium doped ZnO layer, forming a p-type ZnO thin film layer on the deposited intrinsic ZnO thin film, forming a MESA structure on the p-type ZnO thin film layer through wet etching to obtain a diode structure, and subjecting the diode structure to post-heat treatment.

Abstract: A semiconductor device includes a silicon crystal layer on an insulating layer, the silicon crystal layer containing a crystal lattice mismatch plane, a memory cell array portion on the silicon crystal layer, the memory cell array portion including memory strings, each of the memory strings including nonvolatile memory cell transistors connected in series in a first direction, the memory strings being arranged in a second direction orthogonal to the first direction, the crystal lattice mismatch plane crossing the silicon crystal along the second direction without passing under gates of the nonvolatile memory cell transistors as viewed from a top of the silicon crystal layer, or crossing the silicon crystal along the first direction with passing under gates of the nonvolatile memory cell transistors as viewed from the top of the silicon crystal layer.

Abstract: Provided is an organic light emitting display, in which a semiconductor circuit unit of 2T-1C structure including a switching transistor and a driving transistor formed of single crystalline silicon is formed on a plastic substrate. A method of fabricating the single crystalline silicon includes: growing a single crystalline silicon layer to a predetermined thickness on a crystal growth plate; depositing a buffer layer on the single crystalline silicon layer; forming a partition layer at a predetermined depth in the single crystalline silicon layer by, e.g., implanting hydrogen ions in the single crystalline silicon layer from an upper portion of an insulating layer; attaching a substrate to the buffer layer; and releasing the partition layer of the single crystalline silicon layer by heating the partition layer from the crystal growth plate to obtain a single crystalline silicon layer of a predetermined thickness on the substrate.

Abstract: A process for fabricating a III-nitride power semiconductor device which includes forming a gate structure while providing a protective body over areas that are to receive power electrodes.

Abstract: A method of manufacturing a semiconductor device that forms laminate layers includes the steps of reducing contamination containing the single bond of carbon on at least one part of a surface on which the laminate films are formed by activated hydrogen before the laminate films are formed, and forming the laminate films on the surface on which the laminate films are formed.

Abstract: A method for forming an image sensor is provided. The method includes providing a semiconductor substrate having a pixel region and a peripheral circuit region, forming a photoelectric transformation section at the semiconductor substrate of the pixel region, forming a plurality of interlayer dielectrics over the semiconductor substrate with interconnections interposed therebetween, forming a passivation layer, partially patterning the passivation layer at the peripheral circuit region to form a via hole exposing the interconnection and removing the passivation layer and the underlying interlayer dielectric at the pixel region. The method further includes forming a conductive layer to fill the via hole and etching the conductive layer to remove the conductive layer at the pixel region and form a via plug and a conductive pad at the peripheral circuit region. The via plug fills the via hole and the conductive pad protrudes outwardly from the via hole.

Abstract: The present invention provides semiconductor-on-diamond devices, and methods for the formation thereof. In one aspect, a mold is provided which has an interface surface configured to inversely match a configuration intended for the device surface of a diamond layer. An adynamic diamond layer is then deposited upon the diamond interface surface of the mold, and a substrate is joined to the growth surface of the adynamic diamond layer. At least a portion of the mold can then be removed to expose the device surface of the diamond which has received a shape which inversely corresponds to the configuration of the mold's diamond interface surface. The mold can be formed of a suitable semiconductor material which is thinned to produce a final device. Optionally, a semiconductor material can be coupled to the diamond layer subsequent to removal of the mold.

Abstract: A nitride semiconductor light emitting device comprising an n-side nitride semiconductor layer and a p-side nitride semiconductor layer formed on a substrate, with a light transmitting electrode 10 formed on the p-side nitride semiconductor layer, and the p-side pad electrode 14 formed for the connection with an outside circuit, and the n-side pad electrode 12 formed on the n-side nitride semiconductor layer for the connection with the outside circuit, so as to extract light on the p-side nitride semiconductor layer side, wherein taper angles of end faces of the light transmitting electrode 10 and/or the p-side nitride semiconductor layer are made different depending on the position.

Abstract: A method of manufacturing a semiconductor device, includes the steps of: raising a temperature of a sapphire substrate which is included in the semiconductor device from a room temperature to a preheat temperature of 150° C. to 450° C. and keeping the preheat temperature for a first predetermined time, thereby preheating the semiconductor device; and subsequently raising a temperature of the sapphire substrate from the preheat temperature to a thermal reaction temperature of 500° C. or higher and keeping the thermal reaction temperature for a second predetermined time, thereby performing a thermal reaction treatment of the semiconductor device.

Abstract: According to the present invention, a method for fabricating a semiconductor device using a Silicon-On-Sapphire (SOS) wafer comprises a process for preparing a sapphire substrate, a process for forming a silicon (Si) layer on the sapphire substrate, a process for implanting silicon ions in the silicon layer, and a process for inducing epitaxial regrowth in the silicon layer after the silicon ion implantation. The silicon ion implantation process induces the number of interstitial Si having crystalline defects in the proximity of the surface of said silicon layer to be reduced below 6.5E2/cm3; and induces an ion implantation amount per unit area of said silicon ions in the proximity of an interface between said sapphire substrate and said silicon layer to be increased to 3.0E19 ions/cm3 or more.

Abstract: A semiconductor device capable of stabilizing operations thereof is provided. This semiconductor device comprises a substrate provided with a region having concentrated dislocations at least on part of the back surface thereof, a semiconductor element layer formed on the front surface of the substrate, an insulator film formed on the region of the back surface of the substrate having concentrated dislocations and a back electrode formed to be in contact with a region of the back surface of the substrate other than the region having concentrated dislocations.

Abstract: A gallium-nitride-based semiconductor stacked structure includes a low-temperature-deposited buffer layer and an active layer. The low-temperature-deposited buffer layer is composed of a Group III nitride material that has been grown at low temperature and includes a single-crystal layer in an as-grown state, the single-crystal layer being present in the vicinity of a junction area that is in contact with a (0001) (c) plane of a sapphire substrate. The active layer is composed of a gallium-nitride (GaN)-based semiconductor layer that is provided on the low-temperature-deposited buffer layer. The single-crystal layer is composed of a hexagonal AlxGayN (0.5<X?1, X+Y=1) crystal that contains aluminum in a predominant amount with respect to gallium such that a [2.?1.?1.0.] direction of the AlxGayN crystal orients along with a [2.?1.?1.0.] direction of the (0001) bottom plane of the sapphire substrate.

Abstract: In a method of making graphite devices, a preselected crystal face of a crystal is annealed to create a thin-film graphitic layer disposed against selected face. A preselected pattern is generated on the thin-film graphitic layer. A functional structure includes a crystalline substrate having a preselected crystal face. A thin-film graphitic layer is disposed on the preselected crystal face. The thin-film graphitic layer is patterned so as to define at least one functional structure.

Abstract: The present invention provides a bonded wafer, wherein at least a silicon single crystal layer is formed on a silicon single crystal wafer, the silicon single crystal layer has a crystal plane orientation of {110}, and the silicon single crystal wafer has a crystal plane orientation of {100}. The present invention also provides a method of producing a bonded wafer, wherein after at least a first silicon single crystal wafer having a crystal plane orientation of {110} and a second silicon single crystal wafer having a crystal plane orientation of {100} are bonded directly or bonded via an insulator film, the first silicon single crystal wafer is made into a thin film. Thereby, there can be provided a wafer possible to obtain a MIS device having good characteristics by utilizing a silicon single crystal wafer having the {110} plane.

Abstract: A semiconductor device capable of stabilizing operations thereof is provided. This semiconductor device comprises a substrate provided with a region having concentrated dislocations at least on part of the back surface thereof, a semiconductor element layer formed on the front surface of the substrate, an insulator film formed on the region of the back surface of the substrate having concentrated dislocations and a back electrode formed to be in contact with a region of the back surface of the substrate other than the region having concentrated dislocations.

Abstract: A nitride-based semiconductor substrate has a substrate formed of a nitride-based semiconductor crystal having a mixed crystal composition with three elements or more. The substrate has a diameter of not less than 25 mm, and a thermal resistivity in a range of 0.02 Kcm2/W to 0.5 Kcm2/W in its thickness direction.

Abstract: To provide a semiconductor device that excels in the manufacturing efficiency and device reliability, and a method for the manufacture thereof. The side of a device is composed of scribed grooves 13 and a cleavage plane 100.

Abstract: Semi-insulating Group III nitride layers and methods of fabricating semi-insulating Group III nitride layers include doping a Group III nitride layer with a shallow level p-type dopant and doping the Group III nitride layer with a deep level dopant, such as a deep level transition metal dopant. Such layers and/or method may also include doping a Group III nitride layer with a shallow level dopant having a concentration of less than about 1×1017 cm?3 and doping the Group III nitride layer with a deep level transition metal dopant. The concentration of the deep level transition metal dopant is greater than a concentration of the shallow level p-type dopant.

Abstract: A laser irradiation method using a laser crystallization method which can heighten an efficiency of substrate processing as compared to a conventional one and also heighten mobility of a semiconductor film is provided. It is an irradiation method of a laser beam in which, pattern information of a sub-island formed on a substrate is stored, and a beam spot of a laser beam is condensed so as to become linear, and by use of the stored pattern information, a scanning path of the beam spot is determined so as to include the sub-island, and by moving the beam spot along the scanning path, the laser beam is irradiated to the sub-island, characterized in that on the occasion of scanning the beam spot, when the beam spot has reached to the sub-island, the beam spot and the sub-island are contacted at a plurality of points.