Abstract: A light emitting device includes: a substrate; a laminated structure that is provided on the substrate and that includes a plurality of columnar portions; and an electrode provided at an opposite side of the laminated structure from the substrate. The columnar portion includes a first semiconductor layer, a second semiconductor layer of a conductivity type different from that of the first semiconductor layer, and a light emitting layer located between the first semiconductor layer and the second semiconductor layer. The electrode is connected to the second semiconductor layers in the plurality of columnar portions, and includes a first electrode layer formed of a material that has a work function smaller than that of the second semiconductor layer, and a second electrode layer that is connected to the first electrode layer and that has a work function smaller than that of the first electrode layer. An interface between the first electrode layer and the second electrode layer has an uneven shape.

Abstract: A light emitting device includes a base, a first semiconductor laser element, a second semiconductor laser element, a lens member, and a waveplate. The base has a bottom part. The first semiconductor laser element is disposed on the bottom part of the base. The second semiconductor laser element is disposed on the bottom part of the base. The second semiconductor laser element has a different polarization direction from a polarization direction of the first semiconductor laser element. The lens member is a member into which light beams from the first semiconductor element and the second semiconductor laser element enter. The waveplate is configured to change the polarization direction of light from the first semiconductor laser element.

Abstract: A semiconductor light emitting device includes a substrate having a first major surface and a second major surface, a semiconductor layer that includes a first semiconductor layer of a first conductive type formed on the first major surface of the substrate, a light emitting layer formed on the first semiconductor layer and a second semiconductor layer of a second conductive type formed on the light emitting layer, and a mesa structure formed in the semiconductor layer by selectively notching the first semiconductor layer, the light emitting layer and the second semiconductor layer so as to expose the first semiconductor layer, and a ratio of a luminescent area of the light emitting Layer with respect to an area of the first major surface of the substrate being set to equal to or smaller than 0.25.

Abstract: A semiconductor stripe laser has a first semiconductor region having a first conductivity type and a second semiconductor region having a different, second conductivity type. An active zone for generating laser radiation is located between the semiconductor regions. A stripe waveguide is formed in the second semiconductor region and is arranged to guide waves in a one-dimensional manner and is arranged for a current density of at least 0.5 kA/cm2. A second electrical contact is located on the second semiconductor region and on an electrical contact structure for external electrical contacting. An electrical passivation layer is provided in certain places on the stripe waveguide. A thermal insulation apparatus is located between the second electrical contact and the active zone and/or on the stripe waveguide.

Abstract: The invention relates to a method for manufacturing a component, especially of a gas turbine, made of a single crystal (SX) or directionally solidified (DS) nickelbase superalloy, including a heat treatment and a machining and/or mechanical treatment step. The ductility of the component is improved by doing the machining and/or mechanical treatment step prior to said heat treatment and a solution heat treatment of the component is done prior to the machining/mechanical treatment step.

Abstract: A single-step wet etch process is provided to isolate multijunction solar cells on semiconductor substrates, wherein the wet etch chemistry removes semiconductor materials nonselectively without a major difference in etch rate between different heteroepitaxial layers. The solar cells thus formed comprise multiple heterogeneous semiconductor layers epitaxially grown on the semiconductor substrate.

Abstract: A transistor device may include a first source portion including a first InSb material set and a first first-type dopant set. The transistor device may include a first drain portion including a second InSb material set and a first second-type dopant set. The transistor device may include a first gate and a corresponding first channel portion disposed between the first source portion and the first drain portion and including a third InSb material set. The transistor device may include a second drain portion including a first GaSb material set and a second first-type dopant set. The transistor device may include a second source portion including a second GaSb material set and a second second-type dopant set. The transistor device may include a second gate and a corresponding second channel portion disposed between the second source portion and the second drain portion and including a third GaSb material set.

Abstract: A device that includes: a substrate layer; a first set of source/drain component(s) defining an nFET (n-type field-effect transistor) region; a second set of source/drain component(s) defining a pFET (p-type field-effect transistor) region; a first suspended nanowire, at least partially suspended over the substrate layer in the nFET region and made from III-V material; and a second suspended nanowire, at least partially suspended over the substrate layer in the pFET region and made from Germanium-containing material. In some embodiments, the first suspended nanowire and the second suspended nanowire are fabricated by adding appropriate nanowire layers on top of a Germanium-containing release layer, and then removing the Germanium-containing release layers so that the nanowires are suspended.

Abstract: A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The semiconductor device includes a gate region surrounding the channel region. The gate region includes a gate electrode. A gate electrode length of the gate electrode is less than about 10 nm. A method of forming a semiconductor device is provided.

Abstract: Disclosed are methods and materials useful in the preparation of semiconductor devices. In particular embodiments, disclosed are methods for engineering polycrystalline aluminum nitride substrates that are thermally matched to further materials that can be combined therewith. For example, the polycrystalline aluminum nitride substrates can be engineered to have a coefficient of thermal expansion (CTE) that is closely matched to the CTE of a semiconductor material and/or to a material that can be used as a growth substrate for a semiconductor material. The invention also encompasses devices incorporating such thermally engineered substrates and semiconductor materials grown using such thermally engineered substrates. The thermally engineered substrates are advantageous for overcoming problems caused by damage arising from CTE mismatch between component layers in semiconductor preparation methods and materials.

Abstract: A semiconductor device includes a Si substrate having a principal plane that is a crystal surface inclined at an off angle of 0.1 degrees or less with respect to a (111) plane, an AlN layer that is provided so as to contact the principal plane of the Si substrate and is configured so that an FWHM of a rocking curve of a (002) plane by x-ray diffraction is not greater than 2000 seconds, and a GaN-based semiconductor layer formed on the AlN layer.

Abstract: Fabrication of a single crystal silicon solar cell with an insitu epitaxially deposited very highly doped p-type silicon back surface field obviates the need for the conventional aluminum screen printing step, thus enabling a thinner silicon solar cell because of no aluminum induced bow in the cell. Furthermore, fabrication of a single crystal silicon solar cell with insitu epitaxial p-n junction formation and very highly doped n-type silicon front surface field completely avoids the conventional dopant diffusion step and one screen printing step, thus enabling a cheaper manufacturing process.

Abstract: In a method for making a GaN article, an epitaxial nitride layer is deposited on a single-crystal substrate. A 3D nucleation GaN layer is grown on the epitaxial nitride layer by HVPE under a substantially 3D growth mode. A GaN transitional layer is grown on the 3D nucleation layer by HVPE under a condition that changes the growth mode from the substantially 3D growth mode to a substantially 2D growth mode. A bulk GaN layer is grown on the transitional layer by HVPE under the substantially 2D growth mode. A polycrystalline GaN layer is grown on the bulk GaN layer to form a GaN/substrate bi-layer. The GaN/substrate bi-layer may be cooled from the growth temperature to an ambient temperature, wherein GaN material cracks laterally and separates from the substrate, forming a free-standing article.

Abstract: The substrate comprises a first silicon layer, a target layer made from silicon-germanium alloy-base material forming a three-dimensional pattern with first and second securing areas and at least one connecting area. The first silicon layer is tensile stressed and/or the target layer contains carbon atoms. The first silicon layer is eliminated in the connecting area. The target layer of the connecting area is thermally oxidized so as to form the nanowire. The lattice parameter of the first silicon layer is identical to the lattice parameter of the material constituting the suspended beam, after said first silicon layer has been eliminated.

Abstract: A semiconductor device has a wafer for supporting the device and a conductive layer formed over a top surface of the wafer. A carrier wafer is permanently bonded over the conductive layer. Within the wafer and the carrier wafer, an interconnect structure is formed. The interconnect structure includes a first via formed in the wafer that exposes the conductive layer, a second via formed in the carrier wafer that exposes the conductive layer, a first metal layer deposited over the first via, the first metal layer in electrical contact with the conductive layer, and a second metal layer deposited over the second via, the second metal layer in electrical contact with the conductive layer. First and second insulation layers are deposited over the first and second metal layers respectively. The first or second insulation layer has an etched portion to expose a portion of the first or second metal layer.

Abstract: A semiconductor structure is provided. The semiconductor structure includes one or more III-IV material-based semiconductor layers. A tensile-strained Ge layer is formed on the one or more a III-IV material-based semiconductor layers. The tensile-strained Ge layer is produced through lattice-mismatched heteroepitaxy on the one or more a III-IV material-based semiconductor layers.

Abstract: There are provided a semiconductor device having a structure which can realize not only suppression of a punch-through current but also reuse of a silicon wafer used for bonding, in manufacturing a semiconductor device using an SOI technique, and a manufacturing method thereof. A semiconductor film into which an impurity imparting a conductivity type opposite to that of a source region and a drain region is implanted is formed over a substrate, and a single crystal semiconductor film is bonded to the semiconductor film by an SOI technique to form a stacked semiconductor film. A channel formation region is formed using the stacked semiconductor film, thereby suppressing a punch-through current in a semiconductor device.

Abstract: One surface of a single crystal semiconductor substrate is irradiated with ions to form a damaged region in the single crystal semiconductor substrate. An insulating layer is formed over the one surface of the single crystal semiconductor substrate. A surface of a substrate having an insulating surface and a surface of the insulating layer are disposed in contact with each other to bond the substrate having the insulating surface and the single crystal semiconductor substrate to each other. Heat treatment is performed to divide the single crystal semiconductor substrate along the damaged region and to form a semiconductor layer over the substrate having the insulating surface. One surface of the semiconductor layer is irradiated with light from a flash lamp under conditions where the semiconductor layer is not melted, to repair a defect.

Abstract: The object of this invention is to provide a high-output type nitride light emitting device. The nitride light emitting device comprises an n-type nitride semiconductor layer, a p-type nitride semiconductor layer and an active layer therebetween, wherein the light emitting device comprises a gallium-containing nitride semiconductor layer prepared by crystallization from supercritical ammonia-containing solution in the nitride semiconductor layer.

Abstract: A method includes forming an electrical insulator material over an integrated circuit having a metal-containing conductive interconnect and activating a dopant in a semiconductor material of a substrate to provide a doped region. The doped region provides a junction of opposite conductivity types. After activating the dopant, the substrate is bonded to the insulator material and at least some of the substrate is removed where bonded to the insulator material. After the removing, a memory cell is formed having a word line, an access diode, a state-changeable memory element containing chalcogenide phase change material, and a bit line all electrically connected in series, the access diode containing the junction as a p-n junction. A memory device includes an adhesion material over the insulator material and bonding the word line to the insulator material.

Abstract: A method of forming a semiconductor structure includes providing a substrate and providing a detach region which is carried by the substrate. A device structure which includes a stack of crystalline semiconductor layers is provided, wherein the detach region is positioned between the device structure and substrate. The stack is processed to form a vertically oriented semiconductor device.

Abstract: A semiconductor process and apparatus provide a dual or hybrid substrate by forming a second semiconductor layer (214) that is isolated from, and crystallographically rotated with respect to, an underlying first semiconductor layer (212) by a buried insulator layer (213); forming an STI region (218) in the second semiconductor layer (214) and buried insulator layer (213); exposing the first semiconductor layer (212) in a first area (219) of a STI region (218); epitaxially growing a first epitaxial semiconductor layer (220) from the exposed first semiconductor layer (212); and selectively etching the first epitaxial semiconductor layer (220) and the second semiconductor layer (214) to form CMOS FinFET channel regions (e.g., 223) and planar channel regions (e.g., 224) from the first epitaxial semiconductor layer (220) and the second semiconductor layer (214).

Abstract: The GaN single-crystal substrate 11 in accordance with the present invention has a polished surface subjected to heat treatment for at least 10 minutes at a substrate temperature of at least 1020° C. in a mixed gas atmosphere containing at least an NH3 gas. As a consequence, an atomic rearrangement is effected in the surface of the substrate 11 in which a large number of minute defects are formed by polishing, so as to flatten the surface of the substrate 11. Therefore, the surface of an epitaxial layer 12 formed on the substrate 11 can be made flat.

Abstract: The invention is directed to a group-III nitride vertical-rods substrate. The group-III vertical-rods substrate comprises a substrate, a buffer layer and a vertical rod layer. The buffer layer is located over the substrate. The vertical rod layer is located on the buffer layer and the vertical rod layer is comprised of a plurality of vertical rods standing on the buffer layer.

Abstract: The invention provides a method for producing a group III nitride based semiconductor having a reduced number of crystal defects. A GaN layer 2 is epitaxially grown on a sapphire substrate 1 having C-plane as a main plane (FIG. 1A). Then, the layer is wet-etched by use of a 25% aqueous TMAH solution at 85° C. for one hour, to thereby form an etch pit 4 (FIG. 1B). Then, a GaN layer 5 is grown on the GaN layer 2 through the ELO method (FIG. 1C). The thus-formed GaN layer 5 has a screw dislocation density lower than that of the GaN layer 2.

Abstract: An insulating film is formed as a pore-wall protective film (103) on pore walls in a porous layer (102) by the use of a mixed gas plasma of a noble gas and an insulating film forming gas generated by microwave excitation. As a result, the pore-wall protective film can have film properties as a protective film.

Abstract: Disclosed is a semiconductor wafer and method of fabricating the same. The semiconductor wafer is comprised of a semiconductor layer formed on an insulation layer on a base substrate. The semiconductor layer includes a surface region organized in a first crystallographic orientation, and another surface region organized in a second crystallographic orientation. The performance of a semiconductor device with unit elements that use charges, which are activated in high mobility to the crystallographic orientation, as carriers is enhanced. The semiconductor wafer is completed by forming the semiconductor layer with the second crystallographic orientation on the plane of the first crystallographic orientation, growing an epitaxial layer, forming the insulation layer on the epitaxial layer, and then bonding the insulation layer to the base substrate.

Abstract: Method of manufacturing a thin film device substrate wherein no trench fabrication is required to be applied onto the substrate surface, and a material which is impervious to light can be used, and the substrate can be peeled off quickly. Firstly, a peeling-off film, a silicon oxide film and an amorphous silicon film are formed in succession on a glass substrate, and the amorphous silicon film is irradiated from above to obtain a polycrystalline silicon film. Subsequently, using the polycrystalline silicon film as an active layer, a TFT is formed, and then a plastic substrate is bonded thereon, and finally the glass substrate is peeled off with the peeling-off film, to complete transfer of the TFT. Because the peeling-off film has a gap space, its etching rate is high. Therefore, it is unnecessary to form a trench for supplying an etchant on the surface of the glass substrate.

Abstract: A thin film transistor (TFT) and a method of manufacturing the same are provided. The TFT includes a transparent substrate, an insulating layer on a region of the transparent substrate, a monocrystalline silicon layer, which includes source, drain, and channel regions, on the insulating layer and a gate insulating film and a gate electrode on the channel region of the monocrystalline silicon layer.

Abstract: In a method of manufacturing a semiconductor device, a first substrate and a second substrate, which include a plurality of memory cells and selection transistors, respectively, are provided. A first insulating interlayer and a second insulating interlayer are formed on the first substrate and the second substrate, respectively, to cover the memory cells and the selection transistors. A lower surface of the second substrate is partially removed to reduce a thickness of the second substrate. The lower surface of the second substrate is attached to the first insulating interlayer. Plugs are formed through the second insulating interlayer, the second substrate and the first insulating interlayer to electrically connect the selection transistors in the first substrate and the second substrate to the plugs. Thus, impurity ions in the first substrate will not diffuse during a thermal treatment process.

Abstract: A junction semiconductor device having a drain region including a low-resistance layer of a first conductive type formed on one surface of a semiconductor crystal, a source region including a low-resistance layer of a first conductive type formed on the other surface of the semiconductor crystal, a gate region of a second conductive type formed on the periphery of the source region, a high-resistance layer of a first conductive type between the source region and the drain region, and a recombination-inhibiting semiconductor layer of a second conductive type provided in the vicinity of the surface of the semiconductor crystal between the gate region and the source region.

Abstract: Methods and systems for growing uniform oxide layers include an example method including growing a first layer of oxide on first and second facets of the substrate, with the first facet having a faster oxide growth rate. The oxide is removed from the first facet and a second oxide layer is grown on the first and second facets. Removing the oxide from the first facet includes shielding the second facet and exposing the substrate to a deoxidizing condition. The second facet is then exposed to receive the second oxide layer. Areas having differing oxide thicknesses are also grown by repeatedly growing oxide layers, selectively shielding areas, and removing oxide from exposed areas.

Abstract: The invention relates to a semiconductor device (10) consisting of a substrate (11) and a semiconductor body (2) comprising a strip-shaped semiconductor region (3,3A,3B) of silicon in which a field effect transistor is formed, wherein a source region (4) of a first conductivity type, a channel region (33) of a second conductivity type opposed to the first, and a drain region (5) of the first conductivity type are arranged in succession, successively, seen in the longitudinal direction of the strip-shaped semiconductor region (3,3A,3B), and wherein the channel region (33) is provided with a gate dielectric (6), on which a first gate electrode (7) is present on a first vertical side of the strip-shaped semiconductor region (3,3A,3B), which gate electrode (7) is provided with a first connection region (7A), and on which a second gate electrode (8) is present on a second vertical side of the strip-shaped semiconductor region (3,3A,3B) positioned opposite the first vertical side, which second gate electrode (8) is

Abstract: A method for fabrication organic light emitting diode (OLED) displays. A white light OLED element is formed on the first substrate. A micro-cavity layer is formed on a second substrate. A color filter is formed on the micro-cavity layer. The first and the second substrates are assembled, wherein the light of white OLED element passes through the color filter and the micro-cavity layer.

Abstract: An integrated semiconductor structure containing at least one device formed upon a first crystallographic surface that is optimal for that device, while another device is formed upon a second different crystallographic surface that is optimal for the other device is provided. The method of forming the integrated structure includes providing a bonded substrate including at least a first semiconductor layer of a first crystallographic orientation and a second semiconductor layer of a second different crystallographic orientation. A portion of the bonded substrate is protected to define a first device area, while another portion of the bonded substrate is unprotected. The unprotected portion of the bonded substrate is then etched to expose a surface of the second semiconductor layer and a semiconductor material is regrown on the exposed surface. Following planarization, a first semiconductor device is formed in the first device region and a second semiconductor device is formed on the regrown material.

Abstract: The present invention provides a bonded wafer, wherein at least a silicon single crystal layer is formed on a silicon single crystal wafer, the silicon single crystal layer has a crystal plane orientation of {110}, and the silicon single crystal wafer has a crystal plane orientation of {100}. The present invention also provides a method of producing a bonded wafer, wherein after at least a first silicon single crystal wafer having a crystal plane orientation of {110} and a second silicon single crystal wafer having a crystal plane orientation of {100} are bonded directly or bonded via an insulator film, the first silicon single crystal wafer is made into a thin film. Thereby, there can be provided a wafer possible to obtain a MIS device having good characteristics by utilizing a silicon single crystal wafer having the {110} plane.

Abstract: The process comprises a step of growing epitaxially mixed crystals of a compound semiconductor represented by the composition formula Inx(Ga1?yAly)1?xP on a GaAs substrate 12 to form an epi-wafer having an n-type cladding layer 14 (0.45<x<0.

Abstract: Optical devices and methods for constructing the same are disclosed. An example optical device includes an optical transmitter, a photodetector and a waveguide optically coupling the optical transmitter and the photodetector. It also includes a substrate having a first cavity to receive the optical transmitter and a second cavity to receive the second transmitter. The first and second cavities are located and dimensioned to passively align the optical transmitter, the waveguide and the photodetector when the transmitter is inserted into the first cavity and the photodetector is inserted into the second cavity.