Epitaxial Re-growth Of Non-monocrystalline Semiconductor Material, E.g., Lateral Epitaxy By Seeded Solidific Ation, Solid-state Crystallization, Solid-state Graphoepitaxy, Explosive Crystallization, Grain Growth In Polycrystalline Material (epo) Patents (Class 257/E21.133)
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Publication number: 20090004835Abstract: Wafers of semi-conducting material are formed by moulding and directional crystallization from a liquid mass of this material. A seed, situated at the bottom of the crucible, presents an orientation along non-dense crystallographic planes. The mould is filled with the molten semi-conducting material by means of a piston or by creation of a pressure difference in the device. The mould is preferably coated with a non-wettable anti-adhesive deposit.Type: ApplicationFiled: June 24, 2008Publication date: January 1, 2009Applicant: COMMISSARIAT A L' ENERGIE ATOMIQUEInventors: Beatrice Drevet, Dominique Sarti, Denis Camel, Jean-Paul Garandet
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Patent number: 7470575Abstract: A process for fabricating a semiconductor device including the steps of: introducing into an amorphous silicon film, a metallic element which accelerates the crystallization of the amorphous silicon film; applying heat treatment to the amorphous silicon film to obtain a crystalline silicon film; irradiating a laser beam or an intense light to the crystalline silicon film; and heat treating the crystalline silicon film irradiated with a laser beam or an intense light.Type: GrantFiled: June 24, 2005Date of Patent: December 30, 2008Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hisashi Ohtani, Takeshi Fukunaga, Akiharu Miyanaga
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Publication number: 20080305618Abstract: A method of forming a polycrystalline semiconductor film, which includes irradiating an amorphous semiconductor film formed on an insulating substrate with light to convert the amorphous semiconductor into a polycrystalline semiconductor with laterally grown crystal grains, thus forming a polycrystalline semiconductor film, wherein crystal growth in the semiconductor is controlled such that first crystal grains laterally grow in the first direction along a X-axis from the first group of initial nuclei, the second crystal grains laterally grow in the second direction opposite to the first direction along the X-axis from the second group of initial nuclei arranged apart from the first group of initial nuclei along the X-axis, and the first crystal grains collide against the second crystal grains at different points in time along a Y-axis.Type: ApplicationFiled: June 5, 2008Publication date: December 11, 2008Inventors: Daisuke IGA, Yukio TANIGUCHI
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Patent number: 7459353Abstract: A method of forming an integrated circuit can be provided by successively laterally forming single crystalline thin film regions from an amorphous thin film using a lower single crystalline seed layer.Type: GrantFiled: March 17, 2006Date of Patent: December 2, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Hoon Son, Yu-Gyun Shin, Jong-Wook Lee
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Patent number: 7452757Abstract: Silicon-on-insulator (SOI) structures are provided by forming a single-crystal insulator over a substrate, followed by heteroepitaxy of a semiconductor layer thereover. Atomic layer deposition (ALD) is preferably used to form an amorphous insulator, followed by solid phase epitaxy to convert the layer into a single-crystal structure. Advantageously, the crystalline insulator has a lattice structure and lattice constant closely matching that of the semiconductor formed over it, and a ternary insulating material facilitates matching properties of the layers. Strained silicon can be formed without need for a buffer layer. An amorphous SiO2 layer can optionally be grown underneath the insulator. In addition, a buffer layer can be grown, either between the substrate and the insulator or between the insulator and the semiconductor layer, to produce desired strain in the active semiconductor layer.Type: GrantFiled: May 7, 2003Date of Patent: November 18, 2008Assignee: ASM America, Inc.Inventors: Christiaan J. Werkhoven, Ivo Raaijmakers, Chantal Arena
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Publication number: 20080268622Abstract: A method of forming a crystalline silicon layer on a microrough face of a substrate by reducing the microroughness of the face and then performing a metal induced crystallization process on the face is disclosed. The method further comprises, after metal induced crystallization and before removing the metal layer, removing silicon islands using the metal layer as a mask.Type: ApplicationFiled: May 1, 2008Publication date: October 30, 2008Applicant: Interuniversitair Microelektronica Centrum (IMEC)Inventor: Dries Van Gestel
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Patent number: 7432141Abstract: A method is disclosed to form a large-grain, lightly p-doped polysilicon film suitable for use as a channel region in thin film transistors. The film is preferably deposited lightly in situ doped with boron atoms by an LPCVD method at temperatures sufficiently low that the film is amorphous as deposited. After deposition, such a film contains an advantageous balance of boron, which promotes crystallization, and hydrogen, which retards crystallization. The film is then preferably crystallized by a low-temperature anneal at, for example, about 560 degrees for about twelve hours. Alternatively, crystallization may occur during an oxidation step performed, for example at about 825 degrees for about sixty seconds. The oxidation step forms a gate oxide for a thin film transistor device, for example a tunneling oxide for a SONOS memory thin film transistor device.Type: GrantFiled: September 8, 2004Date of Patent: October 7, 2008Assignee: SanDisk 3D LLCInventors: Shuo Gu, Sucheta Nallamothu
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Publication number: 20080230779Abstract: Novel articles and methods to fabricate the same resulting in flexible, large-area, [100] or [110] textured, semiconductor-based, electronic devices are disclosed. Potential applications of resulting articles are in areas of photovoltaic devices, flat-panel displays, thermophotovoltaic devices, ferroelectric devices, light emitting diode devices, computer hard disc drive devices, magnetoresistance based devices, photoluminescence based devices, non-volatile memory devices, dielectric devices, thermoelectric devices and quantum dot laser devices.Type: ApplicationFiled: January 28, 2008Publication date: September 25, 2008Inventor: Amit Goyal
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Publication number: 20080206967Abstract: A thin semiconductor film is crystallized in a high yield by being irradiated with laser light. An insulating film, a semiconductor film, an insulating film, and a semiconductor film are stacked in this order over a substrate. Laser light irradiation is performed from above the substrate to melt the semiconductor films of a lower layer and an upper layer, whereby the semiconductor film of the lower layer is crystallized. With the laser light irradiation, the semiconductor film of the upper layer changes to a liquid state, thereby reflecting the laser light and preventing the semiconductor film of the lower layer from being overheated with the laser light. Further, by melting the semiconductor film of the upper layer as well, time for melting the semiconductor film of the lower layer can be extended.Type: ApplicationFiled: February 19, 2008Publication date: August 28, 2008Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Hidekazu MIYAIRI, Sho KATO
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Patent number: 7413939Abstract: A method of fabricating a silicon-germanium CMOS includes preparing a silicon substrate wafer; depositing an insulating layer on the silicon substrate wafer; patterning and etching the insulating layer; depositing a layer of polycrystalline germanium on the insulating layer and on at least a portion of the silicon substrate wafer; patterning and etching the polycrystalline germanium; encapsulating the polycrystalline germanium with an insulating material; rapidly thermally annealing the wafer at a temperature sufficient to melt the polycrystalline germanium; cooling the wafer to promote liquid phase epitaxy of the polycrystalline germanium, thereby forming a single crystal germanium layer; and completing the CMOS device.Type: GrantFiled: June 10, 2005Date of Patent: August 19, 2008Assignee: Sharp Laboratories of America, Inc.Inventors: Sheng Teng Hsu, Jong-Jan Lee, Jer-Shen Maa, Douglas J. Tweet
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Patent number: 7384860Abstract: The present invention relates to a method of manufacturing a semiconductor device having an excellent gettering effect. In this method, when phosphorus is added to a poly-Si film, which has been crystallized by the addition of a metal, to subject the resultant poly-Si film to the heat treatment to carry out gettering therefor, the device is performed for the shape of the island-like insulating film on the poly-Si film which is employed when implanting phosphorus. Thereby, the area of the boundary surface between the region to which phosphorus has been added and the region to which no phosphorus has been added is increased to enhance gettering efficiency.Type: GrantFiled: September 15, 2004Date of Patent: June 10, 2008Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Osamu Nakamura, Manabu Katsumura, Shunpei Yamazaki
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Patent number: 7375011Abstract: A method of making an ex-situ doped semiconductor transport layer for use in an electronic device includes: growing a first set of semiconductor nanoparticles having surface organic ligands in a colloidal solution; growing a second set of dopant material nanoparticles having surface organic ligands in a colloidal solution; depositing a mixture of the first set of semiconductor nanoparticles and the second set of dopant material nanoparticles on a surface, wherein there are more semiconductor nanoparticles than dopant material nanoparticles; performing a first anneal of the deposited mixture of nanoparticles so that the organic ligands boil off the surfaces of the first and second set of nanoparticles; performing a second anneal of the deposited mixture so that the semiconductor nanoparticles fuse to form a continuous semiconductor layer and the dopant material atoms diffuse out from the dopant material nanoparticles and into the continuous semiconductor layer.Type: GrantFiled: February 22, 2007Date of Patent: May 20, 2008Assignee: Eastman Kodak CompanyInventor: Keith B. Kahen
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Patent number: 7364990Abstract: First and second preliminary epitaxial layers are grown from single-crystalline seeds in openings in an insulation layer until the first and second epitaxial layers are connected to each other. While the first and second preliminary epitaxial layers are being grown, a connection structure of a material having an amorphous state is formed on a portion of the insulation layer located between the first and second preliminary epitaxial layers. The material having an amorphous state is then changed into material having a single-crystalline state. Thus, portions of the first and second epitaxial layers are connected to each other through the connection structure so that the epitaxial layers and the connection structure constitute a single-crystalline structure layer that is free of voids for use as a channel layer or the like of a semiconductor device.Type: GrantFiled: December 13, 2005Date of Patent: April 29, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Hoon Son, Yu-Gyun Shin, Jong-Wook Lee
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Patent number: 7358165Abstract: A crystallizing method that can control the orientation of crystal grains with the use of a metal element for promoting crystallization. In the method, the metal element for promoting crystallization is added to selectively form a crystalline semiconductor film, and the crystalline semiconductor film is irradiated with a pulsed laser to form a film having small crystal grains in grid pattern at a regular intervals wherein adjacent crystal grains have the same orientation.Type: GrantFiled: July 9, 2004Date of Patent: April 15, 2008Assignee: Semiconductor Energy Laboratory Co., LtdInventors: Hironobu Shoji, Akihisa Shimomura, Masaki Koyama
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Patent number: 7348222Abstract: It is an object of the present invention to provide a method for removing the metal element from the semiconductor film which is different from the conventional gettering step for removing the metal element from the semiconductor film. In the present invention, when Ni element (Ni) is used as the metal element and a silicon-based film (referred to as a silicon film) is used as the semiconductor film, nickel silicide segregates in the ridge formed in the silicon film by irradiating the pulsed laser light. Next, etching solution of hydrofluoric acid based etchant is used to remove the nickel silicide segregated in the ridge. When the surface of the semiconductor film is rough after removing the metal element by means of etching, the laser light may be irradiated to the semiconductor film under the insert atmosphere to flatten the surface thereof.Type: GrantFiled: June 29, 2004Date of Patent: March 25, 2008Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Akihisa Shimomura, Hideto Ohnuma, Hironobu Shoji
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Patent number: 7335539Abstract: A method for making a thin-film semiconductor device includes an annealing step of irradiating an amorphous semiconductor thin film with a laser beam so as to crystallize the amorphous semiconductor thin film. In the annealing step, the semiconductor thin film is continuously irradiated with the laser beam while shifting the position of the semiconductor thin film irradiated with the laser beam at a predetermined velocity so that excess hydrogen can be removed from the region irradiated with the laser beam without evaporating and expanding hydrogen ions in the semiconductor thin film.Type: GrantFiled: August 16, 2007Date of Patent: February 26, 2008Assignee: Sony CorporationInventors: Akio Machida, Hirotaka Akao, Takahiro Kamei, Isamu Nakao
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Publication number: 20080020554Abstract: [Purpose] It is an object to obtain a crystalline silicon film having preferable characteristics for a thin film transistor. [Structure] A crystalline silicon film having improved crystallinity is obtained by the following steps: forming a silicon nitride film substantially in contact with an amorphous silicon film on glass substrate; introducing a catalyst element such as nickel; performing an annealing treatment at a temperature of 500 to 600° C. for crystallization; and further irradiating it with a laser light, thereby a crystalline silicon film having improved crystallinity can be obtained. By using the crystalline silicon film thus obtained, a semiconductor device such as a TFT having improved characteristic can be obtained.Type: ApplicationFiled: June 6, 2007Publication date: January 24, 2008Inventors: Hisashi Ohtani, Akiharu Miyanaga, Hongyong Zhang, Naoaki Yamaguchi
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Patent number: 7317205Abstract: Semiconductor layers for serving as active layers of a plurality of thin film transistors in a pixel are arranged in the same direction and irradiated with laser light with the scanning direction matched to the channel length direction of the semiconductor layers. It is possible to coincide the crystal growth direction with the carrier moving direction, and high field effect mobility can be obtained. Also, semiconductor layers for serving as active layers of a plurality of thin film transistors in a driving circuit and in a CPU are arranged in the same direction, and are irradiated with laser light with the scanning direction matched to the channel length direction of the semiconductor layers.Type: GrantFiled: September 10, 2002Date of Patent: January 8, 2008Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hideaki Kuwabara
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Patent number: 7297983Abstract: Integrated circuit device comprising a conductive layer and a poly-crystalline silicon layer, wherein the integrated circuit device further comprises an intermediate counter-stress layer. This intermediate counter-stress layer is arranged between the poly-crystalline silicon layer and the conductive layer, and enables stress-reduced crystallization of the poly-crystalline silicon layer. Further, the intermediate counter-stress layer is amorphous at and below a poly-silicon crystallization temperature.Type: GrantFiled: December 29, 2005Date of Patent: November 20, 2007Assignee: Infineon Technologies AGInventors: Thomas Hecht, Henry Bernhardt, Christian Kapteyn
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Patent number: 7294539Abstract: A method of manufacturing a semiconductor device, includes: forming an insulating layer on a single crystal semiconductor substrate; forming a non-crystalline semiconductor layer on the insulating layer; forming an insulating film on the non-crystalline semiconductor layer; forming an opening section for exposing a part of a surface of the single crystal semiconductor substrate through the insulating film, the non-crystalline semiconductor layer and the insulating layer; forming a single crystal semiconductor layer embedded in the opening section so as to have contact with the non-crystalline semiconductor layer; removing the insulating film and the insulating layer while the single crystal semiconductor layer supporting the non-crystalline semiconductor layer above the single crystal semiconductor substrate; forming a single-crystallized semiconductor layer obtained by single-crystallizing the non-crystalline semiconductor layer using the single crystal semiconductor layer as a seed by providing a thermal trType: GrantFiled: March 29, 2006Date of Patent: November 13, 2007Assignee: Seiko Epson CorporationInventor: Kei Kanemoto
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Patent number: 7294857Abstract: A method of manufacturing a thin film transistor array panel is provided, which includes: depositing an amorphous silicon layer on an insulating substrate; converting the amorphous silicon layer to a polysilicon layer by a plurality of laser shots using a mask; forming a gate insulating layer on the polysilicon layer; forming a plurality of gate lines on the gate insulating layer; forming a first interlayer insulating layer on the gate lines; forming a plurality of data lines on the first interlayer insulating layer; forming a second interlayer insulating layer on the data lines; and forming a plurality of pixel electrodes on the second interlayer insulating layer, wherein the mask comprises a plurality of transmitting areas and a plurality of blocking areas arranged in a mixed manner.Type: GrantFiled: February 3, 2005Date of Patent: November 13, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-Jae Kim, Sook-Young Kang, Dong-Byum Kim, Su-Gyeong Lee, Myung-Koo Kang
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Publication number: 20070252229Abstract: A manufacturing method of a field effect transistor in which, a patterned gate electrode is provided on a substrate, and a gate insulator is provided on the substrate and the gate electrode, a source electrode and a drain electrode are spaced apart from each other on the gate insulator, a region to be a channel between the source electrode and the drain electrode is provided, a boundary between the region and either one of the source electrode and the drain electrode is linear, a boundary between the region and either one of the drain electrode and the source electrode is non-linear, the boundary has a continuous or discontinuous shape, and the boundary part has a plurality of recess parts, the surface of the region has hydrophilicity and a peripheral region of the region prepares a member having water-repellency, and a solution including semiconductor organic molecules is supplied to the region, and the solution is dried.Type: ApplicationFiled: April 11, 2007Publication date: November 1, 2007Inventors: MASAAKI FUJIMORI, Tomihiro Hashizume, Masahiko Ando
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Publication number: 20070243670Abstract: A method for fabricating a thin film transistor (“TFT”) device includes providing a substrate, forming a patterned amorphous silicon layer over the substrate including a pair of first regions, a second region disposed between the pair of first regions, and at least one third region, each of which being disposed between and contiguous with the second region and each of the pair of first regions, the second region including a sub-region contiguous with each of the at least one third region, forming a heat retaining layer over the substrate, irradiating the patterned amorphous silicon layer with a laser through the heat retaining layer to form a patterned crystallized silicon layer corresponding to the patterned amorphous silicon layer including a grain boundary extending substantially across a crystallized sub-region corresponding to the sub-region, and forming a patterned conductive layer over a portion of a crystallized second region of the patterned crystallized silicon layer corresponding to the second regiType: ApplicationFiled: April 17, 2006Publication date: October 18, 2007Applicant: Industrial Technology Research InstituteInventors: Chi-Lin Chen, Po-Hao Tsai, Hung-Tse Chen, Yu-Cheng Chen, Jia-Xing Lin
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Methods of fabricating silicon-on-insulator substrates having a laser-formed single crystalline film
Publication number: 20070224789Abstract: In some methods of fabricating a silicon-on-insulator substrate, a semiconductor substrate is provided that includes a single crystalline structure within at least a defined region thereof. A first insulating film is formed on the defined region of the semiconductor substrate with an opening that exposes a portion of the defined region of the semiconductor substrate having the single crystalline structure. A first non-single crystalline film is formed on the exposed portion of the semiconductor substrate and that at least substantially fills the opening in the first insulating film. A laser beam is generated that heats the first non-single crystalline film to change the first non-single crystalline film into a first single crystalline film having substantially the same single crystalline structure as the defined region of the semiconductor substrate.Type: ApplicationFiled: March 12, 2007Publication date: September 27, 2007Inventors: Sungkwan Kang, Yong-Hoon Son, Jongwook Lee, Yugyun Shin -
Publication number: 20070224788Abstract: One aspect of the present invention relates to a method for fabricating a polycrystalline silicon film. In one embodiment, the method includes the steps of providing a substrate having a thermally-grown silicon dioxide layer, forming an amorphous silicon film on the thermally-grown silicon dioxide layer of the substrate, forming an aluminum layer on the amorphous silicon film to form a structure having the substrate, the amorphous silicon film and the aluminum layer, and annealing the structure at an annealing temperature for a period of time in an N2 environment with a ramp-up time to crystallize the amorphous silicon film to form a polycrystalline silicon film.Type: ApplicationFiled: March 23, 2007Publication date: September 27, 2007Applicant: Board of Trustees of the University of ArkansasInventors: Min Zou, Li Cai, William David Brown
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Patent number: 7273774Abstract: A method for making a thin-film semiconductor device includes an annealing step of irradiating an amorphous semiconductor thin film with a laser beam so as to crystallize the amorphous semiconductor thin film. In the annealing step, the semiconductor thin film is continuously irradiated with the laser beam while shifting the position of the semiconductor thin film irradiated with the laser beam at a predetermined velocity so that excess hydrogen can be removed from the region irradiated with the laser beam without evaporating and expanding hydrogen ions in the semiconductor thin film.Type: GrantFiled: September 27, 2005Date of Patent: September 25, 2007Assignee: Sony CorporationInventors: Akio Machida, Hirotaka Akao, Takahiro Kamei, Isamu Nakao
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Patent number: 7271041Abstract: Prior to converting a non-single crystal material of a semiconductor film into a single crystal material through the use of a laser beam, at least one dopant is introduced into whole of the semiconductor film. Then, the non-single crystal semiconductor film is irradiated with a laser beam to crystallize the semiconductor film. In this case, a ratio between quasi-fermi level of the single crystal material within one of transistor formation regions used to form transistors of different conductivity types and quasi-fermi level of the single crystal material within the other thereof is made to be between 0.5:1 and 2.0:1. Thus, transistors of different conductivity types are formed in the crystallized semiconductor film.Type: GrantFiled: April 11, 2005Date of Patent: September 18, 2007Assignee: NEC LCD Technologies, Ltd.Inventor: Mitsuasa Takahashi
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Patent number: 7256109Abstract: A high-quality isotropic polycrystalline silicon (poly-Si) and a method for fabricating high quality isotropic poly-Si film are provided. The method includes forming a film of amorphous silicon (a-Si) and using a MISPC process to form poly-Si film in a first area of the a-Si film. The method then anneals a second area, included in the first area, using a Laser-Induced Lateral Growth (LILaC) process. In some aspects, a 2N-shot laser irradiation process is used as the LILaC process. In some aspects, a directional solidification process is used as the LILaC process. In response to using the MISPC film as a precursor film, the method forms low angle grain boundaries in poly-Si in the second area.Type: GrantFiled: April 4, 2005Date of Patent: August 14, 2007Assignee: Sharp Laboratories of America, Inc.Inventors: Masao Moriguchi, Apostolos T. Voutsas, Mark A. Crowder
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Patent number: 7253010Abstract: A crystallization method is provided which improves a crystallization process by deciding a best-fit focal plane for a laser beam using a test mask and then applying the decided best-fit focal plane to the crystallization process. The crystallization method includes loading a test mask on a mask stage; deciding a best-fit focal plane by performing a crystallization test using the test mask, checking the test result and deciding conditions of a best-fit focal plane from the test result; moving the mask stage to a position corresponding to the best-fit focal plane; loading a mask for crystallization process onto the moved mask stage; and performing the crystallization process using the mask for crystallization process.Type: GrantFiled: December 22, 2004Date of Patent: August 7, 2007Assignee: LG.Philips LCD Co., Ltd.Inventors: Hyun Sik Seo, Yun Ho Jung, Young Joo Kim, JaeSung You
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Patent number: 7247527Abstract: It is an object of the present invention to provide a method for manufacturing a crystalline semiconductor film comprising the steps of crystallizing with the use of the metal element for promoting the crystallization to control the orientation and irradiating the laser once to form a crystalline semiconductor film having a small crystal grain arranged in a grid pattern at a regular interval. In the present invention made in view of the above object, a ridge forms a grid pattern on a surface of the crystalline semiconductor film in such a way that a crystalline semiconductor film is formed by adding the metal element for promoting the crystallization to the amorphous semiconductor film and the pulsed laser whose polarization direction is controlled is irradiated thereto. As the means for controlling the polarization direction, a half-wave plate or a mirror is used.Type: GrantFiled: July 28, 2004Date of Patent: July 24, 2007Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Akihisa Shimomura, Masaki Koyama, Hironobu Shoji
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Publication number: 20070166965Abstract: The present invention is to provide a technique that can increase productivity with high output power by combining a plurality of laser beams on an irradiation surface without any difficulties in optical alignment According to this technique, laser beams having different wavelengths are combined using a plurality of laser oscillators and a dichroic mirror, or additionally a polarizer. For example, a first laser beam emitted from a first laser oscillator is combined with a second laser beam emitted from a second laser oscillator having different wavelength from the first laser beam in such a way that the first laser beam passes through a dichroic mirror and the second laser beam is reflected on the dichroic mirror, and the combined laser beam is projected to an irradiation surface.Type: ApplicationFiled: June 15, 2005Publication date: July 19, 2007Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Koichiro Tanaka, Yoshiaki Yamamoto
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Publication number: 20070161164Abstract: A mask is formed selectively on a crystalline silicon film containing a catalyst element, and an amorphous silicon film is formed so as to cover the mask. Phosphorus is implanted into the amorphous silicon film and the portion of the crystalline silicon film which is not covered with the mask. The silicon films are then heated by rapid thermal annealing (RTA). By virtue of the existence of the amorphous silicon film, the temperature of the crystalline silicon film is increased uniformly, whereby the portion of the crystalline silicon film covered with the mask is also heated sufficiently and the catalyst element existing in this region moves to the phosphorus-implanted, amorphous portion having high gettering ability. As a result, the concentration of the catalyst element is reduced in the portion of the silicon film covered with the mask. A semiconductor device is manufactured by using this portion.Type: ApplicationFiled: March 1, 2007Publication date: July 12, 2007Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shunpei Yamazaki, Hisashi Ohtani
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Publication number: 20070155139Abstract: Integrated circuit device comprising a conductive layer and a poly-crystalline silicon layer, wherein the integrated circuit device further comprises an intermediate counter-stress layer. This intermediate counter-stress layer is arranged between the poly-crystalline silicon layer and the conductive layer, and enables stress-reduced crystallization of the poly-crystalline silicon layer. Further, the intermediate counter-stress layer is amorphous at and below a poly-silicon crystallization temperature.Type: ApplicationFiled: December 29, 2005Publication date: July 5, 2007Applicant: INFINEON TECHNOLOGIES AGInventors: Thomas Hecht, Henry Bernhardt, Christian Kapteyn
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Patent number: 7227186Abstract: An amorphous silicon film is laser irradiated a plural number of times to make the film composed of a plurality of crystal grains while suppressing the formation of protrusions at the boundaries of the adjoining grains to realize a polycrystalline silicon thin film transistor having at least partly therein the clusters of grains, or the aggregates of at least two crystal grains, with preferred orientation in the plane (111), and having high electron mobility of 200 cm2/Vs or above.Type: GrantFiled: May 4, 2005Date of Patent: June 5, 2007Assignee: Hitachi, Ltd.Inventors: Takuo Tamura, Kiyoshi Ogata, Yoichi Takahara, Kazuhiko Horikoshi, Hironaru Yamaguchi, Makoto Ohkura, Hironobu Abe, Masakazu Saitou, Yoshinobu Kimura, Toshihiko Itoga
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Patent number: 7223627Abstract: A method for controlling silver doping of a chalcogenide glass in a resistance variable memory element is disclosed herein. The method includes forming a thin metal containing layer having a thickness of less than about 250 Angstroms over a second chalcogenide glass layer, formed over a first metal containing layer, formed over a first chalcogenide glass layer. The thin metal containing layer preferably is a silver layer. An electrode may be formed over the thin silver layer. The electrode preferably does not contain silver.Type: GrantFiled: November 16, 2004Date of Patent: May 29, 2007Assignee: Micron Technology, Inc.Inventors: John T. Moore, Kristy A. Campbell, Terry L. Gilton
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Patent number: 7220660Abstract: Systems and methods for reducing a surface roughness of a polycrystalline or single crystal thin film produced by the sequential lateral solidification process are disclosed.Type: GrantFiled: September 13, 2004Date of Patent: May 22, 2007Assignee: The Trustees of Columbia University in the City of New YorkInventors: James S. Im, Robert S. Sposili, Mark A. Crowder
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Patent number: 7217642Abstract: A mask for forming polysilicon has a first slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while bearing the same width, a second slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while bearing the same width, a third slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while bearing the same width, and a fourth slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while bearing the same width. The slit patterns arranged at the first to fourth slit regions are sequentially enlarged in width in the horizontal direction in multiple proportion to the width d of the slit pattern at the first slit region. The centers of the slit patterns arranged at the first to fourth slit regions in the horizontal direction are placed at the same line.Type: GrantFiled: January 24, 2002Date of Patent: May 15, 2007Assignee: Samsung Electronis Co., Ltd.Inventors: Myung-Koo Kang, Hyun-Jae Kim, Sook-Young Kang
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Patent number: 7214592Abstract: Methods of forming semiconductor devices with a layered structure of thin and well defined layer of activated dopants, are disclosed. In a preferred method, a region in a semiconductor substrate is amorphized, after which the region is implanted with a first dopant at a first doping concentration. Then a solid phase epitaxy regrowth step is performed on a thin layer of desired thickness of the amorphized region, in order to activate the first dopant only in this thin layer. Subsequently, a second dopant is implanted in the remaining amorphous region at a second doping concentration. Subsequent annealing of the substrate activates the second dopant only in said remaining region, so a very abrupt transition between dopant characteristics of the thin layer with first dopant and the region with the second dopant is obtained.Type: GrantFiled: October 15, 2004Date of Patent: May 8, 2007Assignees: Interuniversitair Microelektronica Centrum (IMEC), Koninklijke Philips Electronics N.V.Inventor: Radu Catalin Surdeanu
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Publication number: 20070072324Abstract: A substrate including a host and a seed layer bonded to the host is provided, then a semiconductor structure including a light emitting layer disposed between an n-type region and a p-type region is grown on the seed layer. In some embodiments, a bonding layer bonds the host to the seed layer. The seed layer may be thinner than a critical thickness for relaxation of strain in the semiconductor structure, such that strain in the semiconductor structure is relieved by dislocations formed in the seed layer, or by gliding between the seed layer and the bonding layer an interface between the two layers. In some embodiments, the host may be separated from the semiconductor structure and seed layer by etching away the bonding layer.Type: ApplicationFiled: September 27, 2005Publication date: March 29, 2007Inventors: Michael Krames, Nathan Gardner, John Epler
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Patent number: 7186597Abstract: A mask is formed selectively on a crystalline silicon film containing a catalyst element, and an amorphous silicon film is formed so as to cover the mask. Phosphorus is implanted into the amorphous silicon film and the portion of the crystalline silicon film which is not covered with the mask. The silicon films are then heated by rapid thermal annealing (RTA). By virtue of the existence of the amorphous silicon film, the temperature of the crystalline silicon film is increased uniformly, whereby the portion of the crystalline silicon film covered with the mask is also heated sufficiently and the catalyst element existing in this region moves to the phosphorus-implanted, amorphous portion having high gettering ability. As a result, the concentration of the catalyst element is reduced in the portion of the silicon film covered with the mask. A semiconductor device is manufactured by using this portion.Type: GrantFiled: July 25, 2005Date of Patent: March 6, 2007Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hisashi Ohtani
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Publication number: 20070049021Abstract: The invention includes atomic layer deposition (ALD) methods for forming crystalline materials. The crystalline materials can have a first atomic arrangement within one layer, and a second atomic arrangement within another layer; with the first and second atomic arrangements having different crystallographic orientations relative to one another. Alternatively, or additionally, the crystalline materials can have a first portion with a first concentration of a particular element, and a second portion with a second concentration of the particular element which is different than the first concentration.Type: ApplicationFiled: August 31, 2005Publication date: March 1, 2007Inventors: Cem Basceri, Gurtej Sandhu
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Patent number: 7176049Abstract: A method of selectively heating a predetermined region of a semiconductor substrate includes providing a semiconductor substrate, selectively focusing a free carrier generation light on only a predetermined region of the semiconductor substrate, irradiating the free carrier generation light on the predetermined region of the semiconductor substrate to increase a free carrier concentration within the predetermined region of the semiconductor substrate, wherein the free carrier generation light causes the predetermined region to increase in temperature by less than a temperature necessary to change the solid phase of the predetermined region, and irradiating the semiconductor substrate with a heating light to selectively heat the predetermined region of the semiconductor substrate.Type: GrantFiled: May 14, 2004Date of Patent: February 13, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Gyoung Ho Buh, Ji-Sang Yahng, Yu Gyun Shin, Guk-Hyon Yon, Sangjin Hyun
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Patent number: 7142297Abstract: A method for determining the movement of particles, particularly impurities, in a medium, under the influence of a changing interface between two neighboring phases. In a first step, the temporal and/or local evolution of said interface is determined. In a second step, the movement of said particles in dependence of the temporal and/or local evolution of the phase interface as determined in the first step is calculated. Optionally, the distribution of the particles within the medium at a certain time is then determined.Type: GrantFiled: October 31, 2003Date of Patent: November 28, 2006Assignee: Synopsys Switzerland LLCInventor: Christoph Zechner
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Patent number: 7141491Abstract: Concentration of metal element which promotes crystallization of silicon and which exists within a crystalline silicon film obtained by utilizing the metal element is reduced. A first heat treatment for crystallization is performed after introducing nickel to an amorphous silicon film 103. Then, laser light is irradiated to diffuse nickel element which is concentrated locally. After that, another heat treatment is performed within an oxidizing atmosphere at a temperature higher than that of the previous heat treatment. At this time, HCl or the like is added to the atmosphere. A thermal oxide film 106 is formed in this step. At this time, gettering of the nickel element into the thermal oxide film 106 takes place. Then, the thermal oxide film 106 is removed. Thereby, a crystalline silicon film 107 having low concentration of the metal element and a high crystallinity can be obtained.Type: GrantFiled: December 19, 2005Date of Patent: November 28, 2006Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Satoshi Teramoto, Jun Koyama, Yasushi Ogata, Masahiko Hayakawa, Mitsuaki Osame
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Patent number: 7129522Abstract: Protrusions called ridges are formed on the surface of a crystalline semiconductor film formed by a laser crystallization method or the like. A heat absorbing layer are formed below a semiconductor film. When the semiconductor film is crystallized by laser, a temperature difference is produced between a semiconductor film 1010 positioned above a heat absorbing layer 1011 and a semiconductor film 1013 of the other region to produce a difference in thermal expansion at the boundary of the outside end 1015 of the heat absorbing layer. This difference produces a strain to form a surface wave. The surface wave starting at the outer periphery of the heat absorbing layer is formed in the vicinity of the heat absorbing layer. When the semiconductor layer is solidified after it is melted, the protrusions of the surface wave remain as protrusions after the semiconductor film is solidified.Type: GrantFiled: December 18, 2003Date of Patent: October 31, 2006Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Setsuo Nakajima, Ritsuko Kawasaki
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Patent number: 7112516Abstract: One aspect of the invention relates to a method of forming P-N junctions within a semiconductor substrate. The method involves providing a temporary impurity species, such as fluorine, within the semiconductor crystal matrix prior to solid source in-diffusion of the primary dopant, such as boron. The impurity atom is a faster diffusing species relative to silicon atoms. During in-diffusion, the temporary impurity species acts to reduce the depth to which the primary dopant diffuses and thereby facilitates the formation of very shallow junctions.Type: GrantFiled: October 2, 2003Date of Patent: September 26, 2006Assignee: Texas Instruments IncorporatedInventors: Srinivasan Chakravarthi, Periannan Chidambaram
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Patent number: 7084081Abstract: A display device includes a display area composed of pixels in a matrix. Each pixel has a light-emitting element and a driving element to supply a driving current to the light-emitting element. The driving element includes a thin film transistor with a semiconductor layer of a poly-crystalline film. The semiconductor layer is provided with channel region, and a source and drain region disposed on both sides of the channel region. The channel region connects the source region to the drain region and has at least two conductive regions with different average grain sizes. The characteristics of the driving elements are made substantially uniform so that the display quality of the display device can be improved remarkably.Type: GrantFiled: November 26, 2004Date of Patent: August 1, 2006Assignee: Toshiba Matsushita Display Technology Co., Ltd.Inventor: Yasumasa Goto
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Publication number: 20040113287Abstract: A semiconductor device manufacturing unit is provided, wherein a cathode and an anode can be placed in a simple structure; wherein excellent film deposition and film thickness distribution can be gained; and wherein no cooling devices are required to be provided.Type: ApplicationFiled: November 10, 2003Publication date: June 17, 2004Inventors: Katsushi Kishimoto, Yusuke Fukuoka, Yasushi Fujioka, Hiroyuki Fukuda, Katsuhiko Nomoto