Abstract: There is provided a method and apparatus for forming a layer, by sequentially repeating a layer deposition cycle to process a substrate disposed in a reaction chamber. The deposition cycle comprising: supplying a first precursor into the reaction chamber for a first pulse period; supplying a second precursor into the reaction chamber for a second pulse period. At least one of the first and second precursors may be supplied into the reaction chamber for a pretreatment period longer than the first or second pulse period before sequentially repeating the deposition cycles.

Abstract: The present disclosure provides a method of fabricating a semiconductor structure in accordance with some embodiments. The method includes receiving a substrate having an active region and an isolation region; forming gate stacks on the substrate and extending from the active region to the isolation region; forming an inner gate spacer and an outer gate spacer on sidewalls of the gate stacks; forming an interlevel dielectric (ILD) layer on the substrate; removing the outer gate spacer in the isolation region, resulting in an air gap between the inner gate spacer and the ILD layer; and performing an ion implantation process to the ILD layer, thereby expanding the ILD layer to cap the air gap.

Abstract: A method of manufacturing a semiconductor device includes: forming a gate over a semiconductor substrate; forming doped regions in the semiconductor substrate on both sides of the gate; depositing a dielectric layer on sidewalls of the gate; depositing a spacer laterally surrounding the dielectric layer, the spacer including a carbon-free portion and a carbon-containing portion laterally surrounding the carbon-free portion; removing the gate and vertical portions of the dielectric layer to form a recess; and filling a conductive layer in the recess.

Abstract: The present disclosure provides a method of fabricating a semiconductor structure in accordance with some embodiments. The method includes receiving a substrate having an active region and an isolation region; forming gate stacks on the substrate and extending from the active region to the isolation region; forming an inner gate spacer and an outer gate spacer on sidewalls of the gate stacks; forming an interlevel dielectric (ILD) layer on the substrate; removing the outer gate spacer in the isolation region, resulting in an air gap between the inner gate spacer and the ILD layer; and performing an ion implantation process to the ILD layer, thereby expanding the ILD layer to cap the air gap.

Abstract: Structures for a field-effect transistor and methods for fabricating a structure for a field-effect transistor. A first epitaxial layer has a first surface and a second surface inclined relative to the first surface. A surface layer is arranged on the first and second surfaces of the first epitaxial layer. A second epitaxial layer is arranged over the surface layer on the first and second surfaces of the first epitaxial layer. A portion of the first epitaxial layer defines an interface with the surface layer. The portion of the first epitaxial layer contains a first concentration of a dopant. The surface layer contains a second concentration of the dopant that is greater than the first concentration of the dopant in the portion of the first epitaxial layer.

Abstract: A field-programmable-gate-array (FPGA) IC chip includes multiple first non-volatile memory cells in the FPGA IC chip, wherein the first non-volatile memory cells are configured to save multiple resulting values for a look-up table (LUT) of a programmable logic block of the FPGA IC chip, wherein the programmable logic block is configured to select, in accordance with its inputs, one from the resulting values into its output; and multiple second non-volatile memory cells in the FPGA IC chip, wherein the second non-volatile memory cells are configured to save multiple programming codes configured to control a switch of the FPGA IC chip.

Abstract: An embodiment of a method for forming a transistor that includes providing a semiconductor substrate having a source/drain region is provided where a first SiGe layer is formed over the source/drain region. A thermal oxidation is performed to convert a top portion of the first SiGe layer to an oxide layer and a bottom portion of the first SiGe layer to a second SiGe layer. A thermal diffusion process is performed after the thermal oxidation is performed to form a SiGe area from the second SiGe layer. The SiGe area has a higher Ge concentration than the first SiGe layer.

Abstract: A field-programmable-gate-array (FPGA) IC chip includes multiple first non-volatile memory cells in the FPGA IC chip, wherein the first non-volatile memory cells are configured to save multiple resulting values for a look-up table (LUT) of a programmable logic block of the FPGA IC chip, wherein the programmable logic block is configured to select, in accordance with its inputs, one from the resulting values into its output; and multiple second non-volatile memory cells in the FPGA IC chip, wherein the second non-volatile memory cells are configured to save multiple programming codes configured to control a switch of the FPGA IC chip.

Abstract: A method of fabricating air gap spacers is provided. The method includes forming gate structures to extend upwardly from a substrate with source or drain (S/D) regions disposed between the gate structures and with contact trenches defined above the S/D regions and between the gate structures. The method further includes disposing contacts in the contact trenches. The method also includes configuring the contacts to define open-ended air gap spacer trenches with the gate structures. In addition, the method includes forming a cap over the open-ended air gap spacer trenches to define the open-ended air gap spacer trenches as air gap spacers. The gate structures have an initial structure prior to and following the disposing and the configuring of the contacts and prior to and following the forming of the cap.

Abstract: Structures for a field-effect transistor and methods for forming a field-effect transistor. The structure includes a gate structure having a sidewall and a sidewall spacer arranged adjacent to the sidewall of the gate structure. The sidewall spacer includes an energy removal film material and one or more air gaps in the energy removal film material.

Abstract: Embodiments of the disclosure relate to deposition of a conformal carbon-based material. In one embodiment, the method comprises depositing a sacrificial dielectric layer over a substrate, forming patterned features on the substrate by removing portions of the sacrificial dielectric layer to expose an upper surface of the substrate, introducing a hydrocarbon source, a plasma-initiating gas, and a dilution gas into the processing chamber, generating a plasma in the processing chamber at a deposition temperature of about 80° C. to about 550° C. to deposit a conformal amorphous carbon layer on the patterned features and the exposed upper surface of the substrate, selectively removing the amorphous carbon layer from an upper surface of the patterned features and the upper surface of the substrate using an anisotropic etching process to provide the patterned features filled within sidewall spacers, and removing the patterned features formed from the sacrificial dielectric layer.

Abstract: A semiconductor device that includes a gate structure on a channel region of a semiconductor device. Source and drain regions may be present on opposing sides of the channel region. The semiconductor device may further include a composite gate sidewall spacer present on a sidewall of the gate structure. The composite gate sidewall spacer may include a first composition portion having an air gap encapsulated therein, and a second composition portion that is entirely solid and present atop the first composition portion.

Abstract: A method of processing quantum dots is disclosed. The method comprises applying energy to excite the quantum dots to emit light and placing the quantum dots under vacuum after excitation of the quantum dots. Also disclosed is a method of processing a component including quantum dots comprising applying energy to the component including quantum dots to excite the quantum dots to emit light; and placing the component including quantum dots under vacuum after excitation. A method for processing a device is further disclosed, the method comprising applying energy to the device to excite the quantum dots to emit light; and placing the device under vacuum after excitation of the quantum dots. A method for preparing a device is also disclosed. Quantum dots, component, and devices of the methods are also disclosed.

Abstract: Embodiments of the invention relate to deposition of a conformal carbon-based material. In one embodiment, the method comprises depositing a sacrificial dielectric layer with a predetermined thickness over a substrate, forming patterned features on the substrate by removing portions of the sacrificial dielectric layer to expose an upper surface of the substrate, introducing a hydrocarbon source, a plasma-initiating gas, and a dilution gas into the processing chamber, wherein a volumetric flow rate of hydrocarbon source:plasma-initiating gas:dilution gas is in a ratio of 1:0.5:20, generating a plasma at a deposition temperature of about 300 C to about 500 C to deposit a conformal amorphous carbon layer on the patterned features and the exposed upper surface of the substrate, selectively removing the amorphous carbon layer from an upper surface of the patterned features and the upper surface of the substrate, and removing the patterned features.

Abstract: A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A plurality of gate formation layers is formed on an etch stop layer disposed on the fin. The plurality of gate formation layers include a dummy gate layer formed from a dielectric material. The plurality of gate formation layers is patterned to form a plurality of dummy gate elements on the etch stop layer. Each dummy gate element is formed from the dielectric material. A spacer layer formed on the dummy gate elements is etched to form a spacer on each sidewall of dummy gate elements. A portion of the etch stop layer located between each dummy gate element is etched to expose a portion the semiconductor fin. A semiconductor material is epitaxially grown from the exposed portion of the semiconductor fin to form source/drain regions.

Abstract: A semiconductor device and method of manufacturing the same are provided in the present invention. Multiple spacer layers are used in the invention to form spacers with different predetermined thickness on different active regions or devices, thus the spacing between the strained silicon structure and the gate structure (SiGe-to-Gate) can be properly controlled and adjusted to achieve better and more uniform performance for various devices and circuit layouts.

Abstract: A semiconductor structure includes a substrate, a source/drain (S/D) junction, and an S/D contact. The S/D junction is associated with the substrate and includes a trench-defining wall, a semiconductor layer, and a semiconductor material. The trench-defining wall defines a trench. The semiconductor layer is formed over the trench-defining wall, partially fills the trench, substantially covers the trench-defining wall, and includes germanium. The semiconductor material is formed over the semiconductor layer and includes germanium, a percentage composition of which is greater than a percentage composition of the germanium of the semiconductor layer. The S/D contact is formed over the S/D junction.

Abstract: Various embodiments provide for a method for roughening a surface of a MEMs device or the surface of a CMOS surface. A first material can be deposited in a thin layer over a surface made of a second material. After heating, the first and second materials, they can partially melt and interdiffuse, forming an alloy. The first material can then be removed and the alloy is removed at the same time. The surface of the second material that is left behind has then been roughened due to the interdiffusion of the first and second materials.

Abstract: An integrated circuit is described as having one or more contact regions to provide one or more interconnections between one or more transistors of the integrated circuit and another integrated circuit. The one or more contact regions represent a self-aligned contact (SAC) whose positioning is determined through one or more patterning processes of a semiconductor fabrication process. The one or more contact regions include one or more contact discontinuities to allow the integrated circuit to accommodate for a wide range of the manufacturing variations and/or the misalignment tolerances by preventing the one or more contact regions from physically contacting other regions, such as gate regions to provide an example, of the one or more transistors. As such, the one or more contact discontinuities have a dynamic size, such as a dynamic area to provide an example, which is dependent upon the manufacturing variations and/or the misalignment tolerances.

Abstract: Solar cell structures and formation methods which utilize the surface texture in conjunction with a passivating dielectric layer to provide a practical and controllable technique of forming an electrical contact between a conducting layer and underlying substrate through the passivating dielectric layer, achieving both good surface passivation and electrical contact with low recombination losses, as required for high efficiency solar cells. The passivating dielectric layer is intentionally modified to allow direct contact, or tunnel barrier contact, with the substrate. Additional P-N junctions, and dopant gradients, are disclosed to further limit losses and increase efficiency.

Abstract: A semiconductor structure includes a substrate and a source/drain (S/D) junction. The S/D junction is associated with the substrate and includes a semiconductor material. The semiconductor material includes germanium and has a percentage composition of the germanium between about 50% and about 95%.

Abstract: A vertical transistor has a first air-gap spacer between the gate and the bottom source/drain, and a second air-gap spacer between the gate and the contact to the bottom source/drain. A dielectric layer disposed between the gate and the contact to the top source/drain decreases parasitic capacitance and inhibits electrical shorting.

Abstract: A semiconductor device includes a gate positioned on a substrate; a nanosheet that extends through the gate, protrudes from a sidewall of the gate, and forms a recess between the substrate and the nanosheet; a dielectric spacer disposed in the recess; a source/drain contact positioned on a source/drain disposed on the substrate adjacent to the gate; an air gap spacer positioned along the sidewall of the gate and in contact with a dielectric material disposed on the nanosheet, the air gap spacer being in contact with the source/drain contact; and an interlayer dielectric (ILD) disposed on the air gap spacer.

Abstract: Disclosed herein is a fabrication method of a semiconductor device to order to increase an operation liability of the semiconductor device. A method for fabricating a semiconductor device comprises forming a recess in a semiconductor substrate, forming a word line in a lower part of the recess, oxidizing a top portion of the word line, and depositing an insulating material in a remained part of the recess.

Abstract: An exemplary method is disclosed for manufacturing a power semiconductor device which has a first electrical contact on a first main side and a second electrical contact on a second main side opposite the first main side and at least a two-layer structure with layers of different conductivity types, and includes providing an n-doped wafer and creating a surface layer of palladium particles on the first main side. The wafer is irradiated on the first main side with ions. Afterwards, the palladium particles are diffused into the wafer at a temperature of not more than 750° C., by which diffusion a first p-doped layer is created. Then, the first and second electrical contacts are created. At least the irradiation with ions is performed through a mask.

Abstract: An improved method of implanting a solar cell is disclosed. A substrate is coated with a soft mask material. A shadow mask is used to perform a pattern ion implant and to set the soft mask material. After the soft mask material is set, the mask is removed and a blanket implant is performed.

Abstract: In transistors requiring a high compressive strain, the germanium contents may be increased by applying a germanium condensation technique. In some illustrative embodiments, an oxidation process is performed in the presence of a silicon/germanium material obtained on the basis of selective epitaxial growth techniques, thereby increasingly oxidizing the silicon species, while driving the germanium into the lower lying areas of the active region, which finally results in an increased germanium concentration.

Abstract: A method of manufacturing a semiconductor device includes forming silicon line patterns in a semiconductor substrate, forming an insulating layer over the silicon line patterns, forming a conductive pattern between the silicon line patterns, forming a spacer over the substrate, forming an interlayer insulating layer between the silicon line patterns, removing the spacer on one side of the silicon line patterns to expose the conductive pattern, forming a bit line contact open region by removing the interlayer insulating layer, forming a polysilicon pattern to cover the bit line contact open region, and forming a junction region diffused to the silicon line pattern through the bit line contact open region. Thereby, a stacked structure of a titanium layer and a polysilicon layer are stably formed when forming a buried bit line and a bit line contact is formed using diffusion of the polysilicon layer to prevent leakage current.

Abstract: Provided is a method that can include forming a gate dielectric layer, a first diffusion layer, and a hard mask layer on a substrate defined to include first and second spaced apart regions, forming a photoresist pattern on the hard mask layer in the first region and exposing the hard mask layer on the second region, removing the exposed hard mask layer on the second region and the first diffusion layer on the second region to expose the gate dielectric layer on the second region, removing the photoresist pattern, forming a second diffusion layer on uppermost surfaces of the first and second regions, and performing a heat treatment process to diffuse a first diffusion material included in the first diffusion layer and a second diffusion material included in the second diffusion layer.

Abstract: Disclosed herein is a fabrication method of a semiconductor device to order to increase an operation liability of the semiconductor device. A method for fabricating a semiconductor device comprises forming a recess in a semiconductor substrate, forming a word line in a lower part of the recess, oxidizing a top portion of the word line, and depositing an insulating material in a remained part of the recess.

Abstract: A method for growing a nitride semiconductor has a first step for forming a surface reformation layer on a sapphire substrate, a second step for raising a temperature of the sapphire substrate with the surface reformation layer formed thereon up to a growth temperature of the nitride semiconductor in an atmosphere including ammonia, and a third step for growing a nitride semiconductor layer on a surface of the surface reformation layer. Alternatively, the second step is conducted in an atmosphere including an inert gas, or an atmosphere including the inert gas and hydrogen at a concentration of 10% or less relative to the inert gas.

Abstract: Methods for producing a semiconductor device are provided. In one embodiment, a method includes the steps of: (i) fabricating a partially-completed semiconductor device including a substrate, a source/drain region in the substrate, a gate stack overlaying the substrate, and a sidewall spacer adjacent the gate stack; (ii) utilizing an anisotropic etch to remove an upper portion of the sidewall spacer while leaving intact a lower portion of the sidewall spacer overlaying the substrate; (iii) implanting ions in the source/drain region; and (iv) annealing the semiconductor device to activate the implanted ions. The step of annealing is performed with the lower portion of the sidewall spacer intact to deter the ingress of oxygen into the substrate and minimize under-oxide regrowth proximate the gate stack.

Abstract: A method for fabricating a three-dimensional photonic crystal comprises the steps of: forming a dielectric thin film; injecting ions selectively into the dielectric thin film by using a focus ion beam to form a mask on the dielectric thin film; forming a pattern by selectively removing an exposed part of the dielectric thin film at which the mask is not formed on the dielectric thin film; forming a sacrificial layer on the dielectric thin film having the pattern formed therein; and flattening the sacrificial layer formed on the dielectric thin film until the pattern comes to the surface.

Abstract: An electronic device, including a substrate, a plurality of first semiconductor islands on the substrate, a plurality of second semiconductor islands on the substrate, a first dielectric film on the first subset of the semiconductor islands, second dielectric film on the second semiconductor islands, and a metal layer in electrical contact with the first and second semiconductor islands. The first semiconductor islands and the first dielectric film contain a first diffusible dopant, and the second semiconductor islands and the second dielectric layer film contain a second diffusible dopant different from the first diffusible dopant. The present electronic device can be manufactured using printing technologies, thereby enabling high-throughput, low-cost manufacturing of electrical circuits on a wide variety of substrates.

Abstract: A semiconductor device having high electrical characteristics is manufactured at low cost and with high throughput. A semiconductor film is crystallized or activated by being irradiated with a laser beam emitted from one fiber laser. Alternatively, laser beams are emitted from a plurality of fiber lasers and coupled by a coupler to be one laser beam, and then a semiconductor film is irradiated with the coupled laser beam so as to be crystallized or activated.

Abstract: A sidewall spacer structure is formed adjacent to a gate structure whereby a material forming an outer surface of the sidewall spacer structure contains nitrogen. Subsequent to its formation the sidewall spacer structure is annealed to harden the sidewall spacer structure from a subsequent cleaning process. An epitaxial layer is formed subsequent to the cleaning process.

Abstract: The present invention provides a semiconductor device having dual nitride liners, a silicide layer, and a protective layer beneath one of the nitride liners for preventing the etching of the silicide layer. A first aspect of the invention provides a semiconductor device comprising a protective layer adjacent a first device, a first silicon nitride liner over the protective layer, a second silicon nitride liner adjacent a second device, and a first silicide layer adjacent the first device and a second silicide layer adjacent the second device, wherein a thickness is substantially the same in the first and second silicide layers.

Abstract: A solution containing impurity ions is applied onto the surface of a silicon film to form a solution layer, followed by drying into a compound layer containing the impurities. Heat treatment is performed by irradiation with an energy beam so as to diffuse the impurity atoms in the compound layer toward the silicon film into a source region and a drain region. Subsequently, the compound layer is removed.

Abstract: Highly uniform silica nanoparticles can be formed into stable dispersions with a desirable small secondary particle size. The silican particles can be surface modified to form the dispersions. The silica nanoparticles can be doped to change the particle properties and/or to provide dopant for subsequent transfer to other materials. The dispersions can be printed as an ink for appropriate applications. The dispersions can be used to selectively dope semiconductor materials such as for the formation of photovoltaic cells or for the formation of printed electronic circuits.

Abstract: Disclosed is a method for fabricating a transistor of a semiconductor device, the method comprising the steps of: providing a semiconductor; forming a gate electrode; performing a low-density ion implantation process with respect to the substrate, thereby forming an LDD ion implantation layer; forming an insulation spacer on a sidewall of the gate electrode; forming a diffusion barrier; performing a high-density ion implantation process with respect to the substrate, thereby forming a source/drain; performing a first thermal treatment process with respect to a resultant structure, so as to activate impurities in the source/drain, and simultaneously causing a diffusion velocity of the impurities in the source/drain to be reduced by the diffusion barrier; and forming a salicide layer.