Abstract: A nitride-based semiconductor device of the present invention includes: a nitride-based semiconductor multilayer structure 20 which includes a p-type semiconductor region with a surface 12 being inclined from the m-plane by an angle of not less than 1° and not more than 5°; and an electrode 30 provided on the p-type semiconductor region. The p-type semiconductor region is formed by an AlxInyGazN (where x+y+z=1, x?0, y?0, and z?0) layer 26. The electrode 30 includes a Mg layer 32 and an Ag layer 34 provided on the Mg layer 32. The Mg layer 32 is in contact with the surface 12 of the p-type semiconductor region of the semiconductor multilayer structure 20.

Abstract: A method of fabricating a semiconductor device includes forming a bottom electrode material layer containing aluminum and copper over the substrate. An insulating material layer and a top electrode material layer are sequentially formed on the surface of the bottom electrode material layer. A photoresist pattern is formed on the top electrode material layer, and then the top electrode material layer is patterned to form a top electrode by using the photoresist pattern as mask. The photoresist pattern is removed by plasma ash and then an alloy process is performed to the bottom electrode material layer. Thereafter, the insulating material layer, and the bottom electrode material layer are patterned to form a patterned insulating layer and a patterned bottom electrode layer.

Abstract: An improvement is achieved in the manufacturing yield of a semiconductor device including a plurality of field effect transistors having different characteristics over the same substrate. By combining anisotropic dry etching with isotropic wet etching or isotropic dry etching, three types of sidewalls having different sidewall lengths are formed. By reducing the number of anisotropic dry etching steps, in a third n-type MISFET region and a third p-type MISFET region where layout densities are high, it is possible to prevent a semiconductor substrate from being partially cut between n-type gate electrodes adjacent to each other, between the n-type gate electrode and a p-type gate electrode adjacent to each other, and the p-type gate electrodes adjacent to each other.

Abstract: A method of forming a doped region in a semiconductor layer of a substrate by alloying with doping elements is disclosed. In one aspect, the method includes screen printing a paste layer of doping element paste to the substrate and firing the screen printed paste layer of doping element paste, wherein a highly pure doping element layer is applied to the semiconductor layer after which the paste layer is screen printed to the doping element layer.

Abstract: This invention provides methods that permit wafers to be loaded and unloaded in a gas-phase epitaxial growth chamber at high temperatures. Specifically, this invention provides a method for moving wafers or substrates that can bathe a substrate being moved in active gases that are optionally temperature controlled. The active gases can act to limit or prevent sublimation or decomposition of the wafer surface, and can be temperature controlled to limit or prevent thermal damage. Thereby, previously-necessary temperature ramping of growth chambers can be reduced or eliminated leading to improvement in wafer throughput and system efficiency.

Abstract: A semiconductor device manufacturing method includes, forming isolation region having an aspect ratio of 1 or more in a semiconductor substrate, forming a gate insulating film, forming a silicon gate electrode and a silicon resistive element, forming side wall spacers on the gate electrode, heavily doping a first active region with phosphorus and a second active region and the resistive element with p-type impurities by ion implantation, forming salicide block at 500° C. or lower, depositing a metal layer covering the salicide block, and selectively forming metal silicide layers. The method may further includes, forming a thick and a thin gate insulating films, and performing implantation of ions of a first conductivity type not penetrating the thick gate insulating film and oblique implantation of ions of the opposite conductivity type penetrating also the thick gate insulating film before the formation of side wall spacers.

Abstract: This invention provides apparatus, protocols, and methods that permit wafers to be loaded and unloaded in a gas-phase epitaxial growth chamber at high temperatures. Specifically, this invention provides a device for moving wafers or substrates that can bath a substrate being moved in active gases that are optionally temperature controlled. The active gases can act to limit or prevent sublimation or decomposition of the wafer surface, and can be temperature controlled to limit or prevent thermal damage. Thereby, previously-necessary temperature ramping of growth chambers can be reduced or eliminated leading to improvement in wafer throughput and system efficiency.

Abstract: A method of fabricating a semiconductor device is provided. The method includes forming a bottom electrode material layer containing aluminum and cupper over the substrate. An insulating material layer and a top electrode material layer are sequentially formed on the surface of the bottom electrode material layer. A photoresist pattern is formed on the top electrode material layer, and then the top electrode material layer is patterned to form a top electrode by using the photoresist pattern as mask. The photoresist pattern is removed by plasma ash and then an alloy process is performed to the bottom electrode material layer. Thereafter, the insulating material layer, and the bottom electrode material layer are patterned to form a patterned insulating layer and a patterned bottom electrode layer.

Abstract: A method of forming a doped region in a semiconductor layer of a substrate by alloying with doping elements is disclosed. In one aspect, the method includes screen printing a paste layer of doping element paste to the substrate and firing the screen printed paste layer of doping element paste, wherein a highly pure doping element layer is applied to the semiconductor layer after which the paste layer is screen printed to the doping element layer.

Abstract: A method of manufacturing a semiconductor device, includes the steps of forming an insulating film on a semiconductor substrate having a silicide layer, forming a hole in the insulating film on the silicide layer, cleaning an inside of the hole and a surface of the silicide layer, forming a titanium layer on a bottom surface and an inner peripheral surface of the hole by a CVD method, forming a copper diffusion preventing barrier metal layer on the titanium layer in the hole, and burying a copper layer in the hole.

Abstract: A method for forming a thin film photovoltaic device. The method includes providing a transparent substrate comprising a surface region. The method forms a first electrode layer overlying the surface region of the transparent substrate. The method also forms a thin layer of indium material, using a sputtering target of indium material, overlying the first electrode layer to act as an intermediary glue layer to facilitate attachment to the first electrode layer. In a specific embodiment, the method forms a copper material overlying the thin layer of indium material. The method also forms an indium layer overlying the copper material to form a multi layered structure including at least the thin layer of indium material, copper material, and the indium layer. In a preferred embodiment, the multi-layered structure has a first thickness.

Abstract: A thin film panel includes a substrate, a gate line formed on the substrate, a gate insulating layer formed on the gate line, a semiconductor layer formed on the gate insulating layer, a data line, including a source electrode, and a drain electrode formed on the gate insulating layer or the semiconductor layer, and a pixel electrode connected to the drain electrode, wherein at least one of the gate line and the data line and drain electrode includes a first conductive layer made of a molybdenum Mo-niobium Nb alloy and a second conductive layer made of a copper Cu-containing metal.

Abstract: A semiconductor device includes: an n-transistor including a first gate insulating film made of a high-dielectric-constant material and a first gate electrode fully silicided with a metal, the first gate insulating film and the first gate electrode being formed in this order over a semiconductor region; and a p-transistor including a second gate insulating film made of the high-dielectric-constant material and a second gate electrode fully silicided with the metal, the second gate insulating film and the second gate electrode being formed in this order over the semiconductor region. If the metal has a work function larger than a Fermi level in potential energy of electrons of silicon, a metal concentration of the second gate electrode is higher than that of the first gate electrode whereas if the metal has a work function smaller than the Fermi level of silicon, a metal concentration of the second gate electrode is lower than that of the first gate electrode.

Abstract: To provide a Ga2O3 compound semiconductor device in which a Ga2O3 system compound is used as a semiconductor, which has an electrode having ohmic characteristics adapted to the Ga2O3 system compound, and which can make a heat treatment for obtaining the ohmic characteristics unnecessary. An n-side electrode 20 including at least a Ti layer is formed on a lower surface of an n-type ?-Ga2O3 substrate 2 by utilizing a PLD method. This n-side electrode 20 has ohmic characteristics at 25° C. The n-side electrode 20 may have two layer including a Ti layer and an Au layer, three layers including a Ti layer, an Al layer and an Au layer, or four layers including a Ti layer, an Al layer, a Ni layer and an Au layer.

Abstract: A semiconductor device manufacturing method includes, forming isolation region having an aspect ratio of 1 or more in a semiconductor substrate, forming a gate insulating film, forming a silicon gate electrode and a silicon resistive element, forming side wall spacers on the gate electrode, heavily doping a first active region with phosphorus and a second active region and the resistive element with p-type impurities by ion implantation, forming salicide block at 500° C. or lower, depositing a metal layer covering the salicide block, and selectively forming metal silicide layers. The method may further includes, forming a thick and a thin gate insulating films, and performing implantation of ions of a first conductivity type not penetrating the thick gate insulating film and oblique implantation of ions of the opposite conductivity type penetrating also the thick gate insulating film before the formation of side wall spacers.

Abstract: There are provided an ohmic electrode, which includes a contact layer made of an Al alloy and formed on a nitride-based semiconductor layer functioning as a light emitting layer, a reflective layer made of Ag metal, formed on the contact layer and having some particles in-diffused to the semiconductor layer, and a protective layer formed on the reflective layer to restrain out-diffusion of the reflective layer; a method of forming the ohmic electrode; and a semiconductor light emitting element having the ohmic electrode. The present invention has strong adhesive strength and low contact resistance since the reflective layer and the light emitting layer directly form an ohmic contact due to the interface reaction during heat treatment, and the present invention has high light reflectance and excellent thermal stability since the contact layer and the protective layer restrain out-diffusion of the reflective layer during heat treatment.

Abstract: The invention relates to a method of fabricating a CMOS device, comprising providing a semiconductor substrate (101) having therein a layer of insulating material (102), the method comprising providing a layer (106) of a first material over the insulating layer (102), the thickness of the layer (106) of the first material being less in a first region (103) for supporting a first active device than in a second region (104) for supporting a second active device. A layer (107) of a second material is then deposited over the layer (106) of a first material, and the structure is then subjected to a thermal treatment to alloy the first and second materials. The portion of the layers over the first region is entirely alloyed, whereas the portion of the layers over the second region is not, so that a portion (109) of the layer (106) of the first material remains.

Abstract: The present invention relates to methods for producing anode materials for use in nonaqueous electrolyte secondary batteries. In the present invention, a metal-semiconductor alloy layer is formed on an anode material by contacting a portion of the anode material with a solution containing metals ions and a dissolution component. When the anode material is contacted with the solution, the dissolution component dissolves a part of the semiconductor material in the anode material and deposit the metal on the anode material. After deposition, the anode material and metal are annealed to form a uniform metal-semiconductor alloy layer. The anode material of the present invention can be in a monolithic form or a particle form. When the anode material is in a particle form, the particulate anode material can be further shaped and sintered to agglomerate the particulate anode material.

Abstract: An integration scheme that enables full silicidation (FUSI) of the nFET and pFET gate electrodes at the same time as that of the source/drain regions is provided. The FUSI of the gate electrodes eliminates the gate depletion problem that is observed with polysilicon gate electrodes. In addition, the inventive integration scheme creates different silicon thicknesses of the gate electrode just prior to silicidation. This feature of the present invention allows for fabricating nFETs and pFETs that have a band edge workfunction that is tailored for the specific device region.