Abstract: The invention includes methods of forming and/or passivating semiconductor constructions. In particular aspects, various oxides of a semiconductor substrate can be formed by exposing semiconductive material of the substrate to deuterium-enriched steam. In other aspects, a semiconductor construction is passivated by subjecting the construction to an anneal at a temperature of greater than or equal to 350° C. while exposing the construction to a deuterium-enriched ambient.

Abstract: There is provided a method of removing trap levels and defects, which are caused by stress, from a single crystal silicon thin film formed by an SOI technique. First, a single crystal silicon film is formed by using a typical bonding SOI technique such as Smart-Cut or ELTRAN. Next, the single crystal silicon thin film is patterned to form an island-like silicon layer, and then, a thermal oxidation treatment is carried out in an oxidizing atmosphere containing a halogen element, so that an island-like silicon layer in which the trap levels and the defects are removed is obtained.

Abstract: A high quality bonded substrate is obtained in which generation of microprotrusions and cracked particles are restricted on a surface of an active layer of the bonded substrate and the surface of the active layer is flattened. A laminated body is formed by overlapping a first semiconductor substrate serving as an active layer onto a second semiconductor substrate serving as a support substrate via an oxide film or without an oxide film; the active layer is formed by forming a thin film from the first semiconductor substrate; and the surface of the active layer is flattened by vapor-phase etching. After forming a thin film from the first semiconductor substrate and before flattening the surface of the active layer by the vapor-phase etching, an organic substance adhering to the surface of the active layer is removed and a native oxide film generated on the surface of the active layer is removed after removing the organic substance.

Abstract: A doping method comprising the steps of; obtaining a proportion X of ions of a compound including a donor or an acceptor impurity in total ions from mass spectrum by using a first source gas of a first concentration; analyzing a peak concentration Y of the compound in a first processing object which is doped by using a second source gas of a second concentration equal to or lower than the first concentration, referring to a dose amount of total ions as D0 and setting an acceleration voltage at a value, obtaining a dose amount D1 of total ions from a expression, Y=(D1/D0)(aX+b), and doping a second processing object with the donor or the acceptor impurity by a ion doping apparatus using a third source gas, wherein a dose amount of total ions is set at D1, and an acceleration voltage is set at the value.

Abstract: A peeling method is provided which does not cause damage to a layer to be peeled, and the method enables not only peeling of the layer to be peeled having a small area but also peeling of the entire layer to be peeled having a large area at a high yield. Further, there are provided a semiconductor device, which is reduced in weight through adhesion of the layer to be peeled to various base materials, and a manufacturing method thereof. In particular, there are provided a semiconductor device, which is reduced in weight through adhesion of various elements, typically a TFT, to a flexible film, and a manufacturing method thereof. A metal layer or nitride layer is provided on a substrate; an oxide layer is provided contacting with the metal layer or nitride layer; then, a base insulating film and a layer to be peeled containing hydrogen are formed; and heat treatment for diffusing hydrogen is performed thereto at 410° C. or more.

Abstract: Provided is an organic light emitting display, in which a semiconductor circuit unit of 2T-1C structure including a switching transistor and a driving transistor formed of single crystalline silicon is formed on a plastic substrate. A method of fabricating the single crystalline silicon includes: growing a single crystalline silicon layer to a predetermined thickness on a crystal growth plate; depositing a buffer layer on the single crystalline silicon layer; forming a partition layer at a predetermined depth in the single crystalline silicon layer by, e.g., implanting hydrogen ions in the single crystalline silicon layer from an upper portion of an insulating layer; attaching a substrate to the buffer layer; and releasing the partition layer of the single crystalline silicon layer by heating the partition layer from the crystal growth plate to obtain a single crystalline silicon layer of a predetermined thickness on the substrate.

Abstract: The present invention provides a thin film transistor in which a substantial length of a channel is shortened to miniaturize a semiconductor device and a manufacturing method thereof. In addition, the present invention provides a semiconductor device which realizes high-speed operation and high-performance of the semiconductor device and a manufacturing method thereof. Further in addition, it is an object of the present invention to provide a manufacturing method in which a manufacturing process is simplified. The semiconductor device of the present invention has an island-shaped semiconductor film formed over a substrate having an insulating surface and a gate electrode formed over the island-shaped semiconductor film, in which the gate electrode is oxidized its surface by high-density plasma to be slimmed and the substantial length of a channel is shortened.

Abstract: The semiconductor device according to this invention is characterized by a package structure of a semiconductor substrate 100 equipped with a photoelectric converting portion, wherein a light-shading means 104 is arranged in an area corresponding to at least the photoelectric converting portion on the side of the rear surface of the semiconductor substrate.

Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a gate electrode, a first insulating film formed between the semiconductor substrate and the gate electrode, and a second insulating film formed along a top surface or a side surface of the gate electrode and including a lower silicon nitride film containing nitrogen, silicon and hydrogen and an upper silicon nitride film formed on the lower silicon nitride film and containing nitrogen, silicon and hydrogen, and wherein a composition ratio N/Si of nitrogen (N) to silicon (Si) in the lower silicon nitride film is higher than that in the upper silicon nitride film.

Abstract: A method for activating the P-type semiconductor layer of a semiconductor device is disclosed in this present invention. The above-mentioned method can activate the impurities in the P-type semiconductor layer of a semiconductor device by plasma. The plasma comprises a gas source including a VI Group compound element. The performance of the semiconductor device activated by plasma according to this invention is similar to the performance of the semiconductor device activated by heat in the prior art. Therefore, this invention can provide a method, other then heat, for activating the P-type semiconductor layer of a semiconductor device. Moreover, in this invention, during the activating process by plasma, the layers other than P-type semiconductor layer will not be affected by plasma. That is, the activating process according to this invention will not cause any side-reactions in the layers other than the P-type semiconductor layer of a semiconductor device.

Abstract: A method and apparatus for fabricating a semiconductor device are provided. First plasma ions are introduced into a process chamber including a semiconductor substrate to amorphize the semiconductor substrate. An inert gas is introduced into the process chamber to purge the first plasma ions. Second plasma ions are introduced into the process chamber to remove impurities formed on the semiconductor substrate. The second plasma ions can be hydrogen ions. Since a PAI process and a cleaning process are performed in a single chamber, process efficiency improves. In addition, a cleaning process using hydrogen ions can reduce damage on the surface of the semiconductor substrate.

Abstract: A method and/or system are provided for producing a structure comprising a thin layer of semiconductor material on a substrate. The method includes creating an area of embrittlement in the thickness of a donor substrate, bonding the donor substrate with a support substrate and detaching the donor substrate at the level of the area of embrittlement to transfer a thin layer of the donor substrate onto the support substrate. The method also includes thermal treatment of this resulting structure to stabilize the bonding interface between the thin layer and the substrate support. The invention also relates to the structures obtained by such a process.

Abstract: A method for fabricating a quartz nanoresonator which can be integrated on a substrate, along with other electronics is disclosed. In this method a quartz substrate is bonded to a base substrate. The quartz substrate is metallized so that a bias voltage is applied to the resonator, thereby causing the quartz substrate to resonate at resonant frequency greater than 100 MHz. The quartz substrate can then be used to drive other electrical elements with a frequency equal to its resonant frequency. The quartz substrate also contains tuning pads to adjust the resonant frequency of the resonator. Additionally, a method for accurately thinning a quartz substrate of the resonator is provided.

Abstract: The invention includes methods of forming and/or passivating semiconductor constructions. In particular aspects, various oxides of a semiconductor substrate can be formed by exposing semiconductive material of the substrate to deuterium-enriched steam. In other aspects, a semiconductor construction is passivated by subjecting the construction to an anneal at a temperature of greater than or equal to 350° C. while exposing the construction to a deuterium-enriched ambient.

Abstract: A method is disclosed for depositing a dielectric film on a substrate having a plurality of gaps formed between adjacent raised surfaces disposed in a high density plasma substrate processing chamber substrate. In one embodiment the method comprises flowing a process gas comprising a germanium source, a silicon source and an oxidizing agent into the substrate processing chamber; forming a high density plasma that has simultaneous deposition and sputtering components from the process gas to deposit a dielectric film comprising silicon, germanium and oxygen; and during the step of forming a high density plasma, maintaining a pressure within the substrate processing chamber of less than 100 mTorr while allowing the dielectric film to be heated above its glass transition temperature.

Abstract: In a metal gate replacement process, a cup-shaped gate metal oxide dielectric may have vertical portions that may be exposed to a reduction reaction. As a result of the reduction reaction, the vertical portions may be converted to metal, which adds to the existing gate electrode. In some cases, removing the vertical dielectric portions reduces fringe capacitance and may also advantageously slightly increased underdiffusion without adding heat, in some embodiments.

Abstract: A semiconductor device including a silicon substrate, a gate insulator film formed on the silicon substrate and including silicon, deuterium, and at least one of oxygen and nitrogen, and a gate electrode formed on the gate insulator film wherein a deuterium concentration in a vicinity of an interface of the gate insulator film with the gate electrode is at least 1×1017 cm?3, and a deuterium concentration in a vicinity of an interface of the gate insulator film with the silicon substrate is higher than the deuterium concentration in the vicinity of the interface of the gate insulation film with the gate electrode.