Abstract: A semiconductor device 100 includes a first gate 210, which is formed using a gate last process. The first gate 210 includes a gate insulating film formed in a bottom surface in a first concave portion formed in the insulating film; a gate electrode formed over the gate insulating film in the first concave portion; and a protective insulating film 140 formed on the gate electrode in the first concave portion. In addition, the semiconductor device 100 includes a contact 134, which is coupled to the N-type impurity-diffused region 116a in the both sides of the first gate 210 and is buried in the second concave portion having a diameter that is large than the first concave portion.

Abstract: The present invention provides a semiconductor apparatus for improving a switching speed and a withstand voltage, and a manufacturing method of the semiconductor apparatus.

Abstract: The present invention is related to a method for reducing attraction forces between wafers (4). This method is characterized in that it comprises the step of, after sawing and before dissolution of the adhesive (5), introducing spacers (6) between wafers (4). The invention comprises also a wafer singulation method and an agent for use in said methods.

Abstract: There is disclosed an exhaust processing process of a processing apparatus for processing a substrate or a film, which comprises after the processing of the substrate or the film, introducing a non-reacted gas and/or a by-product into a trap means comprising a filament comprised of a high-melting metal material comprising as a main component at least one of tungsten, molybdenum and rhenium; and processing the non-reacted gas and/or the by-product inside the trap means. This makes it possible to prevent lowering in exhaust conductance, to lengthen the maintenance cycle of the processing apparatus, and to provide a high-quality product (processed substrate or film).

Abstract: A method for controlling dislocation position in a silicon germanium buffer layer located on a substrate includes irradiating one or more regions of the silicon germanium layer with a dislocation inducing agent and depositing a strained silicon germanium layer on the substrate. The dislocation inducing agent may include ions, electrons, or other radiation source. Dislocations in the silicon germanium layer are located in one or more of the regions. The substrate and strained silicon germanium layer may then be subjected to an annealing process to transform the strained silicon germanium layer into a relaxed state. A top layer of strained silicon or silicon germanium may be deposited on the relaxed silicon germanium layer. Semiconductor-based devices may then be fabricated in the non-damaged regions of the strained silicon or silicon germanium layer. Threading dislocations are confined to damaged areas which may be transformed into SiO2 isolation regions.

Abstract: A method of fabricating an opening or plug. In the process of forming the opening, before a photoresist layer is formed over a dielectric layer, a treatment process is performed to form a film on the dielectric layer, wherein the film can suppress the outgasing phenomenon of the dielectric layer and prevent the later formed photoresist layer from reacting with the running-off composition component from the dielectric layer. Therefore, the problem of incomplete development due to outgasing of the dielectric layer can be solved. Additionally, in the procedure for forming a plug, before a block layer is forming on a surface of a via, a treatment process is performed to form a film on the surface of the via. Therefore, the problem of having defects inside the block layer caused by outgasing of the dielectric layer can be overcome.

Abstract: Methods of forming transparent conducting oxides and devices formed by these methods are shown. Monolayers that contain zinc and monolayers that contain magnesium are deposited onto a substrate and subsequently processed to form magnesium-doped zinc oxide. The resulting transparent conducing oxide includes properties such as an amorphous or nanocrystalline microstructure. Devices that include transparent conducing oxides formed with these methods have better step coverage over substrate topography and more robust film mechanical properties.

Abstract: A thin film transistor array substrate and a method for manufacturing the same is disclosed, in which it is possible to prevent mobile ions contained in a substrate from penetrating into a semiconductor layer by the gettering effect or neutralization in case soda lime glass is used for the substrate. The method includes forming a buffer layer on a substrate; doping impurity ions in the buffer layer; and forming a pixel electrode and a thin film transistor including a semiconductor layer on the buffer layer.

Abstract: After introducing oxygen into an N? type FZ wafer serving as an N? type first semiconductor layer, a P type second semiconductor layer and an anode are formed on a surface of the FZ wafer. The FZ wafer is irradiated with protons from the side of the anode, introducing crystal defects into the FZ wafer. By performing heat treatment to recover the crystal defects in the FZ wafer, the net doping concentration of a portion within the first semiconductor layer is made higher than the initial net doping concentration of the FZ wafer, and a desired broad buffer structure is formed. Accordingly, a semiconductor device with fast operation and low losses, and having soft switching characteristics, can be manufactured inexpensively using FZ bulk wafers, with good controllability and yields.

Abstract: A method of fabricating a polycrystalline silicon layer includes: forming an amorphous silicon layer on a substrate; crystallizing the amorphous silicon layer into a polycrystalline silicon layer using a crystallization-inducing metal; forming a metal layer pattern or metal silicide layer pattern in contact with an upper or lower region of the polycrystalline silicon layer corresponding to a region excluding a channel region in the polycrystalline silicon layer; and annealing the substrate to getter the crystallization-inducing metal existing in the channel region of the polycrystalline silicon layer to the region in the polycrystalline silicon layer having the metal layer pattern or metal silicide layer pattern. Accordingly, the crystallization-inducing metal existing in the channel region of the polycrystalline silicon layer can be effectively removed, and thus a thin film transistor having an improved leakage current characteristic and an OLED display device including the same can be fabricated.

Abstract: In a calibration method, the relation between dopant concentrations of ?-doping layers in a multilayered semiconductor structure and process parameters is determined S1 based on multiple bulk specimens of the material in which the ?-doping layers are located. A desired dopant concentration is selected S2, and the semiconductor structure with predetermined doping levels can be generated S3 based on the relation between the process parameters and the predetermined doping concentrations.

Abstract: Provided are a wafer with the characteristics of abrupt metal-insulator transition (MIT), and a heat treatment apparatus and method that make it possible to mass-produce a large-diameter wafer without directly attaching the wafer to a heater or a substrate holder. The heat treatment apparatus includes a heater applying heat to a wafer having the characteristics of abrupt MIT and one surface covered with a thermally opaque film, and a plurality of fixing units formed along an edge portion of a top surface of the heater to fix the wafer to the heater.

Abstract: A method of introducing an impurity into a wafer surface is provided. The method comprises the steps of: low energy implantation of impurity into a surface of the wafer to generate an implanted dopant layer; and simultaneously removing an implanted surface of the implanted dopant layer to generate a doping profile with controlled areal impurity dosage.

Abstract: The principal objects of the present invention are to provide structure of a semiconductor device capable of reducing a bowing of a wafer, and a method for fabricating the semiconductor device. The present invention is applied to a semiconductor device, which is fabricated with a semiconductor substrate having a silicon carbide (SiC) film. The method includes the steps of: forming the SiC film on a semiconductor wafer; discriminating a deformation condition of the semiconductor wafer; and forming grooves in the SiC film, the grooves having a shape determined in accordance with the deformation condition of the semiconductor wafer.

Abstract: Methods are provided for fabricating a stress enhanced MOS circuit. One method comprises the steps of depositing a stressed material overlying a semiconductor substrate and patterning the stressed material to form a stressed dummy gate electrode overlying a channel region in the semiconductor substrate so that the stressed dummy gate induces a stress in the channel region. Regions of the semiconductor substrate adjacent the channel are processed to maintain the stress to the channel region and the stressed dummy gate electrode is replaced with a permanent gate electrode.

Abstract: Techniques are here disclosed for a solar cell pre-processing. The method and system remove impurities from low-grade crystalline semiconductor wafers and include forming a low-grade semiconductor wafer having a substrate having high impurity content. The process and system damage at least one surface of the semiconductor wafer either in the semiconductor wafer forming step or in a separate step to form a region on the surface that includes a plurality of gettering centers. The gettering centers attract impurities from the substrate during subsequent processing. The subsequent processes include diffusing impurities from the substrate using a phosphorus gettering process that includes impregnating the surface with a phosphorus material for facilitating the formation of impurity clusters associated with the gettering centers.

Abstract: Provided according to some embodiments of the present invention are methods of forming an impurity region in a semiconductor device. Such methods may include forming a pad oxide layer on a substrate; providing impurities to the substrate to form a preliminary impurity region in the substrate; performing a heat treatment process on the substrate while providing oxygen gas and an inert gas to the substrate; and removing the pad oxide layer. Methods according to embodiments of the invention may reduce pitting of the silicon substrate upon removal of the pad oxide layer.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. A preferred embodiment comprises a method of forming an insulating material layer. The method includes forming a barrier layer and forming a rare earth element-containing material layer over the barrier layer.

Abstract: In a vapor-phase growth method in which a silicon-germanium mixed crystal layer is deposited on a semiconductor substrate, the vapor-phase growth method comprises a first step of introducing silicon raw material gas into a reaction furnace in such a manner that a silicon raw material gas partial pressure increases in proportion to a time to thereby deposit a first semiconductor layer of a silicon layer on the semiconductor substrate under reduced pressure, a second step of introducing silicon raw material gas and germanium raw material gas into the reaction furnace in such a manner that a desired germanium concentration may be obtained to thereby deposit a second semiconductor layer of a silicon-germanium mixed crystal layer on the first semiconductor layer under reduced pressure and a third step of introducing silicon raw material gas into the reaction furnace under reduced pressure to thereby deposit a third semiconductor layer of a silicon layer on the second semiconductor layer.

Abstract: A method is provided capable of universally controlling the proximity gettering structure, the need for which can vary from manufacturer to manufacturer, by arbitrarily controlling an M-shaped distribution in a depth direction of a wafer BMD density after RTA in a nitrogen-containing atmosphere. The heat-treatment method is provided for forming a desired internal defect density distribution by controlling a nitrogen concentration distribution in a depth direction of the silicon wafer for heat-treatment, the method including heat-treating a predetermined silicon wafer used for manufacturing a silicon wafer having a denuded zone in the vicinity of the surface thereof.

Abstract: This invention is directed to a process for heat-treating a single crystal silicon segment to influence the profile of minority carrier recombination centers in the segment. The segment is subjected to a heat-treatment to form crystal lattice vacancies, the vacancies being formed in the bulk of the silicon. The segment is then cooled at a rate which allows some, but not all, of the crystal lattice vacancies to diffuse to the front surface to produce a segment having the desired vacancy concentration profile. Platinum atoms are then in-diffused into the silicon matrix such that the resulting platinum concentration profile is substantially related to the concentration profile of the crystal lattice vacancies.