Abstract: A method for manufacturing a vertical CMOS image sensor related to a semiconductor device is disclosed. A high-temperature double annealing process and/or an additional passivation nitride film are selectively applied in order to improve dark leakage characteristics and also to prevent or reduce an incidence of circular defects, thereby enhancing the quality and reliability of the vertical CMOS image sensor.

Abstract: Densely spaced gates of field effect transistors usually lead to voids in a contact interlayer dielectric. If such a void is opened by a contact via and filled with conductive material, an electrical short between neighboring contact regions of neighboring transistors may occur. By forming a recess between two neighboring contact regions, the void forms at a lower level. Thus, opening of the void by contact vias is prevented.

Abstract: A method of manufacturing a semiconductor device according to embodiments includes forming an interlayer dielectric film with a damascene pattern over a semiconductor substrate having a lower metal wire. A seed layer may be formed over the interlayer dielectric film including the damascene pattern. Impurities generated during the formation of the seed layer be removed through an annealing process using H2. A copper wire may then be formed by filling the damascene pattern.

Abstract: Misfit dislocations are redirected from the buffer/Si interface and propagated to the Si substrate due to the formation of bubbles in the substrate. The buffer layer growth process is generally a thermal process that also accomplishes annealing of the Si substrate so that bubbles of the implanted ion species are formed in the Si at an appropriate distance from the buffer/Si interface so that the bubbles will not migrate to the Si surface during annealing, but are close enough to the interface so that a strain field around the bubbles will be sensed by dislocations at the buffer/Si interface and dislocations are attracted by the strain field caused by the bubbles and move into the Si substrate instead of into the buffer epi-layer. Fabrication of improved integrated devices based on GaN and Si, such as continuous wave (CW) lasers and light emitting diodes, at reduced cost is thereby enabled.

Abstract: A method of producing a semiconductor element in a substrate includes forming a plurality of micro-cavities and carbide precipitates in the substrate, creating an amorphization of the substrate to form crystallographic defects and a doping of the substrate with doping atoms, annealing the substrate such that at least a part of the crystallographic defects are eliminated using the micro-cavities and the carbide precipitates, and wherein the semiconductor element is formed using the doping atoms.

Abstract: Disclosed is a method for manufacturing an image sensor. The method includes forming a polysilicon layer on a semiconductor substrate having an active region, forming a sacrificial layer on the polysilicon layer, forming a photoresist pattern on the sacrificial layer, implanting conductive impurities onto the polysilicon layer using the photoresist pattern as an ion implantation mask, removing the photoresist pattern, and removing the sacrificial layer from the polysilicon layer, thereby removing photoresist residues remaining on the sacrificial layer.

Abstract: A method is provided for forming a metal/semiconductor/metal (MSM) current limiter and resistance memory cell with an MSM current limiter. The method provides a substrate; forms an MSM bottom electrode overlying the substrate; forms a ZnOx semiconductor layer overlying the MSM bottom electrode, where x is in the range between about 1 and about 2, inclusive; and, forms an MSM top electrode overlying the semiconductor layer. The ZnOx semiconductor can be formed through a number of different processes such as spin-coating, direct current (DC) sputtering, radio frequency (RF) sputtering, metalorganic chemical vapor deposition (MOCVD), or atomic layer deposition (ALD).

Abstract: Methods of forming a barrier layer are provided. In one embodiment, the method includes providing a substrate into a physical valor deposition (PVD) chamber, supplying at least two reactive gases and an inert gas into the PVD chamber, sputtering a source material from a target disposed in the processing chamber in the presence of a plasma formed from the gas mixture, and forming a metal containing dielectric layer on the substrate from the source material. In another embodiment, the method includes providing a substrate into a PVD chamber, supplying a reactive gas the PVD chamber, sputtering a source material from a target disposed in the PVD chamber in the presence of a plasma formed from the reactive gas, forming a metal containing dielectric layer on the substrate from the source material, and post treating the metal containing layer in presence of species generated from a remote plasma chamber.

Abstract: A method of fabricating a semiconductor transistor device is provided. The fabrication method begins by forming a gate structure overlying a layer of semiconductor material, such as silicon. Then, spacers are formed about the sidewalls of the gate structure. Next, ions of an amorphizing species are implanted into the semiconductor material at a tilted angle toward the gate structure. The gate structure and the spacers are used as an ion implantation mask during this step. The ions form amorphized regions in the semiconductor material. Thereafter, the amorphized regions are selectively removed, resulting in corresponding recesses in the semiconductor material. In addition, the recesses are filled with stress inducing semiconductor material, and fabrication of the semiconductor transistor device is completed.

Abstract: An interconnect structure of the single or dual damascene type and a method of forming the same, which substantially reduces the surface oxidation problem of plating a conductive material onto a noble metal seed layer are provided. In accordance with the present invention, a hydrogen plasma treatment is used to treat a noble metal seed layer such that the treated noble metal seed layer is highly resistant to surface oxidation. The inventive oxidation-resistant noble metal seed layer has a low C content and/or a low nitrogen content.

Abstract: A method for producing a Group IV semiconductor thin film in a chamber is disclosed. The method includes positioning a substrate in the chamber, wherein the chamber further has a chamber pressure. The method further includes depositing a nanoparticle ink on the substrate, the nanoparticle ink including set of Group IV semiconductor nanoparticles and a solvent, wherein each nanoparticle of the set of Group IV semiconductor nanoparticles includes a nanoparticle surface, wherein a layer of Group IV semiconductor nanoparticles is formed. The method also includes striking a hydrogen plasma; and heating the layer of Group IV semiconductor nanoparticles to a fabrication temperature of between about 300° C. and about 1350° C., and between about 1 nanosecond and about 10 minutes; wherein the Group IV semiconductor thin film is formed.

Abstract: A method for manufacturing a semiconductor substrate comprises the steps of: forming a gate oxide film as an insulating layer on the surface of a semiconductor substrate; implanting boron ions for inhibiting the migration of a peeling substance in the semiconductor substrate to form an anti-diffusion layer in the semiconductor substrate; activating boron in the anti-diffusion layer by heat treatment; implanting hydrogen ions into the semiconductor substrate to form a peel layer in part of the semiconductor substrate at a side of the anti-diffusion layer opposite to the gate oxide film; bonding a glass substrate to the surface of the semiconductor substrate where the gate oxide film has been formed; and heat-treating the semiconductor substrate to separate part of the semiconductor substrate along the peel layer.

Abstract: Hydrogen gas is ion-implanted into a silicon wafer for active layer via an insulating film, and thus ion-implanted wafer is then bonded with a supporting wafer via an insulating film interposed therebetween. This bonded wafer is heated to 500° C., so that a part of the bonded wafer is cleaved and separated, thereby producing an SOI wafer. Subsequently, thus-obtained SOI wafer is subjected to a heat treatment in an argon gas atmosphere. After that, the SOI wafer is subjected to an oxidation process in an oxidizing atmosphere, and thus formed oxide film is removed using an HF solution. Consequently, the surface of the SOI wafer is recrystallized and thus planarized.

Abstract: A bonded wafer is produced by implanting ions of a light element into a wafer for active layer to a predetermined depth position to form an ion implanted layer, bonding the wafer for active layer to a wafer for support substrate directly or through an insulating film of not more than 50 nm, exfoliating the wafer for active layer at the ion implanted layer and thinning an active layer exposed through the exfoliation to form the active layer having a predetermined thickness, in which the thickness of the active layer before the thinning is not more than 750 nm and an elongation of slip dislocation in a strength test of the wafer for active layer before the bonding is not more than 100 ?m at a predetermined thickness.

Abstract: A method and apparatus for depositing a material layer onto a substrate is described. The method includes delivering a mixture of precursors for the material layer into a process chamber and depositing the material layer on the substrate at low temperature. The material layer can be used as an encapsulating layer for various display applications which require low temperature deposition process due to thermal instability of underlying materials used. In one aspect, the encapsulating layer includes one or more material layers (multilayer) having one or more barrier layer materials and one or more low-dielectric constant materials. The encapsulating layer thus deposited provides reduced surface roughness, improved water-barrier performance, reduce thermal stress, good step coverage, and can be applied to many substrate types and many substrate sizes. Accordingly, the encapsulating layer thus deposited provides good device lifetime for various display devices, such as OLED devices.

Abstract: In a method for using a film formation apparatus for a semiconductor process, process conditions of a film formation process are determined. The process conditions include a preset film thickness of a thin film to be formed on a target substrate. Further, a timing of performing a cleaning process is determined in accordance with the process conditions. The timing is defined by a threshold concerning a cumulative film thickness of the thin film. The cumulative film thickness does not exceed the threshold where the film formation process is repeated N times (N is a positive integer), but exceeds the threshold where the film formation process is repeated N+1 times. The method includes continuously performing first to Nth processes, each consisting of the film formation process, and performing the cleaning process after the Nth process and before an (N+1)th process consisting of the film formation process.

Abstract: A method of forming a semiconductor device including forming a low-k dielectric material over a substrate, depositing a liner on a portion of the low-k dielectric material, and exposing the liner to a plasma. The method also includes depositing a layer over the liner.

Abstract: This invention relates to a process for adjusting the strain in a strained layer on a substrate. The process steps include identifying one or more regions of the strained layer wherein the strain is to be adjusted; implanting elements into at least one of the regions thus identified in the strained layer; annealing the substrate with the strained layer to a temperature maintained for a sufficiently long time to cure crystalline defects caused by the implantation in the implanted region or regions.

Abstract: It is an object of the present invention to provide a high reliable EL display device and a manufacturing method thereof by shielding intruding moisture or oxygen which is a factor of deteriorating the property of an EL element without enlarging the EL display device. In the invention, application is used as a method for forming a high thermostability planarizing film 16, typically, an interlayer insulating film (a film which serves as a base film of a light emitting element later) of a TFT in which a skeletal structure is configured by the combination of silicon (Si) and oxygen (O). After the formation, an edge portion or an opening portion is formed to have a tapered shape. Afterwards, distortion is given by adding an inert element with a comparatively large atomic radius to modify or highly densify a surface (including a side surface) for preventing the intrusion of moisture or oxygen.

Abstract: A method of fabricating thin films of semiconductor materials by implanting ions in a substrate composed of at least two different elements at least one of which can form a gaseous phase on bonding with itself and/or with impurities includes the following steps: (1) bombarding one face of the substrate with ions of a non-gaseous heavy species in order to implant those ions in a concentration sufficient to create in the substrate a layer of microcavities containing a gaseous phase formed by the element of the substrate; (2) bringing this face of the substrate into intimate contact with a stiffener; and (3) obtaining cleavage at the level of the microcavity layer by the application of heat treatment and/or a splitting stress.

Abstract: A method for manufacturing a SIMOX wafer includes: heating a silicon wafer, implanting oxygen ions so as to form a high oxygen concentration layer; implanting oxygen ions into the silicon wafer obtained by the forming of the high oxygen concentration layer to form an amorphous layer; and heat-treating the silicon wafer to form a buried oxide layer, wherein in the forming of the amorphous layer, the implantation of oxygen ions is carried out after preheating the silicon wafer to a temperature lower than the heating temperature of the forming of the high oxygen concentration layer. Alternatively, the method for manufacturing a SIMOX wafer includes: in the formation of the high oxygen concentration layer, implanting oxygen ions while heating a silicon wafer at a temperature of 300° C. or more; and in the formation of the amorphous layer, implanting oxygen ions after preheating the silicon wafer to a temperature of less than 300° C.

Abstract: A thin-film formation apparatus possesses a reaction chamber to be evacuated, a placing portion on which a substrate is placed inside the reaction chamber, a gas-dispersion guide installed over the placing portion for supplying a gas onto a substrate surface, a gas-supply port for introducing the gas into the gas-dispersion guide, a gas-dispersion plate disposed on the side of the substrate of the gas-dispersion guide and having multiple gas-discharge pores, a first exhaust port for exhausting, downstream of the gas-dispersion plate, the gas supplied onto the substrate surface from the gas-dispersion plate, and a second exhaust port for exhausting, upstream of the gas-dispersion plate, a gas inside the gas-dispersion guide via a space between the gas-dispersion guide and the gas-dispersion plate.

Abstract: A high-k dielectric film, a method of forming the high-k dielectric film, and a method of forming a related semiconductor device are provided. The high-k dielectric film includes a bottom layer of metal-silicon-oxynitride having a first nitrogen content and a first silicon content and a top layer of metal-silicon-oxynitride having a second nitrogen content and a second silicon content. The second nitrogen content is higher than the first nitrogen content and the second silicon content is higher than the first silicon content.

Abstract: A method of manufacturing a semiconductor device contact including forming an insulating layer over a substrate and forming an agglutinating layer over the insulating layer. The agglutinating layer is then exposed to a plasma treatment. A barrier layer is formed over the plasma-treated agglutinating layer, and a conductive layer is formed over the barrier layer.

Abstract: A method is disclosed of forming an extension region for a transistor having a gate structure overlying a compound semiconductor layer. An anneal is used either before or after deep source/drain implantation to diffuse a dopant from a raised region adjacent the gate structure to a location underlying the gate structure. A non-diffusing activation process can be used to activate source/drain implants when the dopants from the raised region are diffused prior to deep source/drain implantation.

Abstract: A method and apparatus for fabricating a semiconductor device are provided. First plasma ions are introduced into a process chamber including a semiconductor substrate to amorphize the semiconductor substrate. An inert gas is introduced into the process chamber to purge the first plasma ions. Second plasma ions are introduced into the process chamber to remove impurities formed on the semiconductor substrate. The second plasma ions can be hydrogen ions. Since a PAI process and a cleaning process are performed in a single chamber, process efficiency improves. In addition, a cleaning process using hydrogen ions can reduce damage on the surface of the semiconductor substrate.

Abstract: The present invention provides a system for removing organic contaminants (216) from a copper seed layer that has been deposited on a semiconductor substrate (206). The present invention provides a housing (204) to enclose the semiconductor substrate within. An ultraviolet radiation source (210) is disposed within the housing. A treatment medium (208) is also provided within the housing. The semiconductor substrate is enclosed within the housing and exposed to the treatment medium. The ultraviolet radiation source exposes the semiconductor substrate to ultraviolet radiation, desorbing the contaminants from the seed layer.

Abstract: Embodiments of the present invention relate to an apparatus and method of annealing substrates in a thermal anneal chamber and/or a plasma anneal chamber before electroless deposition thereover. In one embodiment, annealing in a thermal anneal chamber includes heating the substrate in a vacuum environment while providing a gas, such as noble gases, hydrogen gas, other reducing gases, nitrogen gas, other non-reactive gases, and combinations thereof. In another embodiment, annealing in a plasma chamber comprises plasma annealing the substrate in a plasma, such as a plasma from an argon gas, helium gas, hydrogen gas, and combinations thereof.

Abstract: A method of forming a relaxed SiGe layer having a high germanium content in a semiconductor device includes preparing a silicon substrate; depositing a strained SiGe layer; implanting ions into the strained SiGe layer, wherein the ions include silicon ions and ions selected from the group of ions consisting of boron and helium, and which further includes implanting H+ ions; annealing to relax the strained SiGe layer, thereby forming a first relaxed SiGe layer; and completing the semiconductor device.

Abstract: A process for producing an electronic device material of a high quality MOS-type semiconductor having an insulating layer and a semiconducting layer. The process includes a step of CVD-treating a substrate to be processed having single-crystal silicon as a main component to thereby form an insulating layer, and a step of exposing the substrate to be processed to a plasma which has been generated from a process gas on the basis of microwave irradiation via a plane antenna member having a plurality of slots to thereby modify the insulating film by using the thus generated plasma.

Abstract: An interconnect structure which includes a plating seed layer that has enhanced conductive material, preferably, Cu, diffusion properties is provided that eliminates the need for utilizing separate diffusion and seed layers. Specifically, the present invention provides an oxygen/nitrogen transition region within a plating seed layer for interconnect metal diffusion enhancement. The plating seed layer may include Ru, Ir or alloys thereof, and the interconnect conductive material may include Cu, Al, AlCu, W, Ag, Au and the like. Preferably, the interconnect conductive material is Cu or AlCu. In more specific terms, the present invention provides a single seeding layer which includes an oxygen/nitrogen transition region sandwiched between top and bottom seed regions. The presence of the oxygen/nitrogen transition region within the plating seed layer dramatically enhances the diffusion barrier resistance of the plating seed.

Abstract: Disclosed in a method of forming a copper wiring in a semiconductor device. A copper layer buries a damascene pattern in which an interlayer insulating film of a low dielectric constant. The copper layer is polished by means of a chemical mechanical polishing process to form a copper wiring within a damascene pattern. At this time, the chemical mechanical polishing process is overly performed so that the top surface of the copper wiring is concaved and is lower than the surface of the interlayer insulating film of the low dielectric constant neighboring it. Furthermore, an annealing process is performed so that the top surface of the copper wiring is changed from the concaved shape to a convex shape while stabilizing the copper wiring. A copper anti-diffusion insulating film is then formed on the entire structure including the top surface of the copper wiring having the convex shape.

Abstract: A semiconductor device is formed by performing an amorphizing ion implantation to implant dopants of a first conductivity type into a semiconductor body. The first ion implantation causes a defect area (e.g., end-of-range defects) within the semiconductor body at a depth. A non-amorphizing implantation implants dopants of the same conductivity type into the semiconductor body. This ion implantation step implants dopants throughout the defect area. The dopants can then be activated by heating the semiconductor body for less than 10 ms, e.g., using a flash anneal or a laser anneal.

Abstract: A method of fabricating a high-quality silicon thin layer includes making Xe ions generated by RF power collide with a silicon target material layer to generate silicon particles from the silicon target material layer; and depositing the silicon particles on a predetermined substrate. The method is performed under a pressure of about 5 mTorr or lower and at an RF power of about 200 W or more. In this method, the silicon thin layer is thermally stabilized, and the amount of gas captured in silicon crystals during the sputtering process is greatly reduced.

Abstract: A method for producing a semiconductor structure that includes at least one useful layer on a substrate.

Abstract: A method for concurrently producing at least a pair of semiconductor structures that each include at least one useful layer on a substrate. The method includes providing an initial structure that includes a useful layer having a front face on a support substrate. Atomic species are implanted into the useful layer to a controlled mean implantation depth to form a zone of weakness within the useful layer that defines first and second useful layers. Next, a stiffening substrate is bonded to the front face of the initial structure. The first useful layer is then detached from the second useful layer along the zone of weakness to obtain a pair of semiconductor structures with a first structure including the stiffening substrate and the first useful layer and a second structure including the support substrate and the second useful layer. The structures obtained can be used in the fields of electronics, optoelectronics or optics.