Abstract: A method for programming an anti-fuse element in which the ratio between current values before and after writing is increased to ensure accuracy in making a judgment about how writing has been performed on the anti-fuse element. The method for programming the anti-fuse element as a transistor includes the steps of applying a prescribed gate voltage to a gate electrode to break down a gate dielectric film, and moving the silicide material of a silicide layer formed on a surface of at least one of a first impurity diffusion region and a second impurity diffusion region, into the gate dielectric film in order to couple the gate electrode with at least the one of the first impurity diffusion region and the second impurity diffusion region electrically through the silicide material.

Abstract: A system for dicing substrates to singulate integrated circuit units within in them includes a dicing machine (Z) which operates with a chuck table (4). A lifting assembly (Ax,Ay) deposits substrates to be singulated onto the chuck table (4) at substantially the same time as it removes previously singulated units from the chuck table (4).

Abstract: A method for the production of a contact structure of a solar cell allows p-contacts and n-contacts to be produced simultaneously.

Abstract: The present invention provides antifuse structures having an integrated heating element and methods of programming the same, the antifuse structures comprising first and second conductors and a dielectric layer formed between the conductors, where one or both of the conductors functions as both a conventional antifuse conductor and as a heating element for directly heating the antifuse dielectric layer during programming.

Abstract: Carbon nanotube template arrays may be edited to form connections between proximate nanotubes and/or to delete undesired nanotubes or nanotube junctions.

Abstract: A method is provided for detecting laser optical paths in integrated circuit (IC) packages. The method provides an IC die encapsulated as a package in a compound of glass spheres and epoxy. Power is supplied to the IC. The IC is scanned with a laser. Typically, a laser wavelength is used that is minimally absorbed by the glass spheres in the epoxy compound of the IC package, and changes in current to the IC are detected. A detected current change is cross-referenced against a scanned IC package surface region. This process identifies an optical pathway underlying the scanned IC package surface region. In some aspects, this process leads to the identification of a glass sphere-collecting package structure underlying the optical pathway. Examples of a glass sphere-collecting structure might include an inner lead wire, lead frame edge, or die edge.

Abstract: A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming, on a surface of a semiconductor substrate, an isolation trench including sidewall parts and a bottom part, or a stepped structure including a first planar part, a second planar part, and a step part located at a boundary between the first planar part and the second planar part, and supplying oxidizing ions or nitriding ions contained in plasma generated by a microwave, a radio-frequency wave, or electron cyclotron resonance to the sidewall parts and the bottom part of the isolation trench or the first and second planar parts and the step part of the stepped structure by applying a predetermined voltage to the semiconductor substrate, to perform anisotropic oxidation or anisotropic nitridation of the sidewall parts and the bottom part of the isolation trench or the first and second planar parts and the step part of the stepped structure.

Abstract: Efficient power management method in integrated circuit through a nanotube structure is disclosed. In one embodiment, a method includes patterning a nanotube structure adjacent to a transistor layer of an integrated circuit. The transistor layer may be above a semiconductor substrate. The transistor layer above the semiconductor substrate may comprise a plurality of transistors. The method also includes supplying power to the plurality of transistors through one or more power sources. In addition, the method includes coupling the plurality of transistors in the transistor layer to the one or more power sources based on a state of the nanotube structure.

Abstract: In one embodiment, a node comprises a plurality of processor cores and a node controller configured to receive a first read operation addressing a first register. The node controller is configured to return a first value in response to the first read operation, dependent on which processor core transmitted the first read operation. In another embodiment, the node comprises the processor cores and the node controller. The node controller comprises a queue shared by the processor cores. The processor cores are configured to transmit communications at a maximum rate of one every N clock cycles, where N is an integer equal to a number of the processor cores. In still another embodiment, a node comprises the processor cores and a plurality of fuses shared by the processor cores. In some embodiments, the node components are integrated onto a single integrated circuit chip (e.g. a chip multiprocessor).

Abstract: In at least one embodiment, a TFT includes: a first capacitor formed of a first capacitor electrode connected to a source electrode and a second capacitor electrode; a second capacitor formed of a third capacitor electrode and a fourth capacitor electrode; a first lead-out line; a second lead-out line connected to a gate electrode; a third lead-out line; a fourth lead-out line; a first interconnection; and a second interconnection. This realizes a TFT which can be easily saved from being a defective product even if leakage occurs in a capacitor connected to a TFT body section.

Abstract: A coating process to infill high aspect-ratio vias and trenches in semiconductor substrates with dense boron for the production of neutron detectors and other devices uses a vacuum cathodic arc or other source of fully ionized boron plasma. Biasing of the substrate is used to impart energies to the plasma ions directing them toward the substrate, while repulsing the electrons. The full ionization produced by the source allows control of the energies of the boron ions by means of the bias voltage. The bias is alternated between coating deposition at low ion energies and sputtering of already coated material by energetic ions. Most of the sputtered material comes off the substrate top surface and between the trenches or vias and much of it is redeposited, thereby contributing to the infill. The process is suitable for carbon, boron or similar light elements, and is of particular interest for 10B, an element having exceptionally high thermal neutron cross-section.

Abstract: A method for manufacturing a thin film photoelectric conversion module includes the steps of forming a plurality of photoelectric conversion elements connected in series on a substrate, and carrying out reverse bias processing simultaneously on a group of photoelectric conversion elements including a plurality of the photoelectric conversion elements positioned with one or a plurality of the photoelectric conversion elements interposed between each of them, by applying a plurality of voltages electrically isolated from one another to the group of photoelectric conversion elements.

Abstract: Exposed are a semiconductor device and method of fabricating the same. The device includes an insulation film that is disposed between an active pattern and a substrate, which provides various improvements. This structure enhances the efficiency of high integration and offers an advanced structure for semiconductor devices.

Abstract: This invention relates to methods and devices for the production of optical microstructures or domains in dielectric substrates based on electrothermal focussing. More specifically, the invention relates to a method of introducing a change of dielectric and/or optical properties in a region of an electrically insulating or electrically semiconducting substrate, and to substrates produced by such method.

Abstract: Structure and method for providing a programmable anti-fuse in a FET structure. A method of forming the programmable anti-fuse includes: providing a p? substrate with an n+ gate stack; implanting an n+ source region and an n+ drain region in the p? substrate; forming a resist mask over the n+ drain region, while leaving the n+ source region exposed; etching the n+ source region to form a recess in the n+ source region; and growing a p+ epitaxial silicon germanium layer in the recess in the n+ source region to form a pn junction that acts as a programmable diode or anti-fuse.

Abstract: A diode is disclosed. One embodiment provides a semiconductor body having a front and a back, opposite the front in a vertical direction of the semiconductor body. The semiconductor body contains, successively in the vertical direction from the back to the front, a heavily n-doped zone, a weakly n-doped zone, a weakly p-doped zone and a heavily p-doped zone. In the vertical direction, the weakly p-doped zone has a thickness of at least 25% and at most 50% of the thickness of the semiconductor body.

Abstract: Embodiments of a system with first means for forming a chamber adjacent to a component formed on a substrate and a single orifice between the chamber and a first surface of the first means that is opposite a second surface of the first means adjacent to the substrate and second means for enclosing the chamber on at least a portion of the first surface that encompasses the single orifice are disclosed.

Abstract: A system for dicing substrates to singulate integrated circuit units within in them includes a dicing machine (Z) which operates with a chuck table (4). A lifting assembly (Ax,Ay) deposits substrates to be singulated onto the chuck table (4) at substantially the same time as it removes previously singulated units from the chuck table (4).

Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include forming an identification mark on a portion of a backside of an individual die of a wafer by utilizing laser assisted CVD, wherein the formation of the identification mark is localized to a focal spot of the laser.

Abstract: A semiconductor device includes an interlayer insulating film formed above a semiconductor substrate. The interlayer insulating film has a concave portion. A barrier metal layer is formed along a bottom and a sidewall of the concave portion. The barrier metal layer has a first portion provided along the sidewall of the concave portion and a second portion provided along the bottom of the concave portion. A metal wiring layer is formed in the concave portion via the barrier metal layer. The first portion of the barrier metal layer is composed of a titanium nitride layer whose titanium content is more than 50 at %, and the second portion of the barrier metal layer is composed of a titanium nitride layer whose titanium content is relatively larger than the titanium content of the first portion or of a Ti layer.

Abstract: A method for manufacturing a photovoltaic device including one or a plurality of photovoltaic cells is provided. Each of the photovoltaic cells includes a transparent conductive film, a photovoltaic layer, and a metal electrode which are formed on a substrate. A voltage is applied between a first portion of the metal electrode and a second portion of the metal electrode that is distant from the first portion, so as to remove at least apart of the metal electrode.

Abstract: A non-volatile memory cell and a fabrication method thereof are provided. The non-volatile memory cell includes an anode; a cathode having a surface facing the anode; a specific structure disposed on the surface; and an ion conductor disposed among the anode, the cathode and the specific structure, wherein the specific structure is one of a bulging area on the surface of the cathode and an insulating layer with an opening.

Abstract: An antifuse contains a first silicide layer, a grown silicon oxide antifuse layer on a first surface of the first silicide layer, and a first semiconductor layer having a first surface in contact with the antifuse layer.

Abstract: A method for fabricating a semiconductor transistor which eliminates device defects generated during an etching process for forming gates. The method may include laminating an ONO layer on and/or over a semiconductor substrate, and then coating a polysilicon layer on and/or over the ONO layer, and then forming a photoresist pattern on and/or over the polysilicon layer, and then sequentially performing a first etching of the polysilicon layer using the photoresist pattern as an etching mask so as to maintain a predetermined thickness of the polysilicon layer and then a second etching to remove the polysilicon layer remaining from the first etching.

Abstract: Provided is a method of manufacturing a photovoltaic device using a Joule heating-induced crystallization method. The method includes: forming a first conductive pattern on a substrate; forming a photoelectric conversion layer on the substrate having the first conductive pattern; and crystallizing at least part of the photoelectric conversion layer by applying an electric field to the photoelectric conversion layer, wherein the photoelectric conversion layer includes a first amorphous semiconductor layer containing first impurities, a second intrinsic, amorphous semiconductor layer, and a third amorphous semiconductor layer containing second impurities.

Abstract: A method of forming a microball grid array includes adhering a microball precursor material to a transfer medium under conditions to reflect a selective charge pattern. The method includes transferring the microball precursor material from the transfer medium across a gap and to an integrated circuit substrate under conditions to reflect the selective charge pattern. The method includes achieving the microball grid array without the aid of a mask.

Abstract: An embodiment of a Geiger-mode avalanche photodiode includes a body of semiconductor material having a first conductivity type, a first surface and a second surface; a trench extending through the body from the first surface and surrounding an active region; a lateral-isolation region within the trench, formed by a conductive region and an insulating region of dielectric material, the insulating region surrounding the conductive region; an anode region having a second conductivity type, extending within the active region and facing the first surface. The active region forms a cathode region extending between the anode region and the second surface, and defines a quenching resistor. The photodiode has a contact region of conductive material, overlying the first surface and in contact with the conductive region for connection thereof to a circuit biasing the conductive region, thereby a depletion region is formed in the active region around the insulating region.

Abstract: A method for manufacturing a thin film is provided. A substrate is loaded into a chamber. A first reaction gas and a second reaction gas are supplied into the chamber. The first reaction gas is dissociated to form crystalline nanoparticles. An amorphous material is inhibited from being formed on the substrate using the second reaction gas. Thereafter, a crystalline thin film is formed from the crystalline nanoparticles provided on the substrate.

Abstract: Non-polar or semi-polar (Al, Ga, In)N substrates are fabricated by re-growth of (Al, Ga, In)N crystal on (Al, Ga, In)N seed crystals, wherein the size of the seed crystal expands or is increased in the lateral and vertical directions, resulting in larger sizes of non-polar and semi-polar substrates useful for optoelectronic and microelectronic devices. One or more non-polar or semi-polar substrates may be sliced from the re-grown crystal. The lateral growth rate may be greater than the vertical growth rate. The seed crystal may be a non-polar seed crystal. The seed crystal may have crystalline edges of equivalent crystallographic orientation.

Abstract: The electronic properties (such as electron mobility, resistivity, etc.) of an electronic material can be modified/enhanced when subjected to dynamic or stationary magnetic fields in conjunction with select cycles of heating, cooling and passage of electric current through the material. This “processing” includes one or more cycles using combinations of the aforementioned variables.

Abstract: One-transistor memory devices facilitate nonvolatile data storage through the manipulation of oxygen vacancies within a trapping layer of a field-effect transistor (FET), thereby providing control and variation of threshold voltages of the transistor. Various threshold voltages may be assigned a data value, providing the ability to store one or more bits of data in a single memory cell. To control the threshold voltage, the oxygen vacancies may be manipulated by trapping electrons within the vacancies, freeing trapped electrons from the vacancies, moving the vacancies within the trapping layer and annihilating the vacancies.

Abstract: A wafer is mounted on the top surface of the stage having an electrostatic chuck function, and the wafer at 50° C. or more is cooled to a temperature lower than 50° C. In this step, the voltage to be applied to the internal electrode provided in the stage is raised stepwise to gradually increase the contact area between the back surface of the wafer and the top surface of the stage. Finally, a chuck voltage is applied to the internal electrode, so that the entire back surface of the wafer is uniformly attracted to the top surface of the stage. This reduces damage occurring in the top surface of the stage due to rubbing between the back surface of the wafer and the top surface of the stage.

Abstract: A diode is disclosed. One embodiment provides a semiconductor body having a front and a back, opposite the front in a vertical direction of the semiconductor body. The semiconductor body contains, successively in the vertical direction from the back to the front, a heavily n-doped zone, a weakly n-doped zone, a weakly p-doped zone and a heavily p-doped zone. In the vertical direction, the weakly p-doped zone has a thickness of at least 25% and at most 50% of the thickness of the semiconductor body.

Abstract: Examples of the present invention include methods of assembling structures, such as nanostructures, at predetermined locations on a substrate. A voltage between spaced-apart electrodes supported by substrate attracts the structures to the substrate, and positional registration can be provided the substrate using topographic features such as wells. Examples of the present invention also include devices, such as electronic and optoelectronic devices, prepared by such methods.

Abstract: A method for passivating short circuit defects in a thin film large area photovoltaic device in accordance with an exemplary embodiment is provided. The method employs a passivation agent and a counter electrode disposed in said passivation agent. The method includes controlling an application of current between the substrate of said photovoltaic device and said counter electrode so as to ensure high selectivity of modification of a transparent conductive oxide material of said photovoltaic module adjacent said short circuit defect, while leaving the transparent conductive oxide material of said photovoltaic module of non-defect areas in its unmodified form.

Abstract: The present invention provides a method for preparation of crystallization of amorphous silicon thin film, which comprises providing a forming a amorphous silicon on a dielectric film formed on a transparent substrate; then forming a conductive layer on the top surface of substrate; applying an electric field to the conductive layer so as to generate heat; and crystallization of amorphous silicon thin film by the generated heat.

Abstract: A thin film transistor (TFT) including a nanowire semiconductor layer having nanowires aligned in one direction in a channel region is disclosed. The nanowire semiconductor layer is selectively formed in the channel region. A method for fabricating the TFT, a liquid crystal display (LCD) device using the TFT, and a method for manufacturing the LCD device are also disclosed. The TFT fabricating method includes forming alignment electrodes on the insulating film such that the alignment electrodes face each other, to define a channel region, forming an organic film, to expose the channel region, coating a nanowire-dispersed solution on an entire surface of a substrate including the organic film, forming a nanowire semiconductor layer in the channel region by generating an electric field between the alignment electrodes such that nanowires of the nanowire semiconductor layer are aligned in a direction, and removing the organic film.

Abstract: A fuse structure includes a non-planar fuse material layer typically located over and replicating a topographic feature within a substrate. The non-planar fuse material layer includes an angular bend that assists in providing a lower severance current within the non-planar fuse material layer.

Abstract: A method of fabricating a thin film transistor, in which source and drain electrodes are formed through a solution process, even all stages which include formation of electrodes on a substrate, formation of an insulator layer, and formation of an organic semiconductor layer are conducted through the solution process. In the method, the fabrication is simplified and a fabrication cost is reduced. It is possible to apply the organic thin film transistor to integrated circuits requiring high speed switching because of high charge mobility.

Abstract: A MEMS system including a fixed electrode and a suspended moveable electrode that is controllable over a wide range of motion. In traditional systems where an fixed electrode is positioned under the moveable electrode, the range of motion is limited because the support structure supporting the moveable electrode becomes unstable when the moveable electrode moves too close to the fixed electrode. By repositioning the fixed electrode from being directly underneath the moving electrode, a much wider range of controllable motion is achievable. Wide ranges of controllable motion are particularly important in optical switching applications.

Abstract: A method for crystallizing an amorphous silicon layer is provided. (A) A substrate with an amorphous silicon layer thereon is provided. (B) A mask with a mask pattern is provided. The mask pattern includes a first region pattern and a second region pattern in mirror symmetry. (C) The first region pattern is selected as a first scanning region and the substrate is moved toward a first direction, such that a laser beam passes through the first region pattern to crystallize the amorphous silicon layer along the first direction. (D) The second region pattern is selected as a second scanning region and the substrate is moved toward a second direction, such that the laser beam passes through the second region pattern to crystallize the amorphous silicon layer along the second direction. (E) The steps of (C) and (D) are repeated to convert the whole amorphous silicon layer into a polysilicon layer.

Abstract: Pathways to rapid and reliable fabrication of nanocylinder arrays are provided. Simple methods are described for the production of well-ordered arrays of nanopores, nanowires, and other materials. This is accomplished by orienting copolymer films and removing a component from the film to produce nanopores, that in turn, can be filled with materials to produce the arrays. The resulting arrays can be used to produce nanoscale media, devices, and systems.

Abstract: Certain modifications and additions to the prior art short passivation technique have lead to improvements in the low light voltage of solar cells which are made using the improved passivation technique. Examples of the modifications include: 1) reducing the voltage bias on the cell while increasing the time of application of the voltage; 2) reversing the polarity of the voltage bias on the devices; 3) alternating pulsing between forward and reverse polarity bias; or 4) applying light energy simultaneously with an electrical bias voltage.

Abstract: A method for developing a manufacturing process includes measuring, in a first testing environment, a primary property of a nano-engineered material at one or more positions to provide one or more measurements. The method also includes determining whether the one or more measurements satisfy a first tolerance criterion and taking a further action based on whether the one or more measurements satisfy the first tolerance criterion. Additionally, a method of measuring thermal properties of a nano-engineered material includes irradiating a nano-engineered material with laser radiation, wherein the laser radiation impinges on a first surface of the nano-engineered material at one ore more locations, capturing at least one image of the nano-engineered material, and analyzing the at least one image to characterize the thermal properties of the nano-engineered material.

Abstract: Diode devices with superior and pre-settable characteristics and of nanometric dimensions, comprise etched insulative lines (8, 16, 18) in a conductive substrate to define between the lines charge carrier flow paths, formed as elongate channels (20) at least 100 nm long and less than 100 nm wide. The current-voltage characteristic of the diode devices are similar to a conventional diode, but both the threshold voltage (from 0V to a few volts) and the current level (from nA to ?A) can be tuned by orders of magnitude by changing the device geometry. Standard silicon wafers can be used as substrates. A full family of logic gates, such as OR, AND, and NOT, can be constructed based on this device solely by simply etching insulative lines in the substrate.

Abstract: Polysilicon or other material is directionally trimmed using two layers of photoresist and a photoresist etching process, such as ashing. A first layer of photoresist is patterned on a wafer. Portions of the first patterned photoresist are covered with a second layer of photoresist. The photoresist is trimmed to reduce the size of the exposed portions of the first patterned photoresist without reducing the size of the covered portions of the first patterned photoresist. The second layer of photoresist is removed. The selectively etched patterned first layer of photoresist is used as a process mask to define a structure in the underlying material. In a particular embodiment, the second photoresist covers endcap portions of gate photoresist. Directional trimming reduces the width of a polysilicon gate structure (i.e. gate length) over an active area of an FET, without reducing the length of original first patterned photoresist.