Abstract: Embodiments of the present application provide an electroplating method and an electroplating apparatus. The electroplating method includes: before putting wafers into an electroplating solution to undergo an electroplating process, adding particles into the electroplating solution, and applying ultrasonic waves to the electroplating solution, so as to remove bubbles in the electroplating solution by oscillation; removing the particles in the electroplating solution; and putting the wafers into the electroplating solution to undergo the electroplating process.

Abstract: Methods of fabricating a semiconductor device include providing a semiconductor substrate that includes a plurality of epitaxial layers, including a channel layer and a permanent cap over the channel layer, where the permanent cap defines an upper surface of the semiconductor substrate, and forming a sacrificial cap over the permanent cap in an active region of the device, where the sacrificial cap comprises a semiconductor material that includes aluminum. The method also includes forming one or more current carrying regions (e.g., source and drain regions) in the semiconductor substrate in the active region of the device by performing an ion implantation process to implant ions through the sacrificial cap, and into the semiconductor substrate, completely removing the sacrificial cap in the active region of the device, while refraining from removing the permanent cap, and forming one or more current carrying contacts over the one or more current carrying regions.

Abstract: A laser alignment fixture for a reactor system may be used to align components of the reactor system to allow for a uniform deposition of a thin film onto a substrate. The laser alignment fixture may include: a lid assembly; and a plurality of laser and sensor assemblies. The laser alignment fixture may align at least: a flow control ring, a susceptor, and a side wall of the reactor system.

Abstract: A monocrystalline germanium wafer that increases the open-circuit voltage of multijunction solar cells, a method for preparing the monocrystalline germanium wafer and a method for preparing an ingot from which the monocrystalline germanium wafer is prepared. The monocrystalline germanium wafer that increases the open-circuit voltage of the bottom cell of multijunction solar cells is prepared by adjusting the amounts of the co-dopants silicon and gallium in the monocrystalline germanium wafer, the ratio of silicon to gallium in the preparation of the monocrystalline germanium.

Abstract: The present disclosure provides an impedance matching method, an impedance matching device and a plasma generating device. The impedance matching method is implemented for matching an impedance of a load connected to an RF source to an impedance of the RF source, including: selectively performing an automatic matching step or a frequency scan matching step according to an operation mode of the RF source, wherein: in the automatic matching step, instructing a motor to drive an impedance matching network to provide a certain impedance; and in the frequency scan matching step, instructing the motor to stop driving and the RF source to perform a frequency scanning operation. According to the embodiments of the present disclosure, a phenomenon of unstable and non-repetitive matching caused by fast impedance changing during the impedance matching process can be effectively avoided, and a large processing window and process stability can be implemented.

Abstract: An ion implanter may include an electrostatic clamp to hold a substrate; a plasma flood gun generating a flux of electrons impinging upon the substrate; and a controller coupled to the plasma flood gun and including a component generating a control signal responsive to a measurement signal, the control signal to adjust operation of the plasma flood gun to a target operating level. At the target operating level the flux of electrons may comprise a stabilizing dose of electrons, the stabilizing concentration of electrons, the stabilizing concentration reducing a clamp current variation in the electrostatic clamp to a target value, the target value being less than a second value of clamp current variation when the plasma flood gun is not operating.

Abstract: A method of forming a nonvolatile memory cell includes forming a first electrode and a second electrode of the memory cell. Sacrificial material is provided between the first second electrodes. The sacrificial material is exchanged with programmable material. The sacrificial material may additionally be exchanged with select device material.

Abstract: The present disclosure provides a method for making an integrated circuit in one embodiment. The method includes providing a semiconductor substrate having an active region and a first gate stack disposed on the semiconductor substrate in the active region; forming in-situ phosphorous-doped silicon carbide (SiCP) features on the semiconductor substrate and disposed on sides of the first gate stack; replacing the first gate stack with a second gate stack having a high k dielectric material layer; and thereafter performing a millisecond annealing (MSA) process with a thermal profile having a first thermal wavelet and a second thermal wavelet.

Abstract: In one embodiment of the invention, there is provided a tool for annealing a magnetic stack. The tool includes a housing defining a heating chamber; a holding mechanism to hold at least one wafer in a single line within the heating chamber, a heating mechanism to heat the at least one wafer; and a magnetic field generator to generate a magnetic field whose field lines pass through the single line of wafers during a magnetic annealing process; wherein the holding mechanism comprises a wafer support of holding the single line of wafers between the heating mechanism and the magnetic field generator. The tool may be a rapid thermal processor retrofitted with the magnetic field generator.

Abstract: A method of detecting the circular uniformity of semiconductor circular contact holes. Several detection circuit structures are disposed on the semiconductor wafer: N-type active regions and P-type active regions; silicon dioxide layers separate the N-type active regions from the P-type active regions; the N-type active regions are formed in the P well and the P-type active regions are formed in the N well; polysilicon gates bridge the N-type active regions and the P-type active regions; gate oxide layers insulate the P-type regions and the N-type regions from the polysilicon gates, so that the P-type regions and the N-type regions are independent; the N-type active regions connect with circular contact holes while the P-type active regions and the polysilicon gates connect with oval contact holes; a electron beam scanner detects the circular uniformity of the contact holes. This invention advantageously reflects effectively and comprehensively the circular uniformity of the contact holes.

Abstract: Enhancement-mode GaN devices having a gate spacer, a gate metal material and a gate compound that are self-aligned, and a methods of forming the same. The materials are patterned and etched using a single photo mask, which reduces manufacturing costs. An interface of the gate spacer and the gate compound has lower leakage than the interface of a dielectric film and the gate compound, thereby reducing gate leakage. In addition, an ohmic contact metal layer is used as a field plate to relieve the electric field at a doped III-V gate compound corner towards the drain contact, which leads to lower gate leakage current and improved gate reliability.

Abstract: A salicide process is described. A substrate having thereon an insulating layer and a silicon-based region is provided. A nickel-containing metal layer is formed on the substrate. A first anneal process is performed to form a nickel-rich silicide layer on the silicon-based region. The remaining nickel-containing metal layer is stripped. A thermal recovery process is performed at a temperature of 150-250° C. for a period longer than 5 minutes. A second anneal process is performed to change the phase of the nickel-rich silicide layer and form a low-resistivity mononickel silicide layer.

Abstract: A method of performing rapid thermal annealing on a substrate including heating the substrate to a first temperature in a rapid thermal annealing system having a front-side heating source and a backside heating source. The method further includes raising the temperature of the substrate from the first temperature to a second temperature greater than the first temperature. The backside heating source provides a greater amount of heat than the front-side heating source during the raising of the temperature of the substrate.

Abstract: An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly linear lamps for emitting light energy onto a wafer. The linear lamps can be placed in various configurations. In accordance with the present invention, tuning devices which are used to adjust the overall irradiance distribution of the light energy sources are included in the heating device. The tuning devices can be, for instance, are lamps or lasers.

Abstract: Ions of silicon are implanted into source/drain regions in a semiconductor wafer to amorphize an ion implantation region in the semiconductor wafer. A nickel film is deposited on the amorphized ion implantation region. First irradiation from a flash lamp is performed on the semiconductor wafer with the nickel film deposited thereon to increase the temperature of a front surface of the semiconductor wafer from a preheating temperature to a target temperature for a time period in the range of 1 to 20 milliseconds. Subsequently, second irradiation from the flash lamp is performed to maintain the temperature of the front surface of the semiconductor wafer within a ±25° C. range around the target temperature for a time period in the range of 1 to 100 milliseconds. This causes nickel silicide to grow preferentially in a direction perpendicular to the semiconductor wafer.

Abstract: Methods are provided for fabricating an integrated circuit that includes metal filled narrow openings. In accordance with one embodiment a method includes forming a dummy gate overlying a semiconductor substrate and subsequently removing the dummy gate to form a narrow opening. A layer of high dielectric constant insulator and a layer of work function-determining material are deposited overlying the semiconductor substrate. The layer of work function-determining material is exposed to a nitrogen ambient in a first chamber. A layer of titanium is deposited into the narrow opening in the first chamber in the presence of the nitrogen ambient to cause the first portion of the layer of titanium to be nitrided. The deposition of titanium continues, and the remaining portion of the layer of titanium is deposited as substantially pure titanium. Aluminum is deposited overlying the layer of titanium to fill the narrow opening and to form a gate electrode.

Abstract: A method for fabricating an integrated circuit having a FinFET structure includes providing a semiconductor substrate comprising silicon and a high carrier mobility material, forming one or more fin structures on the semiconductor substrate, and subjecting the substrate to a condensation process for the condensation of the high carrier mobility material. The condensation process results in the formation of condensed fin structures formed substantially entirely of the high carrier mobility material and a layer of silicon oxide formed over the condensed fin structures. The method further includes removing the silicon oxide formed over the condensed fin structures so as to expose the condensed fin structures.

Abstract: A salicide process is described. A substrate having thereon an insulating layer and a silicon-based region is provided. A nickel-containing metal layer is formed on the substrate. A first anneal process is performed to form a nickel-rich silicide layer on the silicon-based region. The remaining nickel-containing metal layer is stripped. A thermal recovery process is performed at a temperature of 150-250° C. for a period longer than 5 minutes. A second anneal process is performed to change the phase of the nickel-rich silicide layer and form a low-resistivity mononickel silicide layer.

Abstract: Systems and methods are disclosed for performing laser annealing in a manner that reduces or minimizes wafer surface temperature variations during the laser annealing process. The systems and methods include annealing the wafer surface with first and second laser beams that represent preheat and anneal laser beams having respective first and second intensities. The preheat laser beam brings the wafer surface temperate close to the annealing temperature and the anneal laser beam brings the wafer surface temperature up to the annealing temperature. The anneal laser beam can have a different wavelength, or the same wavelength but different orientation relative to the wafer surface. Reflectivity maps of the wafer surface at the preheat and anneal wavelengths are measured and used to select first and second intensities that ensure good anneal temperature uniformity as a function of wafer position.

Abstract: Systems and methods are disclosed for performing laser annealing in a manner that reduces or minimizes wafer surface temperature variations during the laser annealing process. The systems and methods include annealing the wafer surface with first and second laser beams that represent preheat and anneal laser beams having respective first and second intensities. The preheat laser beam brings the wafer surface temperate close to the annealing temperature and the anneal laser beam brings the wafer surface temperature up to the annealing temperature. The anneal laser beam can have a different wavelength, or the same wavelength but different orientation relative to the wafer surface. Reflectivity maps of the wafer surface at the preheat and anneal wavelengths are measured and used to select first and second intensities that ensure good anneal temperature uniformity as a function of wafer position.

Abstract: A semiconductor substrate is irradiated with accelerated hydrogen ions, thereby forming a damaged region including a large amount of hydrogen. After a single crystal semiconductor substrate and a supporting substrate are bonded to each other, the semiconductor substrate is heated, so that the single crystal semiconductor substrate is separated in the damaged region. A single crystal semiconductor layer which is separated from the single crystal semiconductor substrate is irradiated with a laser beam. The single crystal semiconductor layer is melted by laser beam irradiation, whereby the single crystal semiconductor layer is recrystallized to recover its crystallinity and to planarized a surface of the single crystal semiconductor layer. After the laser beam irradiation, the single crystal semiconductor layer is heated at a temperature at which the single crystal semiconductor layer is not melted, so that the lifetime of the single crystal semiconductor layer is improved.

Abstract: Some embodiments include methods in which microwave radiation is used to activate dopant and/or increase crystallinity of semiconductor material during formation of a semiconductor construction. In some embodiments, the microwave radiation has a frequency of about 5.8 gigahertz, and a temperature of the semiconductor construction does not exceed about 500° C. during the exposure to the microwave radiation.

Abstract: Some embodiments include methods of processing a unit containing crystalline material. A damage region may be formed within the crystalline material, and a portion of the unit may be above the damage region. A chuck may be used to bend the unit and thereby induce cleavage along the damage region to form a structure from the portion of the unit above the damage region. Some embodiments include methods of forming semiconductor-on-insulator constructions. A unit may be formed to have dielectric material over monocrystalline semiconductor material. A damage region may be formed within the monocrystalline semiconductor material, and a portion of the monocrystalline semiconductor material may be between the damage region and the dielectric material. The unit may be incorporated into an assembly with a handle component, and a chuck may be used to contort the assembly and thereby induce cleavage along the damage region.

Abstract: A method for fabricating metal-oxide semiconductor (MOS) transistor is disclosed. The method includes the steps of: providing a semiconductor substrate having a silicide thereon; performing a first rapid thermal process to drive-in platinum from a surface of the silicide into the silicide; and removing un-reacted platinum in the first rapid thermal process.

Abstract: The present invention generally relates to a thermal processing apparatus and method that permits a user to index one or more preselected light sources capable of emitting one or more wavelengths to a collimator. Multiple light sources may permit a single apparatus to have the capability of emitting multiple, preselected wavelengths. The multiple light sources permit the user to utilize multiple wavelengths simultaneously to approximate “white light”. One or more of a frequency, intensity, and time of exposure may be selected for the wavelength to be emitted. Thus, the capabilities of the apparatus and method are flexible to meet the needs of the user.

Abstract: A substrate processing apparatus includes a process chamber which processes a substrate, a conductive substrate support table which is installed within the process chamber, a dielectric plate on which the substrate is mounted, the dielectric plate being placed on the substrate support table, a microwave generator which is installed outside the process chamber, and a microwave supplying unit which supplies a microwave generated by the microwave generator into the process chamber.

Abstract: Rapid thermal annealing methods and systems for annealing patterned substrates with minimal pattern effect on substrate temperature non-uniformity are provided. The rapid thermal annealing system includes a front-side heating source and a backside heating source. The backside heating source of the rapid thermal annealing system supplies a dominant amount of heat to bring the substrate temperature to the peak annealing temperature. The front-side heating source contributes to heat up the environment near the front-side of the substrate to a temperature lower than about 100° C. to about 200° C. less than the peak annealing temperature. The asymmetric front-side and backside heating for rapid thermal annealing reduce or eliminate pattern effect and improve WIW and WID device performance uniformity.

Abstract: A method for modulating stress in films formed in semiconductor device manufacturing provides for high temperature annealing of an as-deposited compressive film such as titanium nitride. The high temperature annealing converts the initially compressive film to a tensile film without compromising other film qualities and characteristics. The converted tensile films are particularly advantageous as work function adjusting films in PMOS transistor devices and are advantageously used in conjunction with additional metal gate materials.

Abstract: Multi-stage preheat high-temperature anneal processes after the deposition of the gate dielectric layer(s) reduce the number of interfacial sites and improve the negative bias temperature instability (NTBI) performance of a p-type metal-oxide-semiconductor transistor (PMOS). The gate dielectric layers may include an interfacial oxide layer and a high-k dielectric layer. The multi-stage preheat is designed to reduce dopant deactivation and to improve inter-mixing between the interfacial oxide layer and the high-k dielectric layer. The high-temperature anneal is used to reduce the number of interfacial sites at the interface between the silicon substrate and the interfacial oxide layer.

Abstract: The invention relates to a method for bonding two substrates by applying an activation treatment to at least one of the substrates, and performing the contacting step of the two substrates under partial vacuum. Due to the combination of the two steps, it is possible to carry out the bonding and obtain high bonding energy with a reduced number of bonding voids. The invention is in particular applicable to a substrate of processed or at least partially processed devices.

Abstract: thermal management for large scale processing of CIS and/or CIGS based thin film is described. The method includes providing a plurality of substrates, each of the substrates having a copper and indium composite structure. The method also includes transferring the plurality of substrates into a furnace, each of the plurality of substrates provided in a vertical orientation with respect to a direction of gravity, the plurality of substrates being defined by a number N, where N is greater than 5. The method further includes introducing a gaseous species including a selenide species and a carrier gas into the furnace and transferring thermal energy into the furnace to increase a temperature from a first temperature to a second temperature, to at least initiate formation of a copper indium diselenide film.

Abstract: Methods and substrates for laser annealing are disclosed. The substrate includes a target region to be annealed and a plurality of reflective interfaces. The reflective interfaces cause energy received by the substrate to resonate within the target region. The method includes emitting energy toward the substrate with a laser, receiving the energy with the substrate, and reflecting the received energy with a plurality of reflective interfaces embedded in the substrate to generate a resonance within the target region.

Abstract: A method and system for locally processing a predetermined microstructure formed on a substrate without causing undesirable changes in electrical or physical characteristics of the substrate or other structures formed on the substrate are provided. The method includes providing information based on a model of laser pulse interactions with the predetermined microstructure, the substrate and the other structures. At least one characteristic of at least one pulse is determined based on the information. A pulsed laser beam is generated including the at least one pulse. The method further includes irradiating the at least one pulse having the at least one determined characteristic into a spot on the predetermined microstructure. The at least one determined characteristic and other characteristics of the at least one pulse are sufficient to locally process the predetermined microstructure without causing the undesirable changes.

Abstract: Some embodiments include methods in which microwave radiation is used to activate dopant and/or increase crystallinity of semiconductor material during formation of a semiconductor construction. In some embodiments, the microwave radiation has a frequency of about 5.8 gigahertz, and a temperature of the semiconductor construction does not exceed about 500° C. during the exposure to the microwave radiation.

Abstract: An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly linear lamps for emitting light energy onto a wafer. The linear lamps can be placed in various configurations. In accordance with the present invention, tuning devices which are used to adjust the overall irradiance distribution of the light energy sources are included in the heating device. The tuning devices can be, for instance, are lamps or lasers.

Abstract: First irradiation which causes an emission output from a flash lamp to reach its maximum value over a time period in the range of 1 to 20 milliseconds is performed to increase the temperature of a front surface of a semiconductor wafer from a preheating temperature to a target temperature for a time period in the range of 1 to 20 milliseconds. This achieves the activation of the impurities. Subsequently, second irradiation which gradually decreases the emission output from the maximum value over a time period in the range of 3 to 50 milliseconds is performed to maintain the temperature of the front surface within a ±25° C. range around the target temperature for a time period in the range of 3 to 50 milliseconds. This prevents the occurrence of process-induced damage while suppressing the diffusion of the impurities.

Abstract: In a method for removing at least sections of at least one semiconductor layer (4) of a layer stack (1), an optically dense metallisation layer (3) is heated such that the semiconductor layer located on top is detached.

Abstract: The first flash irradiation is performed on a semiconductor wafer preheated to 500° C. to heat a front surface of the semiconductor wafer. Thereafter, the second flash irradiation is performed to reheat the front surface of the semiconductor wafer before the temperature of the front surface of the semiconductor wafer becomes equal to the temperature of a back surface of the semiconductor wafer. Thus, the second flash irradiation is performed before the temperature of the front surface of the semiconductor wafer falls. Even if less energy is consumable by the second flash irradiation, the efficiency of heating of the front surface of the semiconductor wafer resulting from each iteration of the flash irradiation is improved.

Abstract: An object is to suppress a significant change in electrical characteristics of thin film transistors and a deviation thereof from the designed range due to static electricity, and to improve the yield in manufacturing semiconductor devices. In order to prevent a substrate from being charged with static electricity by heat treatment or to favorably reduce static electricity with which a substrate is charged in a manufacturing process of a semiconductor device, heat treatment is performed with a substrate provided with a thin film transistor stored in a conductive container. In addition, a heating apparatus for performing the heat treatment is electrically connected to a ground potential, and the container and the substrate are also electrically connected to the ground potential.

Abstract: A method of forming a device is presented. The method includes providing a wafer having an active surface and dividing the wafer into a plurality of portions. The wafer is selectively processed by localized heating of a first of the plurality of portions. The wafer is then repeatedly selectively processed by localized heating of a next of the plurality of portions until all plurality of portions have been selectively processed.

Abstract: A process for treating a semiconductor-on-insulator structure that has, in succession, a support substrate, a layer of an oxide or oxynitride of a semiconductor material, and a thin semiconductor layer of the semiconductor material. The process includes providing, on the surface of the thin layer, a mask defining exposed regions of the thin layer; providing a layer of nitride or oxynitride of the semiconductor material on the exposed regions of the thin layer; and applying a heat treatment causing at least some of the oxygen in the oxide or oxynitride layer to diffuse through the exposed regions. The nitride or oxynitride layer is provided at a thickness sufficient to provide a ratio of the rate of oxygen diffusion though the exposed regions to that through the regions covered with the mask that is greater than 2.

Abstract: A film deposited on substrate may originally has a high surface recombination velocity (SRV). In order to suppress the SRV and increase the minority carrier lifetime, the substrate may be treated annealing at a high temperature in gas ambient containing O2 or O2?. The substrate may also be treated annealing at a low or mild temperature in gas ambient containing H2 or H+. The process has been found to improve the passivation effect of silicon oxide thin films on a silicon substrate. Further, the process can be achieved using the same production steps normally applied to the solar cell to create its top and bottom metal contacts without additional heating cycles are required.

Abstract: A method that is performed for heat treating a semiconductor wafer in a process chamber, as an intermediate part of an overall multi-step technique for processing the wafer, includes applying an energy transfer layer to at least a portion of the wafer, and exposing the wafer to an energy source in the process chamber in a way which subjects the wafer to a thermal profile such that the energy transfer layer influences at least one part of the thermal profile. The thermal profile has at least a first elevated temperature event. The method further includes, in time relation to the thermal profile, removing the energy transfer layer in the process chamber at least sufficiently for subjecting the wafer to a subsequent step. An associated intermediate condition of the wafer is described.

Abstract: Disclosed is a method of making polysiloxane and polysilsesquioxane based hardmask respond to radiations with positive tone and negative tone simultaneously. Unradiated films are insoluble in developers, showing positivity tone. Radiated films are insoluble in developers as well, showing negative tone. Only half-way radiated films are soluble in developers. The dual-tone photo-imageable hardmask produces splitted patterns. Compositions of dual-tone photo-imageable hardmask based on the chemistry of polysiloxane and polysilsesquioxanes are disclosed as well. Further disclosed are processes of using photo-imageable hardmasks to create precursor structures on semiconductor substrates with or without an intermediate layer.

Abstract: Provided is a manufacturing method for a semiconductor device having reduced leakage current and increased capacitance while improving interface characteristics. The manufacturing method includes forming a silicon oxide layer on a base layer including silicon, forming a silicon oxynitride layer by implanting nitrogen into the silicon oxide layer, and forming hydroxy groups on a surface of the silicon oxynitride layer while etching the silicon oxynitride layer.

Abstract: Systems and methods for microwave annealing are disclosed. In some embodiments, the system may comprise a microwave emitter configured to emit a microwave at a single frequency during an anneal time. In some embodiments, the system may further comprise an anneal unit to be annealed, the anneal unit having a top side, a bottom side, and one or more edge sides. In some embodiments, the system may further comprise a susceptor configured to absorb microwave energy, where the susceptor is adjacent to the edge side and at the bottom side of the anneal unit.

Abstract: The invention is to provide a method for heat treating a silicon wafer reducing grown-in defects while suppressing generation of slip during RTP and improving surface roughness of the wafer. The method performing a first heat treatment while introducing a rare gas, the first heat treatment comprising the steps of rapidly heating the wafer to T1 of 1300° C. or higher and the melting point of silicon or lower, keeping the wafer at T1, rapidly cooling the wafer to T2 of 400-800° C. and keeping the wafer at T2; and performing a second heat treatment while introducing an oxygen gas in an amount of 20-100 vol. %, the second heat treatment comprising the steps of keeping the wafer at T2, rapidly heating the wafer from T2 to T3 of 1250° C. or higher and the melting point of silicon or lower, keeping the wafer at T3 and rapidly cooling the wafer.

Abstract: A laminated semiconductor wafer (10) to be processed is provided with a substrate (110) and a laminated semiconductor layer (100) formed on the substrate (110). The laminated semiconductor wafer (10) is heated to a temperature above the sublimation point of the laminated semiconductor layer (100) and under the melting point of the substrate (110). As a result, in the laminated semiconductor wafer (10), the laminated semiconductor layer (100) sublimes, and the laminated semiconductor layer (100) is eliminated from the substrate (110). In this way, the laminated semiconductor layer is eliminated from the laminated semiconductor wafer while suppressing damage to the substrate.

Abstract: thermal management for large scale processing of CIS and/or CIGS based thin film is described. The method includes providing a plurality of substrates, each of the substrates having a copper and indium composite structure. The method also includes transferring the plurality of substrates into a furnace, each of the plurality of substrates provided in a vertical orientation with respect to a direction of gravity, the plurality of substrates being defined by a number N, where N is greater than 5. The method further includes introducing a gaseous species including a selenide species and a carrier gas into the furnace and transferring thermal energy into the furnace to increase a temperature from a first temperature to a second temperature, to at least initiate formation of a copper indium diselenide film.

Abstract: An approach to activating a getter within a sealed vacuum cavity is disclosed. The approach uses inductive coupling from an external coil to a magnetically permeable material deposited in the vacuum cavity. The getter material is formed over this magnetically permeable material, and heated specifically thereby, leaving the rest of the device cavity and microdevice relatively cool. Using this inductive coupling technique, the getter material can be activated after encapsulation, and delicate structures and low temperature wafer bonding mechanisms may be used.