Using Incoherent Radiation (epo) Patents (Class 257/E21.349)
  • Patent number: 11842908
    Abstract: An arrangement of linear heat lamps is provided which allows for localized control of temperature nonuniformities in a substrate during semiconductor processing. A reactor includes a substrate holder positioned between a top array and a bottom array of linear heat lamps. At least one lamp of the arrays includes a filament having a varying density and power output along the length of the lamp. In particular, at least one lamp of the arrays includes a filament having a higher filament winding density within a central portion of the lamp relative to peripheral portions of the lamp. In some embodiments, the at least one lamp is a central lamp extending across a central portion of the substrate heated by the lamp. Furthermore, at least one lamp of the arrays has a higher power output within a central portion of the lamp than at peripheral portions of the lamp.
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: December 12, 2023
    Assignee: ASM IP Holding B.V.
    Inventors: Shiva K. T. Rajavelu Muralidhar, Sam Kim
  • Patent number: 10103220
    Abstract: An impurity of a second conductivity type is selectively doped in a surface of a semiconductor substrate of a first conductivity type to form doped regions. A portion of a surface of the doped regions is covered by a heat insulating film. At least a remaining portion of the surface of the doped regions is covered by an absorbing film and the doped regions are heated through the absorbing film, enabling an impurity region of the second conductivity type to be formed having two or more of the doped regions that have a same impurity concentration and differing carrier concentrations.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: October 16, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Tomonori Katano, Fumikazu Imai
  • Patent number: 8841152
    Abstract: Method for making a patterned thin film of an organic semiconductor. The method includes condensing a resist gas into a solid film onto a substrate cooled to a temperature below the condensation point of the resist gas. The condensed solid film is heated selectively with a patterned stamp to cause local direct sublimation from solid to vapor of selected portions of the solid film thereby creating a patterned resist film. An organic semiconductor film is coated on the patterned resist film and the patterned resist film is heated to cause it to sublime away and to lift off because of the phase change.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: September 23, 2014
    Assignee: Massachusetts Institute of Technology
    Inventors: Matthias Erhard Bahlke, Marc A. Baldo, Hiroshi Antonio Mendoza
  • Patent number: 8790959
    Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.
    Type: Grant
    Filed: January 21, 2011
    Date of Patent: July 29, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Tatsuya Honda, Norihito Sone
  • Patent number: 8629069
    Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.
    Type: Grant
    Filed: August 1, 2008
    Date of Patent: January 14, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Tatsuya Honda, Norihito Sone
  • Patent number: 8551893
    Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.
    Type: Grant
    Filed: August 1, 2008
    Date of Patent: October 8, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Tatsuya Honda, Norihito Sone
  • Patent number: 8435872
    Abstract: According to one embodiment, in a method for manufacturing a semiconductor device, a surface region of a semiconductor substrate is modified into an amorphous layer. A microwave is irradiated to the semiconductor substrate in which the amorphous layer is formed in a dopant-containing gas atmosphere so as to form a diffusion layer in the semiconductor substrate. The dopant is diffused into the amorphous layer and is activated.
    Type: Grant
    Filed: July 7, 2010
    Date of Patent: May 7, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tomonori Aoyama
  • Patent number: 8316745
    Abstract: Techniques are here disclosed for a solar cell pre-processing method and system for annealing and gettering a solar cell semiconductor wafer having an undesirably high dispersion of transition metals, impurities and other defects. The process forms a surface contaminant layer on the solar cell semiconductor (e.g., silicon) wafer. A surface of the semiconductor wafer receives and holds impurities, as does the surface contaminant layer. The lower-quality semiconductor wafer includes dispersed defects that in an annealing process getter from the semiconductor bulk to form impurity cluster toward the surface contaminant layer. The impurity clusters form within the surface contaminant layer while increasing the purity level in wafer regions from which the dispersed defects gettered. Cooling follows annealing for retaining the impurity clusters and, thereby, maintaining the increased purity level of the semiconductor wafer in regions from which the impurities gettered.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: November 27, 2012
    Assignee: Calisolar Inc.
    Inventors: Fritz G. Kirscht, Kamel Ounadjela, Jean Patrice Rakotoniaina, Dieter Linke
  • Patent number: 8288199
    Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.
    Type: Grant
    Filed: August 1, 2008
    Date of Patent: October 16, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Tatsuya Honda, Norihito Sone
  • Patent number: 8273633
    Abstract: A method of enhancing dopant activation without suffering additional dopant diffusion, includes forming shallow and lightly-doped source/drain extension regions in a semiconductor substrate, performing a first anneal process on the source/drain extension regions, forming deep and heavily-doped source/drain regions in the substrate adjacent to the source/drain extension regions, and performing a second anneal process on source/drain regions. The first anneal process is a flash anneal process performed for a time of between about 1 millisecond and 3 milliseconds, and the second anneal process is a rapid thermal anneal process performed for a time of between about 1 second and 30 seconds.
    Type: Grant
    Filed: March 26, 2007
    Date of Patent: September 25, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Keh-Chiang Kuo, Chien-Hao Chen, Chun-Feng Nieh, Li-Ping Huang, Hsun Chang, Li-Ting Wang, Chih-Chiang Wang, Tze-Liang Lee
  • Patent number: 8013330
    Abstract: Disclosed are a compound for an organic electroluminescent device (organic EL device) which is improved in luminous efficiency, fully secured of driving stability, and of simple constitution and an organic EL device using said compound. The compound for an organic EL device has two indolocarbazole skeletons each of which is bonded to an aromatic group or two skeletons similar thereto. The organic EL device comprises a light-emitting layer disposed between an anode and a cathode piled one upon another on a substrate and said light-emitting layer comprises a phosphorescent dopant and the aforementioned compound for an organic EL device as a host material.
    Type: Grant
    Filed: May 23, 2008
    Date of Patent: September 6, 2011
    Assignee: Nippon Steel Chemical Co., Ltd
    Inventors: Masaki Komori, Toshihiro Yamamoto, Takahiro Kai, Katsuhide Noguchi, Hiroshi Miyazaki
  • Patent number: 8008107
    Abstract: Techniques are here disclosed for a solar cell pre-processing method and system for annealing and gettering a solar cell semiconductor wafer having an undesirably high dispersion of transition metals, impurities and other defects. The process forms a surface contaminant layer on the solar cell semiconductor (e.g., silicon) wafer. A surface of the semiconductor wafer receives and holds impurities, as does the surface contaminant layer. The lower-quality semiconductor wafer includes dispersed defects that in an annealing process getter from the semiconductor bulk to form impurity cluster toward the surface contaminant layer. The impurity clusters form within the surface contaminant layer while increasing the purity level in wafer regions from which the dispersed defects gettered. Cooling follows annealing for retaining the impurity clusters and, thereby, maintaining the increased purity level of the semiconductor wafer in regions from which the impurities gettered.
    Type: Grant
    Filed: December 30, 2006
    Date of Patent: August 30, 2011
    Assignee: Calisolar, Inc.
    Inventors: Fritz Kirscht, Kamel Ounadjela, Jean Patrice Rakotoniana, Dieter Linke
  • Patent number: 8008657
    Abstract: Disclosed are an organic electroluminescent device (organic EL device) which is improved in luminous efficiency, fully secured of driving stability, and of simple constitution and a compound useful for the fabrication of said organic EL device. The compound for the organic EL device has an indolocarbazole structure or a structure similar thereto in the molecule wherein an aromatic group is bonded to the nitrogen atom in the indolocarbazole. The organic EL device has a light-emitting layer disposed between an anode and a cathode piled one upon another on a substrate and said light-emitting layer comprises a phosphorescent dopant and the aforementioned compound for an organic electroluminescent device as a host material.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: August 30, 2011
    Assignee: Nippon Steel Chemical Co., Ltd.
    Inventors: Takahiro Kai, Masaki Komori, Toshihiro Yamamoto, Katsuhide Noguchi, Hiroshi Miyazaki
  • Publication number: 20110014780
    Abstract: A layer including a semiconductor film is formed over a glass substrate and is heated. A thermal expansion coefficient of the glass substrate is greater than 6×10?7/° C. and less than or equal to 38×10?7/° C. The heated layer including the semiconductor film is irradiated with a pulsed ultraviolet laser beam having a width of less than or equal to 100 ?m, a ratio of width to length of 1:500 or more, and a full width at half maximum of the laser beam profile of less than or equal to 50 ?M, so that a crystalline semiconductor film is formed. As the layer including the semiconductor film formed over the glass substrate, a layer whose total stress after heating is ?500 N/m to +50 N/m, inclusive is formed.
    Type: Application
    Filed: September 22, 2010
    Publication date: January 20, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Akihisa SHIMOMURA, Hidekazu MIYAIRI, Yasuhiro JINBO
  • Publication number: 20110008973
    Abstract: In the case of a lens array type homogenizer optical system, the incident angle and intensity of a laser beam 1 entering a large-sized lens (long-axis condenser lens 22) of a long-axis condensing optical system, which is provided on the rear side, are changed for every shot by performing laser irradiation while long-axis lens arrays 20a and 20b are reciprocated in a direction corresponding to a long axial direction of a linear beam (X-direction). Therefore, vertical stripes are significantly reduced. Further, the incident angle and intensity of a laser beam 1 entering a large-sized lens (projection lens 30) of a short-axis condensing optical system, which is provided on the rear side, are changed for every shot by performing laser irradiation while short-axis lens arrays 26a and 26b are reciprocated in a direction corresponding to a short axial direction of a linear beam (Y-direction). Therefore, horizontal stripes are significantly reduced.
    Type: Application
    Filed: May 30, 2008
    Publication date: January 13, 2011
    Applicant: IHI CORPORATION
    Inventors: Norihito Kawaguchi, Ryusuke Kawakami, Kenichiro Nishida, Miyuki Masaki, Masaru Morita
  • Patent number: 7799666
    Abstract: A method utilizing spatially selective laser doping for irradiating predetermined portions of a substrate of a semiconductor material is disclosed. Dopants are deposited onto the surface of a substrate. A pulsed, visible beam is directed to and preferentially absorbed by the substrate only in those regions requiring doping. Spatial modes of the incoherent beam are overlapped and averaged, providing uniform irradiation requiring fewer laser shots. The beam is then focused to the predetermined locations of the substrate for implantation or activation of the dopants. The method provides for scanning and focusing of the beam across the substrate surface, and irradiation of multiple locations using a plurality of beams. The spatial selectivity, combined with visible laser wavelengths, provides greater efficiency in doping only desired substrate regions, while reducing the amount of irradiation required.
    Type: Grant
    Filed: July 27, 2009
    Date of Patent: September 21, 2010
    Assignee: Potomac Photonics, Inc.
    Inventors: Nicholas A. Doudoumopoulos, C. Paul Christensen, Paul Wickboldt
  • Patent number: 7772135
    Abstract: A method for forming a poly-silicon film, using sequential lateral solidification (SLS) by laser irradiation through an optical device to pattern the laser beam and provide a periodic energy profile on the edges of transparent regions so as to widen the poly-silicon grains and achieve grain size uniformity. The optical device comprises a plurality of first transparent regions with a length of L, wherein at least one side of the edge of each of the first transparent regions has a first periodic shape.
    Type: Grant
    Filed: November 20, 2006
    Date of Patent: August 10, 2010
    Assignee: Industrial Technology Research Institute
    Inventors: Fang-Tsun Chu, Jla-Xing Lin
  • Patent number: 7772595
    Abstract: There is provided a method of forming a nitride semiconductor layer, including the steps of firstly providing a substrate on which a patterned epitaxy layer with a pier structure is formed. A protective layer is then formed on the patterned epitaxy layer, exposing a top surface of the pier structure. Next, a nitride semiconductor layer is formed over the patterned epitaxy layer connected to the nitride semiconductor layer through the pier structure, wherein the nitride semiconductor layer, the pier structure, and the patterned epitaxy layer together form a space exposing a bottom surface of the nitride semiconductor layer. Thereafter, a weakening process is performed to remove a portion of the bottom surface of the nitride semiconductor layer and to weaken a connection point between the top surface of the pier structure and the nitride semiconductor layer. Finally, the substrate is separated from the nitride semiconductor layer through the connection point.
    Type: Grant
    Filed: October 31, 2006
    Date of Patent: August 10, 2010
    Assignee: Industrial Technology Research Institute
    Inventors: Yih-Der Guo, Chih-Ming Lai, Jenq-Dar Tsay, Po-Chun Liu
  • Publication number: 20100099239
    Abstract: A method of laser machining a feature in a substrate includes machining the substrate with a pulsed laser along a scan line so that the successive pulses 81 at the substrate do not overlap but are either contiguous or spaced apart. Pulses 82, 83, 84 in respective succeeding scans of the laser along the scan line, are offset with respect to the starting point of pulses 81, 82, 83 in a previous scan so that multiple successive laser scans provide machining to a required depth while successively smoothing edges, 91, 92, 93, 94 of the feature with each pass.
    Type: Application
    Filed: November 27, 2007
    Publication date: April 22, 2010
    Applicant: ELECTRO SCIENTIFIC INDUSTRIES, INC.
    Inventors: Kali Dunne, Cillian O'Briain Fallon
  • Patent number: 7675072
    Abstract: In a light emitting diode, a light-emitting region is including an active layer provided between a first conductivity type cladding layer formed on the semiconductor substrate and a second conductivity type cladding layer. A transparent conductive film made of a metal oxide is located over the light-emitting region. A layer for preventing exfoliation of the transparent conductive film, the preventing layer being made of a compound semiconductor contains at least aluminum and is located between the light-emitting region and the transparent conductive film. The layer for preventing exfoliation of the transparent conductive film contains a conductivity type determining impurity in a concentration of 1×1019 cm?3 or higher.
    Type: Grant
    Filed: December 12, 2007
    Date of Patent: March 9, 2010
    Assignee: Hitachi Cable, Ltd.
    Inventors: Taichiroo Konno, Masahiro Arai
  • Patent number: 7674650
    Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.
    Type: Grant
    Filed: September 21, 2006
    Date of Patent: March 9, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Tatsuya Honda, Norihito Sone
  • Patent number: 7649193
    Abstract: A semiconductor body (2), comprising a semiconductor layer sequence with an active region (3) suitable for generating radiation. The semiconductor layer sequence comprises two contact layers (6, 7), between which the active region is arranged. The contact layers are assigned a respective connection layer (12, 13) arranged on the semiconductor body. The respective connection layer is electrically conductively connected to the assigned contact layer. The respective connection layer is arranged on that side of the assigned contact layer which is remote from the active region. The connection layers are transmissive to the radiation to be generated in the active region, and the contact layers are of the same conduction type.
    Type: Grant
    Filed: September 26, 2007
    Date of Patent: January 19, 2010
    Assignee: Osram Opto Semiconductors GmbH
    Inventor: Ralph Wirth
  • Publication number: 20090227119
    Abstract: A method of curing a low dielectric constant (low-k) dielectric film on a substrate is described, wherein the dielectric constant of the low-k dielectric film is less than a value of approximately 4. The method comprises exposing the low-k dielectric film to infrared (IR) radiation and ultraviolet (UV) radiation.
    Type: Application
    Filed: March 6, 2008
    Publication date: September 10, 2009
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Junjun Liu, Dorel I. Toma, Eric M. Lee
  • Publication number: 20090191693
    Abstract: A method of processing a wafer having a plurality of devices which are composed of a laminate consisting of an insulating film and a functional film laminated on the front surface of a substrate, along streets for sectioning the plurality of devices, comprising a first trip blocking groove forming step for activating a first laser beam application means to form a blocking groove for dividing the laminate along a street of the wafer while moving the chuck table in a first direction in the processing-feed direction; a second trip blocking groove and dividing groove forming step for activating the first laser beam application means to form a blocking groove for dividing the laminate along a street next to the street which has undergone the first trip blocking groove forming step and also to form a dividing groove along the blocking groove formed by the first trip blocking groove forming step while moving the chuck table in a second direction in the processing-feed direction; and a first trip blocking groove and
    Type: Application
    Filed: January 23, 2009
    Publication date: July 30, 2009
    Applicant: Disco Corporation
    Inventor: Kentaro Iizuka
  • Publication number: 20090156018
    Abstract: A crystallization method includes providing a substrate having a silicon thin film; positioning a laser mask having first to fourth blocks on the substrate, each block having a periodic pattern including a plurality of transmitting regions and a blocking region; and crystallizing the silicon thin film by irradiating a laser beam through the laser mask. A polycrystalline silicon film crystallized by this method is substantially free from a shot mark, and has uniform crystalline characteristics.
    Type: Application
    Filed: February 9, 2009
    Publication date: June 18, 2009
    Inventor: JaeSung You
  • Publication number: 20090156019
    Abstract: A substrate processing apparatus is used for radiating UV rays onto a target film formed on a target surface of a substrate to perform a curing process of the target film. The apparatus includes a hot plate configured to heat the substrate to a predetermined temperature, a plurality of support pins disposed on the hot plate to support the substrate, and a UV radiating device configured to radiate UV rays onto the target surface of the substrate supported on the support pins. The support pins are preset to provide a predetermined thermal conductivity to conduct heat of the substrate to the hot plate. The hot plate is preset to have a predetermined thermal capacity sufficient to absorb heat conducted through the support pins.
    Type: Application
    Filed: June 4, 2008
    Publication date: June 18, 2009
    Inventors: Naoyuki Satoh, Takeshi Tamura, Hiroyuki Ide, Manabu Hama
  • Publication number: 20090148975
    Abstract: A method of manufacturing a nitride semiconductor device includes: a working region forming step of forming a working region in a group III nitride semiconductor substrate by converging a laser beam having a wavelength of 500 nm to 700 nm in the group III nitride semiconductor substrate and by scanning a convergent point of the laser beam in a prescribed scanning direction in the interior of the group III nitride semiconductor substrate; and a dividing step of dividing the group III nitride semiconductor substrate by generating a crack from the working region without processing a surface of the group III nitride semiconductor substrate.
    Type: Application
    Filed: March 26, 2008
    Publication date: June 11, 2009
    Applicant: ROHM CO., LTD.
    Inventor: Shinichi Kohda
  • Publication number: 20080305609
    Abstract: A method for fabricating a seamless shallow trench isolation includes providing a semiconductor substrate having at least a shallow trench that is filled by a dielectric layer with a seam, forming a dielectric layer filling the shallow trench with a seam, forming at least one healing layer on the dielectric layer, and performing a low-temperature steam annealing process to eliminate the seam.
    Type: Application
    Filed: June 6, 2007
    Publication date: December 11, 2008
    Inventor: Hui-Shen Shih
  • Publication number: 20080194064
    Abstract: A method for programming a laser fuse. The laser fuse has a fuse link including a material having a characteristic of changing its electrical resistance after being exposed to a laser beam. The laser beam is directed to the fuse link, the laser beam being controlled such that, in response to the impact of the laser beam upon the fuse link, the electrical resistance of the fuse link changes but the fuse link is not blown off.
    Type: Application
    Filed: April 18, 2008
    Publication date: August 14, 2008
    Inventors: Dinesh A. Badami, Tom C. Lee, Baozhen Li, Gerald Matusiewicz, William T. Motsiff, Christopher D. Muzzy, Kimball M. Watson, Jean E. Wynne
  • Patent number: 7300832
    Abstract: A method of semiconductor device manufacture provided includes forming a gate insulating layer upon a single crystal semiconductor substrate, forming a gate electrode made from a polycrystal conductive film upon the gate insulating layer, implanting impurity in the gate electrode and in the surface layer of the semiconductor substrate adjacent to or separate from the gate electrode, performing a first heat treatment, and performing a second heat treatment. The first heat treatment performs heat treatment at a temperature that diffuses the impurity implanted mainly in the gate electrode and controls the diffusion of the impurity implanted in the surface layer of the semiconductor substrate. The second heat treatment performs heat treatment at a higher temperature and for a shorter time than the first heat treatment, and at a temperature that activates the impurity implanted in the semiconductor substrate.
    Type: Grant
    Filed: June 16, 2004
    Date of Patent: November 27, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takayuki Ito, Kyoichi Suguro