Zener Diode (epo) Patents (Class 257/E21.356)
-
Patent number: 8975661Abstract: An asymmetrical bidirectional protection component formed in a semiconductor substrate of a first conductivity type, including: a first implanted area of the first conductivity type; a first epitaxial layer of the second conductivity type on the substrate and the first implanted area; a second epitaxial layer of the second conductivity type on the first epitaxial layer, the second layer having a doping level different from that of the first layer; a second area of the first conductivity type on the outer surface of the epitaxial layer, opposite to the first area; a first metallization covering the entire lower surface of the substrate; and a second metallization covering the second area.Type: GrantFiled: August 16, 2011Date of Patent: March 10, 2015Assignee: STMicroelectronics (Tours) SASInventor: Benjamin Morillon
-
Patent number: 8829548Abstract: A light emitting device package includes: an undoped semiconductor substrate having first and second surfaces opposed to each other; first and second conductive vias penetrating the undoped semiconductor substrate; a light emitting device mounted on one region of the first surface; a bi-directional Zener diode formed by doping an impurity on the second surface of the undoped semiconductor substrate and having a Zener breakdown voltage in both directions; and first and second external electrodes formed on the second surface of the undoped semiconductor substrate such that they connect the first and second conductive vias to both ends of the bi-directional Zener diode region, respectively.Type: GrantFiled: July 20, 2012Date of Patent: September 9, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jong In Yang, Sung Tae Kim, Yong Il Kim, Su Yeol Lee, Seung Wan Chae, Hyung Duk Ko, Yung Ho Ryu
-
Patent number: 8664728Abstract: A transistor includes a substrate, a well formed in the substrate, a drain including a first impurity region implanted in the well, a source including a second impurity region implanted in the well and spaced apart from the first impurity region, a channel for current flow from the drain to the source, and a gate to control a depletion region between the source and the drain The channel has an intrinsic breakdown voltage, and the well, drain and source are configured to provide an extrinsic breakdown voltage lower than the intrinsic breakdown voltage and such that breakdown occurs in a breakdown region in the well located outside the channel and adjacent the drain or the source.Type: GrantFiled: January 14, 2009Date of Patent: March 4, 2014Assignee: Volterra Semiconductor CorporationInventors: Yang Lu, Budong You, Marco A. Zuniga, Hamza Yilmaz
-
Patent number: 8492866Abstract: Disclosed is a Zener diode having a scalable reverse-bias breakdown voltage (Vb) as a function of the position of a cathode contact region relative to the interface between adjacent cathode and anode well regions. Specifically, cathode and anode contact regions are positioned adjacent to corresponding cathode and anode well regions and are further separated by an isolation region. However, while the anode contact region is contained entirely within the anode well region, one end of the cathode contact region extends laterally into the anode well region. The length of this end can be predetermined in order to selectively adjust the Vb of the diode (e.g., increasing the length reduces Vb of the diode and vice versa). Also disclosed are an integrated circuit, incorporating multiple instances of the diode with different reverse-bias breakdown voltages, a method of forming the diode and a design structure for the diode.Type: GrantFiled: January 9, 2012Date of Patent: July 23, 2013Assignee: International Business Machines CorporationInventors: Frederick G. Anderson, Natalie B. Feilchenfeld, David L. Harmon, Richard A. Phelps, Yun Shi, Michael J. Zierak
-
Publication number: 20130175670Abstract: An exemplary embodiment illustrates a zener diode structure, wherein the zener diode structure includes a first-type semiconductor layer, a second-type semiconductor layer, a first electrode, a second electrode, and an insulation layer. The second-type semiconductor layer is disposed in a designated area in the first-type semiconductor layer. The first electrode is disposed on the bottom side of the first-type semiconductor layer. The second electrode is disposed above the first-type and the second-type semiconductor layers in corresponding to the central area of the second-type semiconductor layer. The insulation layer is disposed above the first-type and the second-type semiconductor layers surrounding the second electrode. The disclosed zener structure having the insulation layer can reduce the short circuit issue resulting from overflow of an adhesive material during the zener diode packaging process.Type: ApplicationFiled: July 6, 2012Publication date: July 11, 2013Applicant: LEXTAR ELECTRONICS CORP.Inventor: FU-SIN CHEN
-
Patent number: 8435853Abstract: A method for forming a field effect power semiconductor is provided. The method includes providing a semiconductor body, a conductive region arranged next to a main surface of the semiconductor body, and an insulating layer arranged on the main horizontal surface. A narrow trench is etched through the insulating layer to expose the conductive region. A polycrystalline semiconductor layer is deposited and a vertical poly-diode structure is formed. The polycrystalline semiconductor layer has a minimum vertical thickness of at least half of the maximum horizontal extension of the narrow trench. A polycrystalline region which forms at least a part of a vertical poly-diode structure is formed in the narrow trench by maskless back-etching of the polycrystalline semiconductor layer. Further, a semiconductor device with a trench poly-diode is provided.Type: GrantFiled: August 30, 2010Date of Patent: May 7, 2013Assignee: Infineon Technologies AGInventors: Franz Hirler, Anton Mauder, Frank Pfirsch, Hans-Joachim Schulze
-
Patent number: 8431959Abstract: In one embodiment, a bi-directional ESD device is formed to have a third harmonic at frequencies no less than about one gigahertz wherein the third harmonic has a magnitude that is no greater than about minus thirty five dBm.Type: GrantFiled: October 19, 2010Date of Patent: April 30, 2013Assignee: Semiconductor Components Industries, LLCInventors: T. Jordan Davis, Ali Salih
-
Patent number: 8415765Abstract: A semiconductor device including a semiconductor substrate having a first conductive type layer; a first diffusion region which has the first conductive type and is formed in the first conductive type layer; a second diffusion region which has a second conductive type and an area larger than an area of the first diffusion region and overlaps the first diffusion region; and a PN junction formed at an interface between the first and the second diffusion regions. The second diffusion region includes a ring shaped structure or a guard ring includes an inverted region which has the second conductive type. According to such a configuration, it is possible to provide a semiconductor device having the required Zener characteristics with good controllability.Type: GrantFiled: February 17, 2010Date of Patent: April 9, 2013Assignee: Panasonic CorporationInventors: Atsuya Masada, Mitsuo Horie
-
Patent number: 8389354Abstract: A method for operating a semiconductor power device by in a forward conducting mode instead of an avalanche mode during a voltage fly-back during an inductive switch operation for absorbing a transient energy with less stress. The method includes a step of clamping the semiconductor power device with a Zener diode connected between a gate metal and a drain metal of the semiconductor power device to function as a gate-drain (GD) clamp diode with the GD clamp diode having an avalanche voltage lower than a source/drain avalanche voltage of the semiconductor power device whereby as the voltage fly-back inducing a drain voltage increase rapidly reaching the avalanche voltage of the GD clamp diode for generating the forward conducting mode.Type: GrantFiled: March 19, 2009Date of Patent: March 5, 2013Assignee: Force-MOS Technology CorporationInventor: Fwu-Iuan Hshieh
-
Patent number: 8377757Abstract: A transient voltage suppressor (TVS) device includes a semiconductor substrate of a first conductivity type, and a first and a second semiconductor regions of a second conductivity type overlying the semiconductor substrate. A semiconductor layer of the second conductivity type overlies the first and the second semiconductor regions. The TVS device has a first trench extending through the semiconductor layer and the first semiconductor region and into the semiconductor substrate, and a fill material of the second conductivity type disposed in the first trench. A clamping diode in the TVS device has a junction between an out-diffused region from the fill material and a portion of the semiconductor substrate. The TVS device also includes a first P-N diode formed in a first portion of the semiconductor layer, and a second P-N diode having a junction between the second semiconductor region and the semiconductor substrate.Type: GrantFiled: April 30, 2010Date of Patent: February 19, 2013Assignee: Shanghai SIM-BCD Semiconductor Manufacturing LimitedInventors: Francis Edward Hawe, Jinsui Liang, Xiaoqiang Cheng, Xianfeng Liu
-
Patent number: 8252656Abstract: Electrostatic discharge (ESD) protection clamps (61, 95) for I/O terminals (22, 23) of integrated circuit (IC) cores (24) comprise a bipolar transistor (25) with an integrated Zener diode (30) coupled between the base (28) and collector (27) of the transistor (25). Prior art variations (311, 312, 313, 314) in clamp voltage in different parts of the same IC chip or wafer caused by prior art deep implant geometric mask shadowing are avoided by using shallow implants (781, 782) and forming the base (28, 68) coupled anode (301, 75) and collector (27, 70, 64) coupled cathode (302, 72) of the Zener (30) using opposed edges (713, 714) of a single relatively thin mask (71, 71?). The anode (301, 75) and cathode (302, 72) are self-aligned and the width (691) of the Zener space charge region (69) therebetween is defined by the opposed edges (713, 714) substantially independent of location and orientation of the ESD clamps (61, 95) on the die or wafer.Type: GrantFiled: March 31, 2009Date of Patent: August 28, 2012Assignee: Freescale Semiconductor, Inc.Inventors: James D. Whitfield, Changsoo Hong
-
Patent number: 8236625Abstract: In one embodiment, a two terminal multi-channel ESD device is configured to include a zener diode and a plurality of P-N diodes. In another embodiment, the ESD devices has an asymmetrical, characteristic.Type: GrantFiled: November 17, 2011Date of Patent: August 7, 2012Assignee: Semiconductor Components Industries, LLCInventors: Ali Salih, Mingjiao Liu
-
Patent number: 8222115Abstract: In one embodiment, high doped semiconductor channels are formed in a semiconductor region of an opposite conductivity type to increase the capacitance of the device.Type: GrantFiled: February 16, 2012Date of Patent: July 17, 2012Assignee: Semiconductor Components Industries, LLCInventors: David D. Marreiro, Sudhama C. Shastri, Gordon M. Grivna, Earl D. Fuchs
-
Patent number: 8217419Abstract: Provided is a semiconductor device in which on-resistance is largely reduced. In a region (2a) of an N type epitaxial layer (2) of the semiconductor device 20, each region between neighboring trenches (3) is blocked with a depletion layer (14) formed around a trench (3) so that a current passage (12) is interrupted, while a part of the depletion layer (14) formed around the trench (3) is deleted so that the current passage (12) is opened. In a region (2b), a junction portion (8) between the N type epitaxial layer (2) and a P+ type diffusion region (7) makes a Zener diode (8).Type: GrantFiled: June 13, 2008Date of Patent: July 10, 2012Assignee: Rohm Co., Ltd.Inventor: Masaru Takaishi
-
Publication number: 20120091504Abstract: In one embodiment, a bi-directional ESD device is formed to have a third harmonic at frequencies no less than about one gigahertz wherein the third harmonic has a magnitude that is no greater than about minus thirty five dBm.Type: ApplicationFiled: October 19, 2010Publication date: April 19, 2012Inventors: T. Jordan Davis, Ali Salih
-
Patent number: 8143701Abstract: In one embodiment, high doped semiconductor channels are formed in a semiconductor region of an opposite conductivity type to increase the capacitance of the device.Type: GrantFiled: December 3, 2009Date of Patent: March 27, 2012Assignee: Semiconductor Components Industries, LLCInventors: David D. Marreiro, Sudhama C. Shastri, Gordon M. Grivna, Earl D. Fuchs
-
Patent number: 8089095Abstract: In one embodiment, a two terminal multi-channel ESD device is configured to include a zener diode and a plurality of P-N diodes. In another embodiment, the ESD devices has an asymmetrical characteristic.Type: GrantFiled: August 20, 2010Date of Patent: January 3, 2012Assignee: Semiconductor Components Industries, LLCInventors: Ali Salih, Mingjiao Liu
-
Publication number: 20110309476Abstract: In a semiconductor device including a protection diode for preventing electrostatic breakdown employing a low capacitance protection diode, an occupation area of a Zener diode as a voltage limiting element is not needed on a front surface of a semiconductor substrate. A P+ type embedded diffusion layer is formed in a P+ type semiconductor substrate. This is then covered by a non-doped first epitaxial layer. A high resistivity N type second epitaxial layer is then formed on the first epitaxial layer. The second epitaxial layer is divided by a P+ isolation layer into a first protection diode forming region and a second protection diode forming region. An N+ type embedded layer extending from the front surface of the first epitaxial layer of the first protection diode forming region to the first epitaxial layer and the second epitaxial layer, and so on are then formed. A Zener diode is formed by a P+ type upward diffusion layer extending from the P+ type embedded diffusion layer and the N+ type embedded layer.Type: ApplicationFiled: June 14, 2011Publication date: December 22, 2011Applicant: ON Semiconductor Trading, Ltd.Inventors: Keiji MITA, Kentaro Ooka
-
Patent number: 8053808Abstract: A semiconductor power device supported on a semiconductor substrate includes a plurality of transistor cells each having a source and a drain with a gate to control an electric current transmitted between the source and the drain. The semiconductor further includes a source metal connected to the source region, and a gate metal configured as a metal stripe surrounding a peripheral region of the substrate connected to a gate pad wherein the gate metal and the gate pad are separated from the source metal by a metal gap. The semiconductor power device further includes an ESD protection circuit includes a plurality of doped polysilicon regions of opposite conductivity types constituting ESD diodes extending across the metal gap and connected between the gate metal and the source metal on the peripheral region of the substrate.Type: GrantFiled: May 21, 2007Date of Patent: November 8, 2011Assignee: Alpha & Omega Semiconductor, Ltd.Inventors: Yi Su, Anup Bhalla, Daniel Ng, Wei Wang, Ji Pan
-
Publication number: 20110266650Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate, a first conductivity type region, a device isolation insulating film, a second conductivity type region, and a low concentration region. The first conductivity type region is formed in part of the semiconductor substrate. The device isolation insulating film is formed in an upper surface of the semiconductor substrate and includes an opening formed in part of an immediately overlying region of the first conductivity type region. The second conductivity type region is formed in the opening and is in contact with the first conductivity type region. The low concentration region is formed along a side surface of the opening, has second conductivity type, has an effective impurity concentration lower than an effective impurity concentration of the second conductivity type region, and separates an interface of the first conductivity type region and the second conductivity type region from the device isolation insulating film.Type: ApplicationFiled: March 10, 2011Publication date: November 3, 2011Applicant: Kabushiki Kaisha ToshibaInventor: Kazuaki YAMAURA
-
Publication number: 20110266592Abstract: A transient voltage suppressor (TVS) device includes a semiconductor substrate of a first conductivity type, and a first and a second semiconductor regions of a second conductivity type overlying the semiconductor substrate. A semiconductor layer of the second conductivity type overlies the first and the second semiconductor regions. The TVS device has a first trench extending through the semiconductor layer and the first semiconductor region and into the semiconductor substrate, and a fill material of the second conductivity type disposed in the first trench. A clamping diode in the TVS device has a junction between an out-diffused region from the fill material and a portion of the semiconductor substrate. The TVS device also includes a first P-N diode formed in a first portion of the semiconductor layer, and a second P-N diode having a junction between the second semiconductor region and the semiconductor substrate.Type: ApplicationFiled: April 30, 2010Publication date: November 3, 2011Inventors: Francis Edward Hawe, Jinsui Liang, Xiaoqiang Cheng, Xianfeng Liu
-
Patent number: 8012842Abstract: An integrated semiconductor structure that has first and second bipolar transistor structures. The first bipolar transistor structure has a doped tank region in contact with a doped tank region located underneath a contacting sinker. The second bipolar transistor structure has a doped buried region that is the same dopant type as its doped tank region. A method for fabricating an integrated semiconductor structure in a bulk semiconductor wafer. A first patterned photomask is used to form a doped buried region and a doped tank region within the first bipolar transistor structure. A second patterned photomask is used to form a doped buried region and a doped tank region within the second bipolar transistor, plus a doped buried region and a doped tank region underneath a contacting sinker adjacent to the first bipolar transistor.Type: GrantFiled: June 12, 2008Date of Patent: September 6, 2011Assignee: Texas Instruments IncorporatedInventors: Scott Balster, Badih El-Kareh, Hiroshi Yasuda
-
Patent number: 8003478Abstract: In one embodiment, a bi-directional diode structure is formed to have a substantially symmetrical current-voltage characteristic.Type: GrantFiled: June 6, 2008Date of Patent: August 23, 2011Assignee: Semiconductor Components Industries, LLCInventors: Mark Duskin, Suem Ping Loo, Ali Salih
-
Patent number: 7910411Abstract: A semiconductor device includes a semiconductor substrate, a cell region, an outer peripheral region, a field plate, an outermost peripheral ring, outer peripheral region layer, an insulator film, and a Zener diode. The semiconductor substrate has a superjunction structure. The outer peripheral region is disposed at an outer periphery of the cell region. The Zener diode is disposed on the insulator film for electrically connecting the field plate with the outermost peripheral ring. The Zener diode has a first conductivity type region and a second conductivity type region that are alternately arranged in a direction from the cell region to the outer peripheral region.Type: GrantFiled: January 3, 2008Date of Patent: March 22, 2011Assignee: DENSO CORPORATIONInventor: Takeshi Miyajima
-
Publication number: 20100321840Abstract: A low voltage transient voltage suppressing (TVS) device supported on a semiconductor substrate supporting an epitaxial layer thereon. The TVS device further includes a bottom-source metal oxide semiconductor field effect transistor (BS-MOSFET) comprises a trench gate surrounded by a drain region encompassed in a body region disposed near a top surface of the semiconductor substrate wherein the drain region interfaces with the body region constituting a junction diode and the drain region encompassed in the body region on top of the epitaxial layer constituting a bipolar transistor with a top electrode disposed on the top surface of the semiconductor functioning as a drain/collector terminal and a bottom electrode disposed on a bottom surface of the semiconductor substrate functioning as a source/emitter electrode.Type: ApplicationFiled: June 17, 2009Publication date: December 23, 2010Inventor: Madhur Bobde
-
Patent number: 7812367Abstract: In one embodiment, a two terminal multi-channel ESD device is configured to include a zener diode and a plurality of P-N diodes.Type: GrantFiled: October 15, 2008Date of Patent: October 12, 2010Assignee: Semiconductor Components Industries, LLCInventors: Ali Salih, Mingjiao Liu, Thomas Keena
-
Publication number: 20100252912Abstract: A method of manufacturing a semiconductor device, comprising the steps of preparing a structure including a semiconductor substrate, an element formed therein, a through hole formed to penetrate the semiconductor substrate, and an insulating layer formed on both surface sides of the semiconductor substrate and an inner surface of the through hole, and covering the element, forming a penetrating electrode in the through hole, forming a first barrier metal pattern layer covering the penetrating electrode, forming a contact hole reaching a connection portion of the element in the insulating layer, removing a natural oxide film on the connection portion of the element in the contact hole, and forming a wiring layer connected to the first barrier metal pattern layer and connected to the element through the contact hole.Type: ApplicationFiled: April 1, 2010Publication date: October 7, 2010Applicant: Shinko Electric Industries Co., Ltd.Inventor: Kei MURAYAMA
-
Patent number: 7666751Abstract: In one embodiment, high doped semiconductor channels are formed in a semiconductor region of an opposite conductivity type to increase the capacitance of the device.Type: GrantFiled: September 21, 2007Date of Patent: February 23, 2010Assignee: Semiconductor Components Industries, LLCInventors: David D. Marreiro, Sudhama C. Shastri, Gordon M. Grivna, Earl D. Fuchs
-
Publication number: 20090302424Abstract: In one embodiment, a bi-directional diode structure is formed to have a substantially symmetrical current-voltage characteristic.Type: ApplicationFiled: June 6, 2008Publication date: December 10, 2009Inventors: Mark Duskin, Suem Ping Loo, Ali Salih
-
Patent number: 7612431Abstract: Embodiments of the present invention include a method of manufacturing a trench transistor. The method includes forming a substrate of a first conductivity type and implanting a dopant of a second conductivity type, forming a body region of the substrate. The method further includes forming a trench in the body region and depositing an insulating layer in the trench and over the body region wherein the insulating layer lines the trench. The method further includes filling the trench with polysilicon forming a top surface of the trench and forming a diode in the body region wherein a portion of the diode is lower than the top surface of the trench.Type: GrantFiled: January 17, 2008Date of Patent: November 3, 2009Assignee: Vishay-SiliconixInventors: Qufei Chen, Robert Xu, Kyle Terrill, Deva Pattanayak
-
Patent number: 7564101Abstract: A semiconductor device includes a Zener diode connected between an outside terminal and ground, and a resistor connected to the Zener diode in series. The Zener diode and the resistor divide a noise voltage, so that the semiconductor device can have the high noise tolerance even if it uses the small Zener diode.Type: GrantFiled: August 23, 2005Date of Patent: July 21, 2009Assignee: DENSO CORPORATIONInventors: Yasuhiro Yamashita, Tadashi Kunou
-
Patent number: 7554157Abstract: An SOI semiconductor component comprises a semiconductor substrate having a basic doping, a dielectric layer arranged on the semiconductor substrate, and a semiconductor layer arranged on the dielectric layer. The semiconductor layer includes a drift zone of a first conduction type, a junction between the drift zone and a further component zone which is configured in such a way that a space charge zone is formed in the drift zone when a reverse voltage is applied to the junction, and a terminal zone adjacent to the drift zone. A first terminal electrode is connected to the further component zone, and a second terminal electrode is connected to the terminal zone. In the semiconductor substrate a first semiconductor zone is doped complementarily with respect to a basic doping of the semiconductor substrate, and the first terminal electrode is connected to the first semiconductor zone. A rectifier element is connected between the first terminal electrode and the first semiconductor zone.Type: GrantFiled: September 26, 2006Date of Patent: June 30, 2009Assignee: Infineon Technologies Austria AGInventors: Uwe Wahl, Ralf Rudolf, Dirk Priefert
-
Patent number: 7544545Abstract: Embodiments of the present invention include a method of manufacturing a trench polysilicon diode. The method includes forming a N?(P?) type epitaxial region on a N+(P+) type substrate and forming a trench in the N?(P?) type epitaxial region. The method further includes forming a insulating layer in the trench and filling the trench with polysilicon forming a top surface of the trench. The method further includes forming P+(N+) type doped polysilicon region and N+(P+) type doped polysilicon region in the trench and forming a diode in the trench wherein a portion of the diode is lower than the top surface of the trench.Type: GrantFiled: December 28, 2005Date of Patent: June 9, 2009Assignee: Vishay-SiliconixInventors: Qufei Chen, Robert Xu, Kyle Terrill, Deva Pattanayak
-
Publication number: 20090140333Abstract: A method and device structure are disclosed for preventing gate oxide damage of a trench MOSFET during wafer processing while adding an ESD protection module atop the trench MOSFET. The ESD protection module has a low temperature oxide (LTO) bottom layer whose patterning process is found to cause the gate oxide damage. The method includes: a) Fabricate numerous trench MOSFETs on a wafer. b) Add a Si3N4 isolation layer, capable of preventing the LTO patterning process from damaging the gate oxide, atop the wafer. c) Add numerous ESD protection modules atop the Si3N4 isolation layer. d) Remove those portions of the Si3N4 isolation layer that are not beneath the ESD protection modules. In one embodiment, hydrofluoric acid is used as a first etchant for patterning the LTO while hot phosphoric acid is used as a second etchant for removing portions of the Si3N4 isolation layer.Type: ApplicationFiled: November 29, 2007Publication date: June 4, 2009Inventors: Mengyu Pan, Zengyi He, Kaiyu Chen
-
Publication number: 20090079022Abstract: In one embodiment, the ESD device uses highly doped P and N regions deep within the ESD device to form a zener diode that has a controlled breakdown voltage.Type: ApplicationFiled: September 21, 2007Publication date: March 26, 2009Inventors: Thomas Keena, Ki Chang, Francine Y. Robb, Mingjiao Liu, Ali Salih, John Michael Parsey, JR., George Chang
-
Patent number: 7419883Abstract: A method for fabricating a semiconductor structure having selective dopant regions in a semiconductor substrate having trenches formed therein I disclosed. In one embodiment, by a dopant source of an auxiliary structure, parts of the semiconductor structure which lie within the trenches are doped by means of a drive-in. In one embodiment, the semiconductor structure is patterned in planar regions outside the trenches and selectively doped by an implantation process.Type: GrantFiled: August 22, 2006Date of Patent: September 2, 2008Assignee: Infineon Technologies Austria AGInventors: Nicola Vannucci, Sven Lanzerstorfer
-
Publication number: 20080173935Abstract: A semiconductor device includes a semiconductor substrate, a cell region, an outer peripheral region, a field plate, an outermost peripheral ring, outer peripheral region layer, an insulator film, and a Zener diode. The semiconductor substrate has a superjunction structure. The outer peripheral region is disposed at an outer periphery of the cell region. The Zener diode is disposed on the insulator film for electrically connecting the field plate with the outermost peripheral ring. The Zener diode has a first conductivity type region and a second conductivity type region that are alternately arranged in a direction from the cell region to the outer peripheral region.Type: ApplicationFiled: January 3, 2008Publication date: July 24, 2008Applicant: DENSO CORPORATIONInventor: Takeshi Miyajima
-
Patent number: 7358194Abstract: A method is provided for forming a Si film in sequential deposition process. The method includes providing a substrate in a process chamber, forming a chlorinated Si film by exposing the substrate to a chlorinated silane gas, and dry etching the chlorinated Si film to reduce the chlorine content of the Si film. The Si film may be deposited selectively or non-selectively on the substrate and the deposition may be self-limiting or non-self-limiting. Other embodiments provide a method for forming SiGe films in a sequential deposition process.Type: GrantFiled: August 18, 2005Date of Patent: April 15, 2008Assignee: Tokyo Electron LimitedInventors: Anthony Dip, Allen John Leith, Seungho Oh
-
Patent number: 7279773Abstract: A protection device for handling energy transients includes a plurality of basic unit Zener diodes connected in series to achieve a desired breakdown voltage. Each of the basic unit Zener diodes is formed in a first-type substrate. Each of the basic unit Zener diodes comprises a second-type well formed in the substrate, a second-type Zener region formed in the second-type well and a first-type+ region formed over the second-type Zener region between a first and second second-type+ region.Type: GrantFiled: March 15, 2005Date of Patent: October 9, 2007Assignee: Delphi Technologies, Inc.Inventors: Jack L. Glenn, Troy D. Clear, Mark W. Gose, John M. Dikeman