Capacitor With Pn - Or Schottky Junction, E.g., Varactor (epo) Patents (Class 257/E21.364)
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Patent number: 7629668Abstract: The electrode of a thin-type capacitor is connected to the rear surface of a p-type semiconductor substrate which is brought to a ground potential, by a conductive DAF (Die Attach Film) or by a conductive adhesive, and the electrodes of the front surface of the p-type semiconductor substrate are respectively connected with and stacked on the terminals of a thin-type inductor by bumps, whereby manufacturing costs can be reduced while the occurrence of noise can be suppressed and packaging area can be made small.Type: GrantFiled: March 28, 2008Date of Patent: December 8, 2009Assignee: Fuji Electric Technology Co., Ltd.Inventors: Jun Yabuzaki, Takeshi Yokoyama, Tomonori Seki
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Publication number: 20090289329Abstract: A high-Q differential varactor includes reduced inner spacing dimensions between differential fingers.Type: ApplicationFiled: May 20, 2008Publication date: November 26, 2009Applicant: ATMEL CORPORATIONInventors: Adam H. Pawlikiewicz, Samir El Rai
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Publication number: 20090250739Abstract: Device structures with hyper-abrupt p-n junctions, methods of forming hyper-abrupt p-n junctions, and design structures for an integrated circuit containing devices structures with hyper-abrupt p-n junctions. The hyper-abrupt p-n junction is defined in a SOI substrate by implanting a portion of a device layer to have one conductivity type and then implanting a portion of this doped region to have an opposite conductivity type. The counterdoping defines the hyper-abrupt p-n junction. A gate structure carried on a top surface of the device layer operates as a hard mask during the ion implantations to assist in defining a lateral boundary for the hyper-abrupt-n junction.Type: ApplicationFiled: April 8, 2008Publication date: October 8, 2009Inventors: Jeffrey B. Johnson, Alvin J. Joseph, Robert M. Rassel, Yun Shi
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Patent number: 7541252Abstract: A method of fabricating a semiconductor device includes forming a conductive layer on a semiconductor substrate, forming an insulating layer on the conductive layer, forming a word line and isolation trenches by patterning the insulating layer and the conductive layer, forming an isolation layer that fills the isolation trenches, forming a cell contact hole in the insulating layer such that the cell contact hole is self-aligned with the word line and exposes the word line, and forming a cell diode in the cell contact hole.Type: GrantFiled: June 29, 2007Date of Patent: June 2, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Ho Eun, Jae-Hee Oh, Jae-Hyun Park, Jung-In Kim, Seung-Pil Ko, Yong-Tae Oh
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Publication number: 20090101887Abstract: Methods and heterostructure barrier varactor (HBV) diodes optimized for application with frequency multipliers at providing outputs at submillimeter wave frequencies and above. The HBV diodes include a silicon-containing substrate, an electrode over the silicon-containing substrate, and one or more heterojunction quantum wells of alternating layers of Si and SiGe of one or more electrodes of the diode. Each SiGe quantum well preferably has a floating SiGe layer between adjacent SiGe gradients followed by adjacent Si layers, such that, a single homogeneous structure is provided characterized by having no distinct separations. The plurality of Si/SiGe heterojunction quantum wells may be symmetric or asymmetric.Type: ApplicationFiled: October 23, 2007Publication date: April 23, 2009Inventors: Erik M. Dahlstrom, Alvin J. Joseph, Robert M. Rassel, David C. Sheridan
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Patent number: 7510944Abstract: In a method of forming MIM capacitor structure, a TiW layer is formed and a capacitor mask is used to define areas of the TiW layer that will be sued in the formation of the MIM capacitor. A capacitor mask is then used to expose surface areas of the TiW layer, followed by deposition of a capacitor dielectric layer. A via mask and etch are then performed to provide a contact via to the bottom plate TiW layer. After the via etch, a Ti/TiN liner stack is deposited. The Ti/TiN multilayer stacked film serves as the capacitor top plate as well as the via contact liner film. Next, Tungsten is deposited to fill the vias and a Tungsten planarization step is performed.Type: GrantFiled: May 10, 2007Date of Patent: March 31, 2009Assignee: National Semiconductor CorporationInventors: Venkat Raghavan, Andrew Strachan
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Publication number: 20090079033Abstract: Large tuning range junction varactor includes first and second junction capacitors coupled in parallel between first and second varactor terminals. First and second plates of the capacitors are formed by three alternating doped regions in a substrate. The second and third doped regions are of the same type sandwiching the first doped region of the second type. A first varactor terminal is coupled to the second and third doped regions and a second varactor terminal is coupled to the first doped region. At the interfaces of the doped regions are first and second depletion regions, the widths of which can be varied by varying the voltage across the terminals from zero to full reverse bias. At zero bias condition, junction capacitance (Cmax) is enhanced due to summation of two junction capacitances in parallel. At reverse bias condition, with the merging of the two junction depletion widths, the capacitor areas are drastically reduced, thereby reducing Cmin significantly.Type: ApplicationFiled: September 20, 2007Publication date: March 26, 2009Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.Inventor: Manju SARKAR
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Patent number: 7449389Abstract: A method for fabricating a semiconductor including defining a first component region and a second component region in a semiconductor body is provided. A first epitaxial layer is formed through the first component region. A second epitaxial layer is formed over the first epitaxial layer, including configuring the physical dimensions of a first active zone of the first component region independent of a second active zone of the second component region via the first epitaxial layer and the second epitaxial layer. In one embodiment, the first component is a radio-frequency transistor and the second component is a varactor.Type: GrantFiled: October 27, 2006Date of Patent: November 11, 2008Assignee: Infineon Technologies AGInventors: Thomas Meister, Herbert Schäfer, Josef Böck, Rudolf Lachner
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Patent number: 7402890Abstract: A structure and associated method for forming a structure. The structure comprises a first doped region, a second doped region, a third doped region, and a first shallow trench isolation structure formed within a substrate. The first doped region comprises a first dopant having a first polarity. The second doped region forms a first electrode of a capacitor. The third doped region forms a second electrode of the capacitor. Each of the second doped region and the third doped region comprises a second dopant having a second polarity. The first shallow trench isolation structure is formed between the second doped region and the third doped region. The capacitor comprises a main capacitance. The structure comprises a first parasitic capacitance and a second parasitic capacitance. The first parasitic capacitance is about equal to the second parasitic capacitance.Type: GrantFiled: June 2, 2006Date of Patent: July 22, 2008Assignee: International Business Machines CorporationInventors: David S. Collins, Hanyi Ding, Kai Di Feng, Zhong-Xiang He, Xuefeng Liu
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Publication number: 20080169495Abstract: The embodiments of the invention provide a structure, method, etc. for a fin differential MOS varactor diode. More specifically, a differential varactor structure is provided comprising a substrate with an upper surface, a first vertical anode plate, and a second vertical anode plate electrically isolated from the first vertical anode plate. Moreover, a semiconductor fin comprising a cathode is between the first vertical anode plate and the second vertical anode plate, wherein the semiconductor fin, the first vertical anode plate, and the second vertical anode plate are each positioned over the substrate and perpendicular to the upper surface of the substrate.Type: ApplicationFiled: January 17, 2007Publication date: July 17, 2008Inventors: Bradley A. Orner, Edward J. Nowak, Robert M. Rassel
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Patent number: 7378327Abstract: A junction varactor includes a gate finger lying across an ion well of a semiconductor substrate; a gate dielectric situated between the gate finger and the ion well; a first ion diffusion region with first conductivity type located in the ion well at one side of the gate finger, the first ion diffusion region serving as an anode of the junction varactor; and a second ion diffusion region with a second conductivity type located in the ion well at the other side of the gate finger, the second ion diffusion region serving as a cathode of the junction varactor. In operation, the gate of the junction varactor is biased to a gate voltage VG that is not equal to 0 volt.Type: GrantFiled: June 10, 2007Date of Patent: May 27, 2008Assignee: United Microelectronics Corp.Inventor: Ching-Hung Kao
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Patent number: 7364967Abstract: Methods of forming a storage capacitor include forming an interlayer insulation layer having an opening therethrough on a semiconductor substrate, forming a contact plug in the opening, forming a molding oxide layer on the interlayer insulation layer and the contact plug, selectively removing portions of the molding oxide layer to form a recess above the contact plug, forming a titanium layer on a bottom surface and side surfaces of the recess, forming a titanium nitride layer on the titanium layer, and forming a titanium oxide nitride layer on the titanium nitride layer. A storage capacitor includes a semiconductor substrate, an interlayer insulation layer having a contact plug therein on the substrate, and a storage electrode on the contact plug including a titanium silicide layer, a titanium nitride layer on the titanium silicide layer, and a titanium oxide nitride layer on the titanium nitride layer.Type: GrantFiled: November 3, 2005Date of Patent: April 29, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Rak-Hwan Kim, Young-Joo Cho, Sung-Tae Kim, In-Sun Park, Hyeon-Deok Lee, Hyun-Suk Lee, Jung-Hee Chung, Hyun-Young Kim, Hyun-Seok Lim
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Patent number: 7285460Abstract: There is provided a semiconductor device which comprises a first interlayer insulating film (first insulating film) formed over a silicon (semiconductor) substrate, a capacitor formed on the first interlayer insulating film and having a lower electrode, a dielectric film, and an upper electrode, a fourth interlayer insulating film (second insulating film) formed over the capacitor and the first interlayer insulating film, and a metal pattern formed on the fourth interlayer insulating film over the capacitor and its periphery to have a stress in an opposite direction to the fourth interlayer insulating film. As a result, characteristics of the capacitor covered with the interlayer insulating film can be improved.Type: GrantFiled: August 31, 2005Date of Patent: October 23, 2007Assignee: Fujitsu LimitedInventor: Naoya Sashida
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Publication number: 20060180895Abstract: A capacitor device selectively combines MOM, MIM and varactor regions in the same layout area of an IC. Two or more types of capacitor regions arranged vertically on a substrate to form the capacitor device. This increase the capacitance per unit of the capacitor device, without occupying an extra layout area.Type: ApplicationFiled: February 11, 2005Publication date: August 17, 2006Inventors: Yueh-You Chen, Chung-Long Chang, Chih-Ping Chao, Chun-Hong Chen