Planar Transistor (epo) Patents (Class 257/E21.376)
  • Patent number: 8258626
    Abstract: A copper interconnection structure includes an insulating layer, an interconnection body including copper and a barrier layer surrounding the interconnection body. The barrier layer includes a first barrier layer formed between a first portion of the interconnection body and the insulating layer. The first portion of the interconnection body is part of the interconnection body that faces the insulating layer. The barrier layer also includes a second barrier layer formed on a second portion of the interconnection body. The second portion of the interconnection body is part of the interconnection body not facing the insulating layer. Each of the first and the second barrier layers is formed of an oxide layer including manganese, and each of the first and the second barrier layers has a position where the atomic concentration of manganese is maximized in their thickness direction of the first and the second barrier layers.
    Type: Grant
    Filed: September 15, 2009
    Date of Patent: September 4, 2012
    Assignee: Advanced Interconnect Materials, LLC
    Inventors: Junichi Koike, Akihiro Shibatomi
  • Patent number: 7553757
    Abstract: An interlayer insulator includes a first interlayer insulator and a second interlayer insulator formed on the first interlayer insulator and having a property of preventing diffusion of copper. A barrier metal film is formed on an inner wall in the wiring trench except an upper end and operative to prevent copper contained in the Cu wiring from diffusing into the interlayer insulator. The Cu wiring is brought into contact with the second interlayer insulator at the upper end and covered with the barrier metal film at a lower portion below the upper end.
    Type: Grant
    Filed: February 5, 2007
    Date of Patent: June 30, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hisakazu Matsumori