Abstract: An IGBT with a fast reverse recovery time rectifier includes an N-type drift epitaxial layer, a gate, a gate insulating layer, a P-type doped base region, an N-type doped source region, a P-type doped contact region, and a P-type lightly doped region. The P-type doped base region is disposed in the N-type drift epitaxial layer, and the P-type doped contact region is disposed in the N-type drift epitaxial layer. The P-type lightly doped region is disposed between the P-type contact doped region and the N-type drift epitaxial layer, and is in contact with the N-type drift epitaxial layer.

Abstract: In a semiconductor device of the present invention, a first base region 16 is extended to a part under a gate electrode 7 while having a vertical concentration profile of an impurity that increases from the surface of a semiconductor layer 3 and becomes maximum under an emitter region 5, and the length in the lateral direction from a point where the impurity concentration becomes maximum located under an end of the gate electrode 7 to the boundary with a second base region 15 is not smaller than the length in the vertical direction from the point where the impurity concentration becomes maximum to the boundary with the second base region 15.

Abstract: This invention generally relates to lateral insulated gate bipolar transistors (LIGBTs), for example in integrated circuits, methods of increasing switching speed of an LIGBT, a method of suppressing parasitic thyristor latch-up in a bulk silicon LIGBT, and methods of fabricating an LIGBT. In particular, a method of suppressing parasitic thyristor latch-up in a bulk silicon LIGBT comprises selecting a current gain ?v for a vertical transistor of a parasitic thyristor of the LIGBT such that in at least one predetermined mode of operation of the LIGBT ?v<1??p where ?p is a current gain of a parasitic bipolar transistor having a base-emitter junction formed by a Schottky contact between the a semiconductor surface and a metal enriched epoxy die attach.

Abstract: A semiconductor device comprises: a semiconductor substrate; a plurality of IGBT cells on the semiconductor substrate, each of the IGBT cells including a gate electrode and a first emitter electrode; a first gate wiring on the substrate and being connected to the gate electrode; an interlayer insulating film covering the first emitter electrode and the first gate wiring; and a second emitter electrode on the interlayer insulating film and being connected to the first emitter electrode through an opening of the interlayer insulating film, wherein the second emitter electrode extends above the first gate wiring via the interlayer insulating film.

Abstract: A method of producing a semiconductor device having a thickness of 90 ?m to 200 ?m and with an electrode on the rear surface, which achieves a high proportion of non-defective devices by optimizing the silicon concentration and thickness of the aluminum-silicon electrode. A surface device structure is formed on a first major surface of a silicon substrate. A buffer layer and a collector layer are formed on the second major surface after grinding to reduce the thickness of the substrate. On the collector layer, a collector electrode is formed including a first layer of an aluminum-silicon film having a thickness of 0.3 ?m to 1.0 ?m and a silicon concentration of 0.5 percent to 2 percent by weight, preferably not more than 1 percent by weight.

Abstract: A lateral hybrid IGBT is provided including: a RESURF region which is an n-type dopant layer formed in a surface portion of a substrate 1 made of p-type Si; a base region which is a p-type dopant layer; an emitter/source region which is an n-type dopant layer with a high concentration; a collector region which is a p-type dopant layer with a low concentration and formed in the RESURF region; a drain region which is an n-type dopant layer with a high concentration and formed adjacent to the collector region but on another cross-section; a base connection region which is a p-type dopant layer with a high concentration; a gate insulator film; and a gate electrode, wherein the collector region is shallower than the drain region located on the other cross-section.

Abstract: An improved coupling stability between the source region and the source electrode of the transistor is achieved. In the method for manufacturing the MOSFET, the p-type base region is formed in a semiconductor layer, and after the p-type base region is formed in the surface portion of the n+ type source region, the higher concentration source region extending from the side edge of the n+ type source region to the lateral side of the n+ type source region is formed in the surface portion of the p-type base region. Then, the source electrode coupled to the higher concentration source region is formed. This allows providing an improved coupling stability between the source electrode and the source region when a misalignment is occurred in the location for forming the source electrode during the formation of the source electrode to be coupled to the first source region.

Abstract: An integrated structure of an IGBT and a diode includes a plurality of doped cathode regions, and a method of forming the same is provided. The doped cathode regions are stacked in a semiconductor substrate, overlapping and contacting with each other. As compared with other doped cathode regions, the higher a doped cathode region is disposed, the larger implantation area the doped cathode region has. The doped cathode regions and the semiconductor substrate have different conductive types, and are applied as a cathode of the diode and a collector of the IGBT. The stacked doped cathode regions can increase the thinness of the cathode, and prevent the wafer from being overly thinned and broken.

Abstract: Stress-modified device structures, methods of fabricating such stress-modified device structures, and design structures for an integrated circuit. An electrical characteristic of semiconductor devices formed on a common substrate, such as the current gains of bipolar junction transistors, may be altered by modifying stresses in structures indirectly on or over, or otherwise indirectly coupled with, the semiconductor devices. The structures, which may be liners for contacts in a contact level of an interconnect, are physically spaced away from, and not in direct physical contact with, the respective semiconductor devices because at least one additional intervening material or structure is situated between the stress-imparting structures and the stress-modified devices.

Abstract: A method for manufacturing a reverse-conducting semiconductor device (RC-IGBT) with a seventh layer formed as a gate electrode and a first electrical contact on a emitter side and a second electrical contact on a collector side, which is opposite the emitter side, a wafer of a first conductivity type with a first side and a second side opposite the first side is provided. For the manufacturing of the RC-IGBT on the collector side, a first layer of the first conductivity type or of a second conductivity type is created on the second side. A mask with an opening is created on the first layer and those parts of the first layer, on which the opening of the mask is arranged, are removed. The remaining parts of the first layer form a third layer. Afterwards, for the manufacturing of a second layer of a different conductivity type than the third layer, ions are implanted into the wafer on the second side into those parts of the wafer, on which the at least one opening is arranged.

Abstract: A lateral bipolar junction transistor includes an emitter region; a base region surrounding the emitter region; a gate disposed at least over a portion of the base region; a collector region surrounding the base region with an offset between an edge of the gate and the collector region; a lightly doped drain region between the edge of the gate and the collector region; a salicide block layer disposed on or over the lightly doped drain region; and a collector salicide formed on at least a portion of the collector region.

Abstract: A horizontal semiconductor device having multiple unit semiconductor elements, each of said unit semiconductor element formed by an IGBT including: a semiconductor substrate of a first conductivity type; a semiconductor region of a second conductivity type formed on the semiconductor substrate; a collector layer of the first conductivity type formed within the semiconductor region; a ring-shaped base layer of the first conductivity type formed within the semiconductor region such that the base layer is off said collector layer but surrounds said collector layer; and a ring-shaped first emitter layer of the second conductivity type formed in said base layer, wherein movement of carriers between the first emitter layer and the collector layer is controlled in a channel region formed in the base layer, and the unit semiconductor elements are disposed adjacent to each other.

Abstract: A reverse-conducting insulated gate bipolar transistor includes a wafer of first conductivity type with a second layer of a second conductivity type and a third layer of the first conductivity type. A fifth electrically insulating layer partially covers these layers. An electrically conductive fourth layer is electrically insulated from the wafer by the fifth layer. The third through the fifth layers form a first opening above the second layer. A sixth layer of the second conductivity type and a seventh layer of the first conductivity type are arranged alternately in a plane on a second side of the wafer. A ninth layer is formed by implantation of ions through the first opening using the fourth and fifth layers as a first mask.

Abstract: A controlled-punch-through semiconductor device with a four-layer structure is disclosed which includes layers of different conductivity types, a collector on a collector side, and an emitter on an emitter side which lies opposite the collector side. The semiconductor device can be produced by a method performed in the following order: producing layers on the emitter side of wafer of a first conductivity type; thinning the wafer on a second side; applying particles of the first conductivity type to the wafer on the collector side for forming a first buffer layer having a first peak doping concentration in a first depth, which is higher than doping of the wafer; applying particles of a second conductivity type to the wafer on the second side for forming a collector layer on the collector side; and forming a collector metallization on the second side.

Abstract: A semiconductor device includes a first semiconductor layer, a second semiconductor layer on the first semiconductor layer, a third semiconductor layer on the second semiconductor layer and being in the shape of an island on the second semiconductor layer, a dielectric film on the second and third semiconductor layers, a control electrode on the dielectric film, a first main electrode electrically connected to the second and third semiconductor layers, and a second main electrode electrically connected to the first semiconductor layer and having a Pd layer.

Abstract: A semiconductor device includes a substrate of a first conductivity type, a base region of a second conductivity type, a source region of the first conductivity type, a collector region of the second conductivity type, a trench gate, which is formed in a trench via a gate insulation film, an electrically conductive layer, which is formed within a contact trench that is formed through the source region, a source electrode, which is in contact with the electrically conductive layer and the source region, and a latch-up suppression region of the second conductivity type, which is formed within the base region, in contact with the electrically conductive layer, and higher in impurity concentration than the base region. The distance between the gate insulation film and the latch-up suppression region is not less than the maximum width of a depletion layer that is formed in the base layer by the trench gate.

Abstract: A cell of a semiconductor device comprises a substrate of n-type with a trench formed in a portion of a first main surface of the substrate and filled with insulator. Two device-feature regions are formed beneath the first main surface of the substrate, the first one at one side and the second one at the other side of the trench. A region of a p-type and/or a region of metal is formed in the first device feature region and is connected to a first electrode. A p-n junction is formed in the second device feature region and the p-region of the p-n junction is connected to a second electrode. A U-shaped region is formed between the two device regions. An IGBT without tail during turning-off can be fabricated with a simple process at a low cost.

Abstract: Methods for fabricating a device structure in a semiconductor-on-insulator substrate. The method includes forming a first isolation region in the substrate device layer that extends from a top surface of the device layer to a first depth and forming a second isolation region in the semiconductor layer that extends from the top surface of the semiconductor layer to a second depth greater than the first depth. The method further includes forming a doped region of the device structure in the semiconductor layer that is located vertically between the first isolation region and the insulating layer.

Abstract: This disclosure relates to devices and methods relating to coupled first and second device portions.

Abstract: A high voltage horizontal IGBT, which is an aspect of a semiconductor device relating to the present invention, has a buffer region formed in an SOI substrate and extending from a surface of the SOI substrate to a surface of a buried oxide film. An interface between the buffer region and a drift region is positioned equally in a vicinity of a bottom of the buffer region and in a vicinity of a surface of the buffer region or shifted toward a body region in the vicinity of the bottom of the buffer region compared to that in the vicinity of the surface of the buffer region. With this structure, a concentration of electric field in the vicinity of the bottom of the buffer region is moderated, whereby a collector-emitter breakdown voltage can further be increased.

Abstract: An IGBT includes a first region, a second region located within the first region, a first contact coupled to the first region, a first layer arranged below the first region, a gate overlying at least a portion of the first region between the second region and the first layer and a second layer formed under the first layer. One or more stacked zones are formed within the second layer. Each one or more stacked zones includes a first zone and a second zone that overlies the first zone. Each first zone is inversely doped with respect to the second layer and each second zone is inversely doped with respect to the first zone. The IGBT further includes a third layer formed under the second layer and a second contact coupled to the third layer.

Abstract: An insulated gate bipolar transistor (IGBT) includes a first conductivity type substrate and a second conductivity type drift layer on the substrate. The second conductivity type is opposite the first conductivity type. The IGBT further includes a current suppressing layer on the drift layer. The current suppressing layer has the second conductivity type and has a doping concentration that is larger than a doping concentration of the drift layer. A first conductivity type well region is in the current suppressing layer. The well region has a junction depth that is less than a thickness of the current suppressing layer, and the current suppressing layer extends laterally beneath the well region. A second conductivity type emitter region is in the well region.

Abstract: A device 100 comprising a substrate 115 having crystal-support-structures 110 thereon, and a III-V crystal 210. The III-V crystal is on a single contact region 140 of one of the crystal-support-structures. An area of the contact region is no more than about 50 percent of a surface area 320 of the III-V crystal.

Abstract: A power semiconductor component is described. One embodiment provides a semiconductor body having an inner zone and an edge zone. A base zone of a first conduction type is provided. The base zone is arranged in the at least one inner zone and the at least one edge zone. An emitter zone of a second conduction type is provided. The emitter zone is arranged adjacent to the base zone in a vertical direction of the semiconductor body. A field stop zone of the first conduction type is provided. The field stop zone is arranged in the base zone and has a first field stop zone section having a first dopant dose in the edge zone and a second field stop zone section having a second dopant dose in the inner zone. The first dopant dose is higher than the second dopant dose.

Abstract: A power semiconductor device has a top surface and an opposed bottom surface below a part of which is a thick portion of semiconductor substrate. At least a portion of a drift region of the device has either no or only a thin portion of semiconductor substrate positioned thereunder. The top surface has a high voltage terminal and a low voltage terminal connected thereto to allow a voltage to be applied laterally across the drift region. At least two MOS (metal-oxide-semiconductor) gates are provided on the top surface. The device has at least one relatively highly doped region at its top surface extending between and in contact with said first and second MOS gates. The device has improved protection against triggering of parasitic transistors or latch-up without the on-state voltage drop or switching speed being compromised.

Abstract: A p-type region is provided on a first n-type region. A second n-type region is provided on the p-type region, spaced apart from the first n-type region by the p-type region. A gate electrode serves to form an n-channel between the first and second n-type regions. A first electrode is electrically connected to each of the p-type region and the second n-type region. A second electrode is provided on the first n-type region such that it is spaced apart from the p-type region by the first n-type region and at least a part thereof is in contact with the first n-type region. The second electrode is made of any of metal and alloy and serves to inject holes into the first n-type region.

Abstract: Current density in an insulated gate bipolar transistor (L-IGBT) may be increased by adding a second gate, and the corresponding MOS transistors, to the source area, which increases the base current compared to a L-IGBT with a single MOS gate. The current density may be further increased by extending the base of the bipolar transistor in the L-IGBT vertically to the bottom surface of the silicon on insulator (SOI) film in which the L-IGBT is fabricated. Adding a buffer diffused region around the sinks in the source improves the base current spatial uniformity, which improves the safe operating area (SOA) of the L-IGBT. A L-IGBT of either polarity may be formed with the inventive configurations. A method of forming the inventive L-IGBT is also disclosed.

Abstract: A punch-through type IGBT generally has a thick p++-type collector layer. Therefore, the FWD need be externally attached to the IGBT when the IGBT is used as a switching element in an inverter circuit for driving a motor load, and thus the number of processes and components increases. In the invention, trenches are formed penetrating through a collector layer and reaching a buffer layer. A collector electrode is formed in the trenches, too. With this structure, a current path is formed between an emitter electrode and the collector electrode without through the collector layer and functions as the FWD.

Abstract: A semiconductor device for ESD protection includes a semiconductor substrate of a first conductivity type and a well region of a second conductivity type formed within the substrate. The well region is characterized by a first depth. The device includes an MOS transistor, a first bipolar transistor, and a second bipolar transistor. The MOS transistor includes a first lightly doped drain (LDD) region of a second depth within the well region, and a drain region and an emitter region within in the first LDD region. The emitter region is characterized by a second conductivity type. The first bipolar transistor is associated with the emitter region, the first LDD region, and the well region, and is characterized by a first trigger voltage. The second bipolar transistor is associated with the first LDD region, the well region, and the substrate, and is characterized by a second trigger voltage.

Abstract: In a first region at a first main surface of an n type semiconductor substrate, a p base layer, an n source layer, a gate electrode and an emitter electrode are formed, and a collector electrode is formed at a second main surface, constituting an IGBT. A p layer constituting a guard ring is formed in a second region qualified as an outer circumferential junction region, extending to a predetermined depth from the surface. In the second region are also formed an AlSi layer and a semi-insulating silicon nitride film, as well as an over coat film. An n layer is formed at the surface of a third region. In addition, an AlSi layer qualified as a stepped portion is formed in the third region, spaced apart from an AlSi layer located at the outermost circumferential side. Thus, a semiconductor device directed to stabilizing the main breakdown voltage characteristics is obtained.

Abstract: An IGBT transistor includes a drift region, at least one body region housed in the drift region and having a first type of conductivity, and a conduction region, which crosses the body region in a direction perpendicular to a surface of the drift region and has the first type of conductivity and a lower resistance than the body region. The conduction region includes a plurality of implant region, arranged at respective depths from the surface of the drift region.

Abstract: Disclosed is a bipolar complementary metal oxide semiconductor (BiCMOS) or NPN/PNP device that has a collector, an intrinsic base above the collector, shallow trench isolation regions adjacent the collector, a raised extrinsic base above the intrinsic base, a T-shaped emitter above the extrinsic base, spacers adjacent the emitter, and a silicide layer that is separated from the emitter by the spacers.

Abstract: SiC-IGBTs, which have an inversion-type channel with high channel resistance and have high on-voltage due to an influence from the surface state of the interface between a gate insulating film and a base layer, are required to decrease the on-voltage. An embedded collector region is partially formed in a base layer which is formed on an emitter layer of a SiC semiconductor. A channel layer is formed on the base layer and the embedded collector region to constitute an accumulation-type channel. Consequently, at on time, holes are accumulated in the upper layer portion of the channel layer so that a low-resistant channel is formed. Current by the holes flows to the emitter layer through a channel from the collector region and becomes a base current for an npn transistor composed of the embedded collector region, the base region and the emitter region.

Abstract: A semiconductor device includes an n-conductive type semiconductor substrate having a main side and a rear side, a p-conductive type layer arranged over the main side of the substrate, a main side n-conductive type region arranged in the p-conductive type layer, a rear side n-conductive type layer arranged over the rear side of the substrate, a first trench which reaches the substrate and penetrates the main side n-conductive type region and the p-conductive type layer, a second trench which reaches an inside of the p-conductive type layer, a second electrode layer, which is embedded in the second trench and connected to the p-conductive type layer. Hereby, the semiconductor device, in which the recovery property of a diode cell can be improved without damaging the property of a MOS transistor cell or an IGBT cell and the surge withstand property does not deteriorate, can be obtained.

Abstract: A semiconductor device arrangement comprises a semiconductor device and an injector device. The semiconductor device comprises a first current electrode region of a first conductivity type, a second current electrode region of the first conductivity type, a drift region between the first and the second current electrode regions, and at least one floating region of a second conductivity type formed in the drift region. The injector device is arranged to receive an activation signal when the semiconductor device is turned on and to inject charge carriers of the second conductivity type into the drift region and the at least one floating region in response to receiving the activation signal.

Abstract: A structure and method of fabricating electrostatic discharge (EDS) circuitry in an integrated circuit chip by integrating a lateral bipolar, either a p-n-p with a NMOSFET or a n-p-n with a PMOSFET within a triple well. The lateral bipolar preferably includes diodes at the I/O and/or the VDDs of the circuitry.

Abstract: A trench PT IGBT (or NPT IGBT) having clamp diodes for ESD protection and prevention of shortage among gate, emitter and collector. The clamp diodes comprise multiple back-to-back Zener Diode composed of doped regions in a polysilicon layer doped with dopant ions of a first conductivity type next to a second conductivity type disposed on an insulation layer above said semiconductor power device. Trench gates are formed underneath the contact areas of the clamp diodes as the buffer layer for prevention of shortage.

Abstract: Disclosed is a semiconductor device including: an N-type RESURF region formed in a P-type semiconductor substrate; a P-type base region formed in an upper portion of the semiconductor substrate so as to be adjacent to the RESURF region; an N-type emitter/source region formed in the base region so as to be apart from the RESURF region; a P-type base connection region formed in the base region so as to be adjacent to the emitter/source region; a gate insulating film and a gate electrode overlying the emitter/source region, the base region, and the RESURF region; and a P-type collector region formed in the RESURF region so as to be apart from the base region. Lattice defect is generated in the semiconductor substrate such that a resistance value of the semiconductor substrate is twice or more the resistance value of the semiconductor substrate that depends on the concentration of an impurity implanted in the semiconductor substrate.

Abstract: Stress-modified device structures, methods of fabricating such stress-modified device structures, and design structures for an integrated circuit. An electrical characteristic of semiconductor devices formed on a common substrate, such as the current gains of bipolar junction transistors, may be altered by modifying stresses in structures indirectly on or over, or otherwise indirectly coupled with, the semiconductor devices. The structures, which may be liners for contacts in a contact level of an interconnect, are physically spaced away from, and not in direct physical contact with, the respective semiconductor devices because at least one additional intervening material or structure is situated between the stress-imparting structures and the stress-modified devices.

Abstract: A p-type body region and an n-type buffer region are formed on an n? drift region. An n++ emitter region and a p++ contact region are formed on the p-type body region in contact with each other. A p++ collector region is formed on the n-type buffer region. An insulating film is formed on the n? drift region, and a gate insulating film is formed on the n++ emitter region, the p-type body region, and the n drift region. A gate electrode is formed on the insulating film and the gate insulating film. A p+ low-resistivity region is formed in the p-type body region and surrounding the interface between the n++ emitter region and between the p-type body region and the p++ contact region. The p-type body region has two local maxima of an impurity concentration profile at the interface between the body region and the gate insulating film.

Abstract: A semiconductor device includes deep first field limiting rings, shallow second field limiting rings, insulation films covering each surface portion of each of the first and the second field limiting rings, and conductive field plates each in contact with a surface of each of the first and the second field limiting rings. Each of the field plates project over a surface of each of the insulation films between the first field limiting rings and the second field limiting rings.

Abstract: A semiconductor device and method of manufacturing the same includes an n?-single crystal silicon substrate, with an oxide film selectively formed thereon. On the oxide film, gate polysilicon is formed. The surface of the gate polysilicon is covered with a gate oxide film whose surface is covered with a cathode film doped in an n-type with an impurity concentration higher than that of the substrate as an n?-drift layer. In the cathode film, a section in contact with the substrate becomes an n+-buffer region with a high impurity concentration, next to which a p-base region is formed. Next to the p-base region, an n+-source region is formed. On the cathode film, an interlayer insulator film is selectively formed on which an emitter electrode is formed. A semiconductor device such as an IGBT is obtained with a high rate of acceptable products, an excellent on-voltage to turn-off loss tradeoff and an excellent on-voltage to breakdown voltage tradeoff.

Abstract: A capacitor may include at least one of a polysilicon layer over a semiconductor substrate; a capacitor dielectric layer over a polysilicon layer; an insulating layer over a capacitor dielectric layer; a metal layer connected to a capacitor dielectric layer through a first region of an insulating layer; an upper metal wiring layer connected to a metal layer over an insulating layer; and/or a lower metal wiring line layer connected to a polysilicon layer through a metal contact that passes through a second region of an insulating layer and a capacitor dielectric layer over the insulating layer.

Abstract: A field effect transistor and a method of fabricating the field effect transistor. The field effect transistor includes: a silicon body, a perimeter of the silicon body abutting a dielectric isolation; a source and a drain formed in the body and on opposite sides of a channel formed in the body; and a gate dielectric layer between the body and an electrically conductive gate electrode, a bottom surface of the gate dielectric layer in direct physical contact with a top surface of the body and a bottom surface the gate electrode in direct physical contact with a top surface of the gate dielectric layer, the gate electrode having a first region having a first thickness and a second region having a second thickness, the first region extending along the top surface of the gate dielectric layer over the channel region, the second thickness greater than the first thickness.

Abstract: A data reading/writing head reading/writing data from/to a ferroelectric recording medium by using an electric field effect, includes a semiconductor body having a first plane on which an air bearing pattern is formed and a second plane crossing the first plane. A sensing unit is located on the second plane and reads data written to the ferroelectric recording medium, wherein the second plane is separated from the first plane, and a floating gate is disposed on the sensing unit, wherein an end of the floating gate extends to the first plane to guide an electric field from the ferroelectric recording medium to the sensing unit.

Abstract: The power conversion apparatus uses the semiconductor device. Said semiconductor device includes a first group of power semiconductor elements at least one of which is electrically connected between a first potential and a third potential, a second group of power semiconductor elements at least one of which is electrically connected between a second potential and the third potential, and a third group of power semiconductor elements at least one of which is electrically connected between the first potential and the third potential. The second group is disposed between the first group and third group. Thereby, a low-loss semiconductor device having both inductance reducibility and heat generation balancing capability and also an electric power conversion apparatus using the same is provided.

Abstract: Method and systems for producing a semiconductor circuit arrangement are disclosed. In one implementation, after a formation of a first electrically conductive layer at the surface of a semiconductor substrate for the purpose of realizing a base connection layer and a first split gate layer, an implantation mask is formed for the purpose of carrying out a first collector implantation for the purpose of forming a collector connection zone. After the formation of a hard mask layer and a first etching mask, the hard mask layer is patterned and an emitter window is uncovered using the patterned hard mask layer. Using the patterned hard mask layer a second collector implantation is effected for the purpose of forming a collector zone, a base layer being formed in the region of the emitter window.

Abstract: A semiconductor has an IGBT active section and a control circuit section for detecting an IGBT abnormal state. A collector region is formed on the back surface side (i.e., on the IGBT collector side) in a selective manner, namely right under the IGBT active section.

Abstract: Present invention proposes a dramatic improvement of CMOS IC technology by providing high speed bipolar current amplifiers compatible with CMOS technological process while retaining the footprint compatible to one of standard CMOS devices. This invention promises further increase of speed of ICs as well as a reduction of power dissipation.

Abstract: An insulated gate bipolar transistor according to an embodiment includes a first conductive type collector ion implantation area in a substrate; a second conductive type buffer layer, including a first segment buffer layer and a second segment buffer layer, on the first conductive collector ion implantation area; a first conductive type base area on the second conductive type buffer layer; a gate on the substrate at a side of the first conductive type base area; a second conductive type emitter ion implantation area in the first conductive type base area; an insulating layer on the gate; an emitter electrode electrically connected to the second conductive type emitter ion implantation area; and a collector electrode electrically connected to the first conductive collector ion implantation area.