Abstract: A semiconductor device according to the invention includes n-type semiconductor substrate 1; trenches 15 formed in the surface portion of semiconductor substrate 1; a protruding semiconductor region between trenches 15; p-type base layer 2 in the protruding semiconductor region, p-type base layer 2 being positioned as deep as or shallower than trench 15; an n++-type emitter region or a source region in the surface portion of p-type base layer 2; gate insulator film 4a on the first side wall of the protruding semiconductor region; and gate electrode 6 on gate insulator film 4a. Trench 15 is from 0.5 ?m to 3.0 ?m deep and the short side of trench 15 is 1.0 ?m or longer. The short side of the protruding semiconductor region is from 0.5 ?m to 3.0 ?m long. Gate electrode 6 contains electrically conductive polycrystalline silicon as its main component. Gate electrode 6 is from 0.2 ?m to 1.0 ?m thick.

Abstract: A semiconductor device includes: a GaAs chip; and a resin sealing the GaAs chip. The GaAs chip includes: a p-type GaAs layer; an n-type GaAs layer on the p-type GaAs layer; a metal electrode located on the n-type GaAs layer along an edge of the GaAs chip and to which a positive voltage is applied; a device region located in a central portion of the GaAs chip; a semi-insulating region located between the metal electrode and the device region and extending in the p-type GaAs layer and the n-type GaAs layer; and a connecting portion disposed outside the semi-insulating region and electrically connecting the p-type GaAs layer to the metal electrode.

Abstract: According to one embodiment, a power semiconductor device comprises a semiconductor substrate. A transistor gate structure is arranged in a trench formed in the semiconductor substrate. A body region of a first conductivity type is arranged adjacent the transistor gate structure and a first highly-doped region of a second conductivity type is arranged in an upper portion of the body region. A drift zone of the second conductivity type is arranged below the body region and a second highly-doped region of the second conductivity type is arranged below the drift zone. An end-of-range irradiation region is arranged adjacent the transistor gate structure and has a plurality of vacancies. In some embodiments, at least some of the vacancies are occupied by metals.

Abstract: A power transistor. One embodiment provides a power transistor having a first terminal, a second terminal and a control terminal. A support layer is formed of a first material having a first bandgap. An active region is formed of a second material having a second bandgap wider than the first bandgap, and is disposed on the support layer. The active region is arranged to form part of a current path between the first and second terminal in a forward mode of operation. The active region includes at least one pn-junction.

Abstract: Provided are a power semiconductor device using a silicon substrate as a FS layer and a method of manufacturing the same. A semiconductor substrate of a first conductivity type is prepared. An epitaxial layer is grown on one surface of the semiconductor substrate. Here, the epitaxial layer is doped at a concentration lower than that of the semiconductor substrate and is intended to be used as a drift region. A base region of a second conductivity type is formed in a predetermined region of the epitaxial layer. An emitter region of the first conductivity type is formed in a predetermined region of the base region. A gate electrode with a gate insulating layer is formed on the base region between the emitter region and the drift region of the epitaxial layer. A rear surface of the semiconductor substrate is ground to reduce the thickness of the semiconductor substrate, thereby setting an FS region of the first conductivity type.

Abstract: A manufacturing method of a semiconductor device 10 includes forming a plurality of second conductive second semiconductor regions at specific intervals on one main surface of a first conductive first semiconductor region, the plurality of second conductive second semiconductor regions being opposite to the first conductive first semiconductor region, forming a plurality of the first conductive third semiconductor regions on a main surface of the second semiconductor region, the plurality of the first conductive third regions being separated from each other, forming a plurality of holes at specific intervals on an another main surface which faces the one main surface of the first semiconductor region, the plurality of holes being separated from each other, forming a pair of adjacent second conductive fourth semiconductor regions which are alternately connected at a bottom part of the hole within the first semiconductor region, and burying an electrode within the hole.

Abstract: A semiconductor device includes: a collector layer of a first conductivity type; a semiconductor area of a second conductivity type formed on the collector layer; a base layer of the first conductivity type formed on the semiconductor area; an emitter layer of the second conductivity type formed in an island shape on the base layer; an insulation film formed on the semiconductor area, the base layer and the emitter layer; a gate electrode formed on the insulation film; an emitter electrode formed on the base layer and the emitter layer; a collector electrode formed on the collector layer; and a crystal defect area of the first conductivity type locally formed in the collector layer. A position of a defect concentration peak of the crystal defect area is in the collector layer. An edge of the crystal defect area adjoins the semiconductor area or is located in the semiconductor area.

Abstract: According to one embodiment, a semiconductor device comprises a body of a first conductivity type having a source region and a channel, the body being in contact with a top contact layer. The device also comprises a gate arranged adjacent the channel and a drift zone of a second conductivity type arranged between the body and a bottom contact layer. An integrated diode is formed partially by a first zone of the first conductivity type within the body and being in contact with the top contact layer and a second zone of the second conductivity type being in contact with the bottom contact layer. A reduced charge carrier concentration region is formed in the drift zone having a continuously increasing charge carrier lifetime in the vertical direction so that the charge carrier lifetime is lowest near the body and highest near the bottom contact layer.

Abstract: A method for manufacturing a semiconductor array, particularly a high-frequency bipolar transistor, is provided, the method includes process steps, so that a dielectric is produced on a mono-crystalline, first semiconductor region of a first conductivity type, a silicide layer is deposited and patterned in such a way that the silicide layer is insulated from the first semiconductor region by the dielectric, and, to form a base region, a second semiconductor region of a second conductivity type is applied to the first semiconductor region and to the silicide layer in such a way that the second semiconductor region lies with a first interface on the first semiconductor region and with a second interface on the silicide layer.

Abstract: According to embodiments, an insulated gate bipolar transistor (IGBT) may include a first conductive type collector ion implantation area, formed within a substrate, second conductive type first buffer layers, formed over the collector ion implantation area and each including a first segment buffer layer and a second segment buffer layer, a first conductive type poly layer formed from a surface of the substrate to the collector ion implantation area, the first conductive type poly layer having a contact structure, a second buffer layer of the second conductive type, formed in the substrate area next to the first conductive type poly layer. According to embodiments, a segment buffer layer may have different concentrations according areas. Accordingly, amounts of hole currents injected through the buffer layers may differ according to areas.

Abstract: A semiconductor device is disclosed that reduces the reverse leakage current caused by reverse bias voltage application and reduces the on-voltage of the IGBT. A two-way switching device using the semiconductor devices is provided, and a method of manufacturing the semiconductor device is disclosed. The reverse blocking IGBT reduces the reverse leakage current and the on-voltage by bringing portions of an n?-type drift region 1 that extend between p-type base regions and an emitter electrode into Schottky contact to form Schottky junctions.

Abstract: A P channel vertical conduction Rad Hard MOSFET has a plurality of closely spaced base strips which have respective sources to form invertible surface channels with the opposite sides of each of the stripes. A non-DMOS late gate oxide and overlying conductive polysilicon gate are formed after the source and base regions have been diffused. The base stripes are spaced by about 0.6 microns, and the polysilicon gate stripes are about 3.2 microns wide. A P type enhancement region is implanted through spaced narrow windows early in the process and are located in the JFET common conduction region which is later formed by and between the spaced base stripes. The device is a high voltage (greater than 25 volts) P channel device with very low gate capacitance and very low on resistance.

Abstract: In a vertical-type metal insulator field effect transistor device having a first conductivity type drain region layer, a plurality of second conductivity type base regions are produced and arranged in the first conductivity type drain region layer, and a first conductivity type source region is produced in each of the second conductivity type base regions. Both a gate insulating layer and a gate electrode layer are formed on the first conductivity type drain region layer such that a plurality of unit transistor cells are produced in conjunction with the second conductivity type base regions and the first conductivity type source regions, and each of the unit transistor cells includes respective span portions of the gate insulating layer and the gate electrode layer, which bridge a space between the first conductivity type source regions formed in two adjacent second conductivity base regions.

Abstract: A process for forming an NPT IGBT in a thin N type silicon wafer in which the bottom surface of a thin silicon wafer (100 microns thick or less) has a shallow reduced lifetime region in its bottom formed by a light species atom implant to a depth of less than about 2.5 microns. A P+ transparent collector region about 0.5 microns deep is formed in the bottom of the damaged region by a boron implant. A collector contact of Al/Ti/NiV and Ag is sputtered onto the collector region and is annealed at 200° C. to 400° C. for 30 to 60 minutes. A pre-anneal step before applying the collector metal can be carried out in vacuum at 300° C. to 400° C. for 30 to 60 seconds.

Abstract: The collector or anode of a non-punch through IGBT formed in a float zone silicon wafer is formed by a P doped amorphous silicon layer deposited on the back surface of an ultra thin wafer. A DMOS structure is formed on the top surface of the wafer before the bottom structure is formed. A back contact is formed over the amorphous silicon layer. No alloy step is needed to activate the anode defined by the P type amorphous silicon.

Abstract: Insulated gate bipolar conduction transistors (IBCTs) are provided. The IBCT includes a drift layer having a first conductivity type. An emitter well region is provided in the drift layer and has a second conductivity type opposite the first conductivity type. A well region is provided in the drift layer and has the second conductivity type. The well region is spaced apart from the emitter well region. A space between the emitter well region and the well region defines a JFET region of the IBCT. An emitter region is provided in the well region and has the first conductivity type and a buried channel layer is provided on the emitter well region, the well region and the JFET region and has the first conductivity type. Related methods of fabrication are also provided.

Abstract: A semiconductor device including a drift layer of a first conductivity type formed on a surface of a semiconductor substrate. A surface of the drift layer has a second area positioned on an outer periphery of a first area. A cell portion formed in the first area includes a first base layer of a second conductivity type, a source layer and a control electrode formed in the first base layer and the source layer. The device also includes a terminating portion formed in the drift layer including a second base layer of a second conductivity type, an impurity diffused layer of a second conductivity type, and a metallic compound whose end surface on the terminating portion side is positioned on the cell portion side away from the end surface of the impurity diffused layer on the terminal portion side.

Abstract: A power electronic device is integrated on a semiconductor substrate of a first type of conductivity. The device includes a plurality of elemental units, and each elemental unit includes a body region of a second type of conductivity which is realized on a semiconductor layer of the first type of conductivity formed on the semiconductor substrate, and a column region of the first type of conductivity which is realized in said semiconductor layer below the body region. The semiconductor layer includes multiple semiconductor layers which overlap each other. The resistivity of each layer is different from that of the other layers. The column region includes a plurality of doped sub-regions, each realized in one of the semiconductor layers. The amount of charge of each doped sub-region balances the amount of charge of the corresponding semiconductor layer in which each doped sub-region is realized.

Abstract: In a semiconductor device, the semiconductor device includes a conductive structure, first insulating layers and first conductive layer patterns. The conductive structure includes a first portion, second portions and third portions. The second portions extend in a first direction on the first portion. The second portions are spaced apart from one another in a second direction substantially perpendicular to the first direction. The third portions are provided on the second portions. The third portions are spaced apart from one another in the first and second directions. The first insulating layers cover sidewalls of the second portions. The first conductive layer patterns are provided on the first insulating layers.

Abstract: A structure and a process for a self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process. Embodiments include SiGe CBiCMOS with high-performance SiGe NPN transistors and PNP transistors. As the PNP transistors and NPN transistors contained different types of impurity profile, they need separate lithography and doping step for each transistor. The process is easy to integrate with existing CMOS process to save manufacturing time and cost. As plug-in module, fully integration with SiGe BiCMOS processes. High doping Polysilicon Emitter can increase hole injection efficiency from emitter to base, reduce emitter resistor, and form very shallow EB junction. Self-aligned N+ base implant can reduce base resistor and parasitical EB capacitor. Very low collector resistor benefits from BP layer. PNP transistor can be Isolated from other CMOS and NPN devices by BNwell, Nwell and BN+ junction.

Abstract: A starting wafer for high voltage semiconductor devices is formed by implanting arsenic into the top surface of a p type silicon substrate wafer to a depth of about 0.1 micron. A N type non-graded epitaxial layer is then grown atop the substrate without any diffusion step so that the arsenic is not intentionally driven. Device junction are then diffused into the epitaxially grown layer.

Abstract: Double gate IGBT having both gates referred to a cathode in which a second gate is for controlling flow of hole current. In on-state, hole current can be largely suppressed. While during switching, hole current is allowed to flow through a second channel. Incorporating a depletion-mode p-channel MOSFET having a pre-formed hole channel that is turned ON when 0V or positive voltages below a specified threshold voltage are applied between second gate and cathode, negative voltages to the gate of p-channel are not used. Providing active control of holes amount that is collected in on-state by lowering base transport factor through increasing doping and width of n well or by reducing injection efficiency through decreasing doping of deep p well. Device includes at least anode, cathode, semiconductor substrate, n? drift region, first & second gates, n+ cathode region; p+ cathode short, deep p well, n well, and pre-formed hole channel.

Abstract: The invention relates to a semiconductor device (10) with a substrate (11) and a semiconductor body (12) comprising a vertical bipolar transistor with an emitter region, a base region and a collector region (1, 2, 3) of, respectively, a first conductivity type, a second conductivity type opposite to the first conductivity type and the first conductivity type, wherein the collector region (3) comprises a first sub-region (3A) bordering the base region (2) and a second sub-region (3B) bordering the first sub-region (3A) which has a lower doping concentration than the second sub-region (3B), and the transistor is provided with a gate electrode (5) which laterally borders the first sub-region (3A) and by means of which the first sub-region (3A) may be depleted.

Abstract: A trench-type insulated-gate semiconductor device is disclosed that includes unit cells having a trench gate structure that are scattered uniformly throughout the active region of the device. The impurity concentration in the portion of a p-type base region, sandwiched between an n+-type emitter region and an n-type drift layer and in contact with a gate electrode formed in the trench via a gate insulator film, is the lowest in the portion thereof sandwiched between the bottom plane of n+-type emitter regions and the bottom plane of p-type base region and parallel to the major surface of a silicon substrate. The trench-type insulate-gate semiconductor device according to the invention minimizes the variation of the gate threshold voltage.

Abstract: A semiconductor device and method of manufacturing the same includes an n?-single crystal silicon substrate, with an oxide film selectively formed thereon. On the oxide film, gate polysilicon is formed. The surface of the gate polysilicon is covered with a gate oxide film whose surface is covered with a cathode film doped in an n-type with an impurity concentration higher than that of the substrate as an n?-drift layer. In the cathode film, a section in contact with the substrate becomes an n+-buffer region with a high impurity concentration, next to which a p-base region is formed. Next to the p-base region, an n+-source region is formed. On the cathode film, an interlayer insulator film is selectively formed on which an emitter electrode is formed. A semiconductor device such as an IGBT is obtained with a high rate of acceptable products, an excellent on-voltage to turn-off loss tradeoff and an excellent on-voltage to breakdown voltage tradeoff.

Abstract: In an insulated gate semiconductor device (1) having an N? type base region (11), P+ type collector regions (12), P type base regions (13), and N+type emitter regions (14), an N+ type collector-short region (15) which extends toward the N? type base region (11) farther than the P+ type collector regions (12) is formed in the lower surface of the N? type base region (11), and a P+ type semiconductor region (16) is formed between the N+ type collector-short region (15) and the N? type base region (11).

Abstract: The semiconductor device according to one of the aspects of the present invention includes a semiconductor substrate of a first conductivity type, having upper and lower surfaces. A collector region of a second conductivity type is formed on the lower surface of the semiconductor substrate, and a collector electrode is formed on the collector region. Also, at least one pair of isolation regions of the second conductivity type are formed extending from the upper surface of the semiconductor substrate to the collector layer for defining a drift region of the first conductivity type, in conjunction with the collector region. A base region of the second conductivity type is formed adjacent the upper surface of the semiconductor substrate and within the drift region, and an emitter region of the first conductivity type is formed adjacent the upper surface of the semiconductor substrate and within the base region. A gate electrode is formed opposing to the base region via an insulating layer.

Abstract: A memory structure having a vertically oriented access transistor with an annular gate region and a method for fabricating the structure. More specifically, a transistor is fabricated such that the channel of the transistor extends outward with respect to the surface of the substrate. An annular gate is fabricated around the vertical channel such that it partially or completely surrounds the channel. A buried annular bitline may also be implemented. After the vertically oriented transistor is fabricated with the annular gate, a storage device may be fabricated over the transistor to provide a memory cell.

Abstract: In a vertical-type metal insulator field effect transistor device having a first conductivity type drain region layer, a plurality of second conductivity type base regions are produced and arranged in the first conductivity type drain region layer, and a first conductivity type source region is produced in each of the second conductivity type base regions. Both a gate insulating layer and a gate electrode layer are formed on the first conductivity type drain region layer such that a plurality of unit transistor cells are produced in conjunction with the second conductivity type base regions and the first conductivity type source regions, and each of the unit transistor cells includes respective span portions of the gate insulating layer and the gate electrode layer, which bridge a space between the first conductivity type source regions formed in two adjacent second conductivity base regions.