Abstract: According an embodiment, an electrostatic discharge protection structure includes: a semiconductor layer doped with a dopant of a first doping type, a first well region extending from a surface of the semiconductor layer into the semiconductor layer, wherein the first well region is doped with a dopant of a second doping type opposite the first doping type; a second well region next to the first well region and extending from the surface of the semiconductor layer into the semiconductor layer, wherein the second well region is doped with a dopant of the first doping type; an isolation structure extending from the surface of the semiconductor layer into the semiconductor layer with a depth similar to the depth of at least one of the first well region or the second well region, wherein the isolation structure is arranged laterally adjacent to the first well region and the second well region.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a top surface. The semiconductor device structure includes a first pillar structure over the substrate. The first pillar structure includes a first heavily n-doped layer, a first p-doped layer, an n-doped layer, and a first heavily p-doped layer, which are sequentially stacked together. The first pillar structure extends in a direction away from the substrate.

Abstract: A semiconductor device includes a P-type semiconductor substrate, a first N-well, a second N-well, and a P-well adjoining the first and second N-wells, a first doped region having a first conductivity type within the first N-well, a second doped region having a second conductivity type bridging the first N-well and the P-well, a third N+ doped region bridging the second N-well and the P-well, a fourth P+ doped region within the second N-well and spaced apart from the third N+ doped region, and a gate structure formed on the surface of the P-well and between the second doped region and the third N+ doped region. The gate structure, the second doped region, and the third N+ doped region form an NMOS structure. The semiconductor device is a low voltage triggered SCR having a relatively small silicon area and high holding voltage.

Abstract: An SRAM cell is formed of FDSOI-type NMOS and PMOS transistors. A doped well extends under the NMOS and PMOS transistors and is separated therefrom by an insulating layer. A bias voltage is applied to the doped well. The applied bias voltage is adjusted according to a state of the memory cell. For example, a temperature of the memory cell is sensed and the bias voltage adjusted as a function of the sensed temperature. The adjustment in the bias voltage is configured so that threshold voltages of the NMOS and PMOS transistors are substantially equal to n and p target threshold voltages, respectively.

Abstract: Device structures, fabrication methods, operating methods, and design structures for a silicon controlled rectifier. The method includes applying a mechanical stress to a region of a silicon controlled rectifier (SCR) at a level sufficient to modulate a trigger current of the SCR. The device and design structures include a SCR with an anode, a cathode, a first region, and a second region of opposite conductivity type to the first region. The first and second regions of the SCR are disposed in a current-carrying path between the anode and cathode of the SCR. A layer is positioned on a top surface of a semiconductor substrate relative to the first region and configured to cause a mechanical stress in the first region of the SCR at a level sufficient to modulate a trigger current of the SCR.

Abstract: The present invention provides a device for electrostatic discharge and the method of manufacturing thereof. P-well is formed on the substrate, and a first N+ doped region, a second N+ doped region and a P+ doped region are formed in the P-well; both ends of each doped region adopt shallow trench isolation for isolation. A lightly doped source-drain region portion is formed between the first N+ doped region and the shallow trench isolation connected thereto. Under the source-drain region, a halo injection with an inverse type is formed. The reverse conduction voltage of the collector of the bipolar transistor is lowered through the introduction of special doped region and the adoption of lightly doped source-drain technology for manufacturing the source-drain region as well as the manufacturing of halo injection with inverse type under the source-drain region, thus reducing the trigger voltage of the device.

Abstract: Some aspects relate to a semiconductor device disposed on a semiconductor substrate. The device includes an STI region that laterally surrounds a base portion of a semiconductor fin. An anode region, which has a first conductivity type, and a cathode region, which has a second conductivity type, are arranged in an upper portion of the semiconductor fin. A first doped base region, which has the second conductivity type, is arranged in the base of the fin underneath the anode region. A second doped base region, which has the first conductivity type, is arranged in the base of the fin underneath the cathode region. A current control unit is arranged between the anode region and the cathode region. The current control unit is arranged to selectively enable and disable current flow in the upper portion of the fin based on a trigger signal. Other devices and methods are also disclosed.

Abstract: An integrated circuit comprising electro-static discharge (ESD) protection circuitry arranged to provide ESD protection to an external terminal of the integrated circuit. The ESD protection circuitry comprises: a thyristor circuit comprising a first bipolar switching device operably coupled to the external terminal and a second bipolar switching device operably coupled to another external terminal, a collector of the first bipolar switching device being coupled to a base of the second bipolar switching device and a base of the first bipolar switching device being coupled to a collector of the second bipolar switching device. A third bipolar switching device is also provided and operably coupled to the thyristor circuit and has a threshold voltage for triggering the thyristor circuit, the threshold voltage being independently configurable of the thyristor circuit.

Abstract: A device includes a dielectric layer, and a heavily doped semiconductor layer over the dielectric layer. The heavily doped semiconductor layer is of a first conductivity type. A semiconductor region is over the heavily doped semiconductor layer, wherein the semiconductor region is of a second conductivity type opposite the first conductivity type. A Lateral Insulated Gate Bipolar Transistor (LIGBT) is disposed at a surface of the semiconductor region.

Abstract: Device structures, fabrication methods, operating methods, and design structures for a silicon controlled rectifier. The method includes applying a mechanical stress to a region of a silicon controlled rectifier (SCR) at a level sufficient to modulate a trigger current of the SCR. The device and design structures include a SCR with an anode, a cathode, a first region, and a second region of opposite conductivity type to the first region. The first and second regions of the SCR are disposed in a current-carrying path between the anode and cathode of the SCR. A layer is positioned on a top surface of a semiconductor substrate relative to the first region and configured to cause a mechanical stress in the first region of the SCR at a level sufficient to modulate a trigger current of the SCR.

Abstract: An embodiment of a power device having a first current-conduction terminal, a second current-conduction terminal, a control terminal receiving, in use, a control voltage of the power device, and a thyristor device and a first insulated-gate switch device coupled in series between the first and the second conduction terminals; the first insulated-gate switch device has a gate terminal coupled to the control terminal, and the thyristor device has a base terminal. The power device is further provided with: a second insulated-gate switch device, coupled between the first current-conduction terminal and the base terminal of the thyristor device, and having a respective gate terminal coupled to the control terminal; and a Zener diode, coupled between the base terminal of the thyristor device and the second current-conduction terminal so as to enable extraction of current from the base terminal in a given operating condition.

Abstract: Device structures and design structures for a silicon controlled rectifier, as well as methods for fabricating a silicon controlled rectifier. The device structure includes first and second layers of different materials disposed on a top surface of a device region containing first and second p-n junctions of the silicon controlled rectifier. The first layer is laterally positioned on the top surface in vertical alignment with the first p-n junction. The second layer is laterally positioned on the top surface of the device region in vertical alignment with the second p-n junction. The material comprising the second layer has a higher electrical resistivity than the material comprising the first layer.

Abstract: A thyristor based semiconductor device includes a thyristor having cathode, P-base, N-base and anode regions disposed in electrical series relationship. The N-base region for the thyristor has a cross-section that defines an inverted “T” shape, wherein a buried well in semiconductor material forms is operable as a part of the N-base. The stem to the inverted “T” shape extends from the upper surface of the semiconductor material to the buried well. The P-base region for the thyristor extends laterally outward from a side of the stem that is opposite the anode region of the thyristor, and is further bounded between the buried well and a surface of the semiconductor material. A thinned portion for the N-base is defined between the cathode region of the thyristor and the buried well, and may include supplemental dopant of concentration greater than that for some other portion of the N-base.

Abstract: Methods of forming polarity dependent switches for resistive sense memory are described. Methods for forming a memory unit include implanting dopant material more heavily in a source contact than a bit contact of a semiconductor transistor, and electrically connecting a resistive sense memory cell to the bit contact. The resistive sense memory cell is configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell.

Abstract: Formation of a thyristor-based memory cell is described. A first gate dielectric of the storage element is formed over a base region thereof located in a silicon layer. A transistor is coupled to the storage element via a cathode region located in the silicon layer. The transistor has a gate electrode formed over a second gate dielectric. A spacer is formed at least in part along a sidewall of the gate electrode facing a gate electrode of the storage element. A shallow implant region is formed in the silicon layer responsive at least in part to the spacer. The spacer offsets the shallow implant region from the sidewall. A portion of the shallow implant region is for an extension region. The first gate dielectric and the second gate dielectric are formed at least in part by deposition of a dielectric material.

Abstract: In a method for producing an electronic component, a first doped connection region and a second doped connection region are formed on or above a substrate; a body region is formed between the first doped connection region and the second doped connection region; at least two gate regions separate from one another are formed on or above the body region; at least one partial region of the body region is doped by means of introducing dopant atoms, wherein the dopant atoms are introduced into the at least one partial region of the body region through at least one intermediate region formed between the at least two separate gate regions.

Abstract: A semiconductor component including a short-circuit structure. One embodiment provides a semiconductor component having a semiconductor body composed of doped semiconductor material. The semiconductor body includes a first zone of a first conduction type and a second zone of a second conduction type, complementary to the first conduction type, the second zone adjoining the first zone. The first zone and the second zone are coupled to an electrically highly conductive layer. A connection zone of the second conduction type is arranged between the second zone and the electrically highly conductive layer.

Abstract: One aspect of the present subject matter relates to a memory cell, or more specifically, to a scalable GLTRAM cell that provides DRAM-like density and SRAM-like performance. According to various embodiments, the memory cell includes an access transistor and a gated, lateral thyristor integrally formed above the access transistor. The access transistor has a drain region, a raised source region, and a gate. The thyristor has a first end that is formed with the raised source region of the access transistor. In various embodiments, the lateral thyristor is fabricated using a metal-induced lateral crystallization technique (MILC) adopted for thin-film-transistor (TFT) technology. In various embodiments, the stacked lateral thyristor is integrated by raising the source region of the access transistor using a selective epitaxy process for raised source-drain technology. Other aspects are provided herein.

Abstract: A thyristor-based semiconductor device includes a thyristor body that has at least one region in the substrate and a thyristor control port in a trenched region of the device substrate. According to an example embodiment of the present invention, the trench is at least partially filled with a dielectric material and a control port adapted to capacitively couple to the at least one thyristor body region in the substrate. In a more specific implementation, the dielectric material includes deposited dielectric material that is adapted to exhibit resistance to voltage-induced stress that thermally-grown dielectric materials generally exhibit. In another implementation, the dielectric material includes thermally-grown dielectric material, and when used in connection with highly-doped material in the trench, grows faster on the highly-doped material than on a sidewall of the trench that faces the at least on thyristor body region in the substrate.

Abstract: In a method for producing an electronic component, a first doped connection region and a second doped connection region are formed on or above a substrate; a body region is formed between the first doped connection region and the second doped connection region; at least two gate regions separate from one another are formed on or above the body region; at least one partial region of the body region is doped by means of introducing dopant atoms, wherein the dopant atoms are introduced into the at least one partial region of the body region through at least one intermediate region formed between the at least two separate gate regions.