Other Device Being A Controlling Device Of The Field-effect-type (epo) Patents (Class 257/E21.391)
  • Patent number: 8236624
    Abstract: In a method for producing an electronic component, a first doped connection region and a second doped connection region are formed on or above a substrate; a body region is formed between the first doped connection region and the second doped connection region; at least two gate regions separate from one another are formed on or above the body region; at least one partial region of the body region is doped by means of introducing dopant atoms, wherein the dopant atoms are introduced into the at least one partial region of the body region through at least one intermediate region formed between the at least two separate gate regions.
    Type: Grant
    Filed: November 18, 2009
    Date of Patent: August 7, 2012
    Assignee: Infineon Technologies AG
    Inventors: Harald Gossner, Thomas Schulz, Christian Russ, Gerhard Knoblinger
  • Publication number: 20120091501
    Abstract: In a DIAC-like device that includes an n+ and a p+ region connected to the high voltage node, and an n+ and a p+ region connected to the low voltage node, at least two MOS devices are formed between the n+ and p+ region connected to the high voltage node, and the n+ and p+ region connected to the low voltage node.
    Type: Application
    Filed: October 18, 2010
    Publication date: April 19, 2012
    Inventors: Vladislav Vashchenko, Antonio Gallerano, Peter J. Hopper
  • Patent number: 7910949
    Abstract: A power semiconductor device includes a conductive board and a switching element mounted on the conductive board and electrically connected thereto. The power semiconductor device also includes an integrated circuit mounted on the conductive board at a distance from the switching element and electrically connected thereto. The switching element turns ON/OFF a connection between first and second main electrodes in response to a control signal inputted to a control electrode. The integrated circuit includes a control circuit which controls ON/OFF the switching element and a back side voltage detection element which detects a voltage of the back side of the integrated circuit.
    Type: Grant
    Filed: October 10, 2007
    Date of Patent: March 22, 2011
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yukio Yasuda, Atsunobu Kawamoto, Shinsuke Goudo
  • Publication number: 20100062573
    Abstract: In a method for producing an electronic component, a first doped connection region and a second doped connection region are formed on or above a substrate; a body region is formed between the first doped connection region and the second doped connection region; at least two gate regions separate from one another are formed on or above the body region; at least one partial region of the body region is doped by means of introducing dopant atoms, wherein the dopant atoms are introduced into the at least one partial region of the body region through at least one intermediate region formed between the at least two separate gate regions.
    Type: Application
    Filed: November 18, 2009
    Publication date: March 11, 2010
    Inventors: Harald Gossner, Thomas Schulz, Christian Russ, Gerhard Knoblinger
  • Patent number: 7504286
    Abstract: A method is provided for fabricating a memory device. A semiconductor substrate is provided which includes a first well region having a first conductivity type, a second well region having the first conductivity type, a first gate structure overlying the first well region and the second gate structure overlying the second well region. An insulating material layer is conformally deposited overlying exposed portions of the semiconductor substrate. Photosensitive material is provided over a portion of the insulating material layer which overlies a portion of the second well region. The photosensitive material exposes portions of the insulating material layer. The exposed portions of the insulating material layer are anisotropically etched to provide a sidewall spacer adjacent a first sidewall of the second gate structure, and an insulating spacer block formed overlying a portion of the second gate structure and adjacent a second sidewall of the second gate structure.
    Type: Grant
    Filed: March 28, 2007
    Date of Patent: March 17, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Hyun-Jin Cho